This source file includes following definitions.
- spfi_readl
- spfi_writel
- spfi_start
- spfi_reset
- spfi_wait_all_done
- spfi_pio_write32
- spfi_pio_write8
- spfi_pio_read32
- spfi_pio_read8
- img_spfi_start_pio
- img_spfi_dma_rx_cb
- img_spfi_dma_tx_cb
- img_spfi_start_dma
- img_spfi_handle_err
- img_spfi_prepare
- img_spfi_unprepare
- img_spfi_setup
- img_spfi_cleanup
- img_spfi_config
- img_spfi_transfer_one
- img_spfi_can_dma
- img_spfi_irq
- img_spfi_probe
- img_spfi_remove
- img_spfi_runtime_suspend
- img_spfi_runtime_resume
- img_spfi_suspend
- img_spfi_resume
1
2
3
4
5
6
7
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/gpio.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/scatterlist.h>
21 #include <linux/slab.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spinlock.h>
24
25 #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
26 #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
27 #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
28 #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
29 #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
30 #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
31 #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
32 #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
33 #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
34
35 #define SPFI_CONTROL 0x14
36 #define SPFI_CONTROL_CONTINUE BIT(12)
37 #define SPFI_CONTROL_SOFT_RESET BIT(11)
38 #define SPFI_CONTROL_SEND_DMA BIT(10)
39 #define SPFI_CONTROL_GET_DMA BIT(9)
40 #define SPFI_CONTROL_SE BIT(8)
41 #define SPFI_CONTROL_TMODE_SHIFT 5
42 #define SPFI_CONTROL_TMODE_MASK 0x7
43 #define SPFI_CONTROL_TMODE_SINGLE 0
44 #define SPFI_CONTROL_TMODE_DUAL 1
45 #define SPFI_CONTROL_TMODE_QUAD 2
46 #define SPFI_CONTROL_SPFI_EN BIT(0)
47
48 #define SPFI_TRANSACTION 0x18
49 #define SPFI_TRANSACTION_TSIZE_SHIFT 16
50 #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
51
52 #define SPFI_PORT_STATE 0x1c
53 #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
54 #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
55 #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
56 #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
57
58 #define SPFI_TX_32BIT_VALID_DATA 0x20
59 #define SPFI_TX_8BIT_VALID_DATA 0x24
60 #define SPFI_RX_32BIT_VALID_DATA 0x28
61 #define SPFI_RX_8BIT_VALID_DATA 0x2c
62
63 #define SPFI_INTERRUPT_STATUS 0x30
64 #define SPFI_INTERRUPT_ENABLE 0x34
65 #define SPFI_INTERRUPT_CLEAR 0x38
66 #define SPFI_INTERRUPT_IACCESS BIT(12)
67 #define SPFI_INTERRUPT_GDEX8BIT BIT(11)
68 #define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
69 #define SPFI_INTERRUPT_GDFUL BIT(8)
70 #define SPFI_INTERRUPT_GDHF BIT(7)
71 #define SPFI_INTERRUPT_GDEX32BIT BIT(6)
72 #define SPFI_INTERRUPT_GDTRIG BIT(5)
73 #define SPFI_INTERRUPT_SDFUL BIT(3)
74 #define SPFI_INTERRUPT_SDHF BIT(2)
75 #define SPFI_INTERRUPT_SDE BIT(1)
76 #define SPFI_INTERRUPT_SDTRIG BIT(0)
77
78
79
80
81
82
83
84
85 #define SPFI_32BIT_FIFO_SIZE 64
86 #define SPFI_8BIT_FIFO_SIZE 16
87
88 struct img_spfi {
89 struct device *dev;
90 struct spi_master *master;
91 spinlock_t lock;
92
93 void __iomem *regs;
94 phys_addr_t phys;
95 int irq;
96 struct clk *spfi_clk;
97 struct clk *sys_clk;
98
99 struct dma_chan *rx_ch;
100 struct dma_chan *tx_ch;
101 bool tx_dma_busy;
102 bool rx_dma_busy;
103 };
104
105 struct img_spfi_device_data {
106 bool gpio_requested;
107 };
108
109 static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
110 {
111 return readl(spfi->regs + reg);
112 }
113
114 static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
115 {
116 writel(val, spfi->regs + reg);
117 }
118
119 static inline void spfi_start(struct img_spfi *spfi)
120 {
121 u32 val;
122
123 val = spfi_readl(spfi, SPFI_CONTROL);
124 val |= SPFI_CONTROL_SPFI_EN;
125 spfi_writel(spfi, val, SPFI_CONTROL);
126 }
127
128 static inline void spfi_reset(struct img_spfi *spfi)
129 {
130 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
131 spfi_writel(spfi, 0, SPFI_CONTROL);
132 }
133
134 static int spfi_wait_all_done(struct img_spfi *spfi)
135 {
136 unsigned long timeout = jiffies + msecs_to_jiffies(50);
137
138 while (time_before(jiffies, timeout)) {
139 u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
140
141 if (status & SPFI_INTERRUPT_ALLDONETRIG) {
142 spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
143 SPFI_INTERRUPT_CLEAR);
144 return 0;
145 }
146 cpu_relax();
147 }
148
149 dev_err(spfi->dev, "Timed out waiting for transaction to complete\n");
150 spfi_reset(spfi);
151
152 return -ETIMEDOUT;
153 }
154
155 static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
156 unsigned int max)
157 {
158 unsigned int count = 0;
159 u32 status;
160
161 while (count < max / 4) {
162 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
163 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
164 if (status & SPFI_INTERRUPT_SDFUL)
165 break;
166 spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
167 count++;
168 }
169
170 return count * 4;
171 }
172
173 static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
174 unsigned int max)
175 {
176 unsigned int count = 0;
177 u32 status;
178
179 while (count < max) {
180 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
181 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
182 if (status & SPFI_INTERRUPT_SDFUL)
183 break;
184 spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
185 count++;
186 }
187
188 return count;
189 }
190
191 static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
192 unsigned int max)
193 {
194 unsigned int count = 0;
195 u32 status;
196
197 while (count < max / 4) {
198 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
199 SPFI_INTERRUPT_CLEAR);
200 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
201 if (!(status & SPFI_INTERRUPT_GDEX32BIT))
202 break;
203 buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
204 count++;
205 }
206
207 return count * 4;
208 }
209
210 static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
211 unsigned int max)
212 {
213 unsigned int count = 0;
214 u32 status;
215
216 while (count < max) {
217 spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
218 SPFI_INTERRUPT_CLEAR);
219 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
220 if (!(status & SPFI_INTERRUPT_GDEX8BIT))
221 break;
222 buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
223 count++;
224 }
225
226 return count;
227 }
228
229 static int img_spfi_start_pio(struct spi_master *master,
230 struct spi_device *spi,
231 struct spi_transfer *xfer)
232 {
233 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
234 unsigned int tx_bytes = 0, rx_bytes = 0;
235 const void *tx_buf = xfer->tx_buf;
236 void *rx_buf = xfer->rx_buf;
237 unsigned long timeout;
238 int ret;
239
240 if (tx_buf)
241 tx_bytes = xfer->len;
242 if (rx_buf)
243 rx_bytes = xfer->len;
244
245 spfi_start(spfi);
246
247 timeout = jiffies +
248 msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
249 while ((tx_bytes > 0 || rx_bytes > 0) &&
250 time_before(jiffies, timeout)) {
251 unsigned int tx_count, rx_count;
252
253 if (tx_bytes >= 4)
254 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
255 else
256 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
257
258 if (rx_bytes >= 4)
259 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
260 else
261 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
262
263 tx_buf += tx_count;
264 rx_buf += rx_count;
265 tx_bytes -= tx_count;
266 rx_bytes -= rx_count;
267
268 cpu_relax();
269 }
270
271 if (rx_bytes > 0 || tx_bytes > 0) {
272 dev_err(spfi->dev, "PIO transfer timed out\n");
273 return -ETIMEDOUT;
274 }
275
276 ret = spfi_wait_all_done(spfi);
277 if (ret < 0)
278 return ret;
279
280 return 0;
281 }
282
283 static void img_spfi_dma_rx_cb(void *data)
284 {
285 struct img_spfi *spfi = data;
286 unsigned long flags;
287
288 spfi_wait_all_done(spfi);
289
290 spin_lock_irqsave(&spfi->lock, flags);
291 spfi->rx_dma_busy = false;
292 if (!spfi->tx_dma_busy)
293 spi_finalize_current_transfer(spfi->master);
294 spin_unlock_irqrestore(&spfi->lock, flags);
295 }
296
297 static void img_spfi_dma_tx_cb(void *data)
298 {
299 struct img_spfi *spfi = data;
300 unsigned long flags;
301
302 spfi_wait_all_done(spfi);
303
304 spin_lock_irqsave(&spfi->lock, flags);
305 spfi->tx_dma_busy = false;
306 if (!spfi->rx_dma_busy)
307 spi_finalize_current_transfer(spfi->master);
308 spin_unlock_irqrestore(&spfi->lock, flags);
309 }
310
311 static int img_spfi_start_dma(struct spi_master *master,
312 struct spi_device *spi,
313 struct spi_transfer *xfer)
314 {
315 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
316 struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
317 struct dma_slave_config rxconf, txconf;
318
319 spfi->rx_dma_busy = false;
320 spfi->tx_dma_busy = false;
321
322 if (xfer->rx_buf) {
323 rxconf.direction = DMA_DEV_TO_MEM;
324 if (xfer->len % 4 == 0) {
325 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
326 rxconf.src_addr_width = 4;
327 rxconf.src_maxburst = 4;
328 } else {
329 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
330 rxconf.src_addr_width = 1;
331 rxconf.src_maxburst = 4;
332 }
333 dmaengine_slave_config(spfi->rx_ch, &rxconf);
334
335 rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
336 xfer->rx_sg.nents,
337 DMA_DEV_TO_MEM,
338 DMA_PREP_INTERRUPT);
339 if (!rxdesc)
340 goto stop_dma;
341
342 rxdesc->callback = img_spfi_dma_rx_cb;
343 rxdesc->callback_param = spfi;
344 }
345
346 if (xfer->tx_buf) {
347 txconf.direction = DMA_MEM_TO_DEV;
348 if (xfer->len % 4 == 0) {
349 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
350 txconf.dst_addr_width = 4;
351 txconf.dst_maxburst = 4;
352 } else {
353 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
354 txconf.dst_addr_width = 1;
355 txconf.dst_maxburst = 4;
356 }
357 dmaengine_slave_config(spfi->tx_ch, &txconf);
358
359 txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
360 xfer->tx_sg.nents,
361 DMA_MEM_TO_DEV,
362 DMA_PREP_INTERRUPT);
363 if (!txdesc)
364 goto stop_dma;
365
366 txdesc->callback = img_spfi_dma_tx_cb;
367 txdesc->callback_param = spfi;
368 }
369
370 if (xfer->rx_buf) {
371 spfi->rx_dma_busy = true;
372 dmaengine_submit(rxdesc);
373 dma_async_issue_pending(spfi->rx_ch);
374 }
375
376 spfi_start(spfi);
377
378 if (xfer->tx_buf) {
379 spfi->tx_dma_busy = true;
380 dmaengine_submit(txdesc);
381 dma_async_issue_pending(spfi->tx_ch);
382 }
383
384 return 1;
385
386 stop_dma:
387 dmaengine_terminate_all(spfi->rx_ch);
388 dmaengine_terminate_all(spfi->tx_ch);
389 return -EIO;
390 }
391
392 static void img_spfi_handle_err(struct spi_master *master,
393 struct spi_message *msg)
394 {
395 struct img_spfi *spfi = spi_master_get_devdata(master);
396 unsigned long flags;
397
398
399
400
401
402 spin_lock_irqsave(&spfi->lock, flags);
403 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
404 spfi->tx_dma_busy = false;
405 spfi->rx_dma_busy = false;
406
407 dmaengine_terminate_all(spfi->tx_ch);
408 dmaengine_terminate_all(spfi->rx_ch);
409 }
410 spin_unlock_irqrestore(&spfi->lock, flags);
411 }
412
413 static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg)
414 {
415 struct img_spfi *spfi = spi_master_get_devdata(master);
416 u32 val;
417
418 val = spfi_readl(spfi, SPFI_PORT_STATE);
419 val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK <<
420 SPFI_PORT_STATE_DEV_SEL_SHIFT);
421 val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
422 if (msg->spi->mode & SPI_CPHA)
423 val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
424 else
425 val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
426 if (msg->spi->mode & SPI_CPOL)
427 val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
428 else
429 val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
430 spfi_writel(spfi, val, SPFI_PORT_STATE);
431
432 return 0;
433 }
434
435 static int img_spfi_unprepare(struct spi_master *master,
436 struct spi_message *msg)
437 {
438 struct img_spfi *spfi = spi_master_get_devdata(master);
439
440 spfi_reset(spfi);
441
442 return 0;
443 }
444
445 static int img_spfi_setup(struct spi_device *spi)
446 {
447 int ret = -EINVAL;
448 struct img_spfi_device_data *spfi_data = spi_get_ctldata(spi);
449
450 if (!spfi_data) {
451 spfi_data = kzalloc(sizeof(*spfi_data), GFP_KERNEL);
452 if (!spfi_data)
453 return -ENOMEM;
454 spfi_data->gpio_requested = false;
455 spi_set_ctldata(spi, spfi_data);
456 }
457 if (!spfi_data->gpio_requested) {
458 ret = gpio_request_one(spi->cs_gpio,
459 (spi->mode & SPI_CS_HIGH) ?
460 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
461 dev_name(&spi->dev));
462 if (ret)
463 dev_err(&spi->dev, "can't request chipselect gpio %d\n",
464 spi->cs_gpio);
465 else
466 spfi_data->gpio_requested = true;
467 } else {
468 if (gpio_is_valid(spi->cs_gpio)) {
469 int mode = ((spi->mode & SPI_CS_HIGH) ?
470 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH);
471
472 ret = gpio_direction_output(spi->cs_gpio, mode);
473 if (ret)
474 dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
475 spi->cs_gpio, ret);
476 }
477 }
478 return ret;
479 }
480
481 static void img_spfi_cleanup(struct spi_device *spi)
482 {
483 struct img_spfi_device_data *spfi_data = spi_get_ctldata(spi);
484
485 if (spfi_data) {
486 if (spfi_data->gpio_requested)
487 gpio_free(spi->cs_gpio);
488 kfree(spfi_data);
489 spi_set_ctldata(spi, NULL);
490 }
491 }
492
493 static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
494 struct spi_transfer *xfer)
495 {
496 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
497 u32 val, div;
498
499
500
501
502
503 div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
504 div = clamp(512 / (1 << get_count_order(div)), 1, 128);
505
506 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
507 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
508 SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
509 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
510 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
511
512 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
513 SPFI_TRANSACTION);
514
515 val = spfi_readl(spfi, SPFI_CONTROL);
516 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
517 if (xfer->tx_buf)
518 val |= SPFI_CONTROL_SEND_DMA;
519 if (xfer->rx_buf)
520 val |= SPFI_CONTROL_GET_DMA;
521 val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
522 if (xfer->tx_nbits == SPI_NBITS_DUAL &&
523 xfer->rx_nbits == SPI_NBITS_DUAL)
524 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
525 else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
526 xfer->rx_nbits == SPI_NBITS_QUAD)
527 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
528 val |= SPFI_CONTROL_SE;
529 spfi_writel(spfi, val, SPFI_CONTROL);
530 }
531
532 static int img_spfi_transfer_one(struct spi_master *master,
533 struct spi_device *spi,
534 struct spi_transfer *xfer)
535 {
536 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
537 int ret;
538
539 if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {
540 dev_err(spfi->dev,
541 "Transfer length (%d) is greater than the max supported (%d)",
542 xfer->len, SPFI_TRANSACTION_TSIZE_MASK);
543 return -EINVAL;
544 }
545
546 img_spfi_config(master, spi, xfer);
547 if (master->can_dma && master->can_dma(master, spi, xfer))
548 ret = img_spfi_start_dma(master, spi, xfer);
549 else
550 ret = img_spfi_start_pio(master, spi, xfer);
551
552 return ret;
553 }
554
555 static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
556 struct spi_transfer *xfer)
557 {
558 if (xfer->len > SPFI_32BIT_FIFO_SIZE)
559 return true;
560 return false;
561 }
562
563 static irqreturn_t img_spfi_irq(int irq, void *dev_id)
564 {
565 struct img_spfi *spfi = (struct img_spfi *)dev_id;
566 u32 status;
567
568 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
569 if (status & SPFI_INTERRUPT_IACCESS) {
570 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
571 dev_err(spfi->dev, "Illegal access interrupt");
572 return IRQ_HANDLED;
573 }
574
575 return IRQ_NONE;
576 }
577
578 static int img_spfi_probe(struct platform_device *pdev)
579 {
580 struct spi_master *master;
581 struct img_spfi *spfi;
582 struct resource *res;
583 int ret;
584 u32 max_speed_hz;
585
586 master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
587 if (!master)
588 return -ENOMEM;
589 platform_set_drvdata(pdev, master);
590
591 spfi = spi_master_get_devdata(master);
592 spfi->dev = &pdev->dev;
593 spfi->master = master;
594 spin_lock_init(&spfi->lock);
595
596 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
597 spfi->regs = devm_ioremap_resource(spfi->dev, res);
598 if (IS_ERR(spfi->regs)) {
599 ret = PTR_ERR(spfi->regs);
600 goto put_spi;
601 }
602 spfi->phys = res->start;
603
604 spfi->irq = platform_get_irq(pdev, 0);
605 if (spfi->irq < 0) {
606 ret = spfi->irq;
607 goto put_spi;
608 }
609 ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
610 IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
611 if (ret)
612 goto put_spi;
613
614 spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
615 if (IS_ERR(spfi->sys_clk)) {
616 ret = PTR_ERR(spfi->sys_clk);
617 goto put_spi;
618 }
619 spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
620 if (IS_ERR(spfi->spfi_clk)) {
621 ret = PTR_ERR(spfi->spfi_clk);
622 goto put_spi;
623 }
624
625 ret = clk_prepare_enable(spfi->sys_clk);
626 if (ret)
627 goto put_spi;
628 ret = clk_prepare_enable(spfi->spfi_clk);
629 if (ret)
630 goto disable_pclk;
631
632 spfi_reset(spfi);
633
634
635
636
637 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
638
639 master->auto_runtime_pm = true;
640 master->bus_num = pdev->id;
641 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
642 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
643 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
644 master->dev.of_node = pdev->dev.of_node;
645 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
646 master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;
647 master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;
648
649
650
651
652
653
654
655
656 if (!of_property_read_u32(spfi->dev->of_node, "spfi-max-frequency",
657 &max_speed_hz)) {
658 if (master->max_speed_hz > max_speed_hz)
659 master->max_speed_hz = max_speed_hz;
660 }
661
662 master->setup = img_spfi_setup;
663 master->cleanup = img_spfi_cleanup;
664 master->transfer_one = img_spfi_transfer_one;
665 master->prepare_message = img_spfi_prepare;
666 master->unprepare_message = img_spfi_unprepare;
667 master->handle_err = img_spfi_handle_err;
668
669 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
670 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
671 if (!spfi->tx_ch || !spfi->rx_ch) {
672 if (spfi->tx_ch)
673 dma_release_channel(spfi->tx_ch);
674 if (spfi->rx_ch)
675 dma_release_channel(spfi->rx_ch);
676 spfi->tx_ch = NULL;
677 spfi->rx_ch = NULL;
678 dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
679 } else {
680 master->dma_tx = spfi->tx_ch;
681 master->dma_rx = spfi->rx_ch;
682 master->can_dma = img_spfi_can_dma;
683 }
684
685 pm_runtime_set_active(spfi->dev);
686 pm_runtime_enable(spfi->dev);
687
688 ret = devm_spi_register_master(spfi->dev, master);
689 if (ret)
690 goto disable_pm;
691
692 return 0;
693
694 disable_pm:
695 pm_runtime_disable(spfi->dev);
696 if (spfi->rx_ch)
697 dma_release_channel(spfi->rx_ch);
698 if (spfi->tx_ch)
699 dma_release_channel(spfi->tx_ch);
700 clk_disable_unprepare(spfi->spfi_clk);
701 disable_pclk:
702 clk_disable_unprepare(spfi->sys_clk);
703 put_spi:
704 spi_master_put(master);
705
706 return ret;
707 }
708
709 static int img_spfi_remove(struct platform_device *pdev)
710 {
711 struct spi_master *master = platform_get_drvdata(pdev);
712 struct img_spfi *spfi = spi_master_get_devdata(master);
713
714 if (spfi->tx_ch)
715 dma_release_channel(spfi->tx_ch);
716 if (spfi->rx_ch)
717 dma_release_channel(spfi->rx_ch);
718
719 pm_runtime_disable(spfi->dev);
720 if (!pm_runtime_status_suspended(spfi->dev)) {
721 clk_disable_unprepare(spfi->spfi_clk);
722 clk_disable_unprepare(spfi->sys_clk);
723 }
724
725 return 0;
726 }
727
728 #ifdef CONFIG_PM
729 static int img_spfi_runtime_suspend(struct device *dev)
730 {
731 struct spi_master *master = dev_get_drvdata(dev);
732 struct img_spfi *spfi = spi_master_get_devdata(master);
733
734 clk_disable_unprepare(spfi->spfi_clk);
735 clk_disable_unprepare(spfi->sys_clk);
736
737 return 0;
738 }
739
740 static int img_spfi_runtime_resume(struct device *dev)
741 {
742 struct spi_master *master = dev_get_drvdata(dev);
743 struct img_spfi *spfi = spi_master_get_devdata(master);
744 int ret;
745
746 ret = clk_prepare_enable(spfi->sys_clk);
747 if (ret)
748 return ret;
749 ret = clk_prepare_enable(spfi->spfi_clk);
750 if (ret) {
751 clk_disable_unprepare(spfi->sys_clk);
752 return ret;
753 }
754
755 return 0;
756 }
757 #endif
758
759 #ifdef CONFIG_PM_SLEEP
760 static int img_spfi_suspend(struct device *dev)
761 {
762 struct spi_master *master = dev_get_drvdata(dev);
763
764 return spi_master_suspend(master);
765 }
766
767 static int img_spfi_resume(struct device *dev)
768 {
769 struct spi_master *master = dev_get_drvdata(dev);
770 struct img_spfi *spfi = spi_master_get_devdata(master);
771 int ret;
772
773 ret = pm_runtime_get_sync(dev);
774 if (ret)
775 return ret;
776 spfi_reset(spfi);
777 pm_runtime_put(dev);
778
779 return spi_master_resume(master);
780 }
781 #endif
782
783 static const struct dev_pm_ops img_spfi_pm_ops = {
784 SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
785 NULL)
786 SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
787 };
788
789 static const struct of_device_id img_spfi_of_match[] = {
790 { .compatible = "img,spfi", },
791 { },
792 };
793 MODULE_DEVICE_TABLE(of, img_spfi_of_match);
794
795 static struct platform_driver img_spfi_driver = {
796 .driver = {
797 .name = "img-spfi",
798 .pm = &img_spfi_pm_ops,
799 .of_match_table = of_match_ptr(img_spfi_of_match),
800 },
801 .probe = img_spfi_probe,
802 .remove = img_spfi_remove,
803 };
804 module_platform_driver(img_spfi_driver);
805
806 MODULE_DESCRIPTION("IMG SPFI controller driver");
807 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
808 MODULE_LICENSE("GPL v2");