drivers/spi/spi-fsl-qspi.c

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This source file includes following definitions.
needs_swap_endian
needs_4x_clock
needs_fill_txfifo
needs_wakeup_wait_mode
needs_amba_base_offset
needs_tdh_setting
fsl_qspi_endian_xchg
qspi_writel
qspi_readl
fsl_qspi_irq_handler
fsl_qspi_check_buswidth
fsl_qspi_supports_op
fsl_qspi_prepare_lut
fsl_qspi_clk_prep_enable
fsl_qspi_clk_disable_unprep
fsl_qspi_invalidate
fsl_qspi_select_mem
fsl_qspi_read_ahb
fsl_qspi_fill_txfifo
fsl_qspi_read_rxfifo
fsl_qspi_do_op
fsl_qspi_readl_poll_tout
fsl_qspi_exec_op
fsl_qspi_adjust_op_size
fsl_qspi_default_setup
fsl_qspi_get_name
fsl_qspi_probe
fsl_qspi_remove
fsl_qspi_suspend
fsl_qspi_resume
   1 // SPDX-License-Identifier: GPL-2.0+
   2 
   3 /*
   4  * Freescale QuadSPI driver.
   5  *
   6  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   7  * Copyright (C) 2018 Bootlin
   8  * Copyright (C) 2018 exceet electronics GmbH
   9  * Copyright (C) 2018 Kontron Electronics GmbH
  10  *
  11  * Transition to SPI MEM interface:
  12  * Authors:
  13  *     Boris Brezillon <bbrezillon@kernel.org>
  14  *     Frieder Schrempf <frieder.schrempf@kontron.de>
  15  *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  16  *     Suresh Gupta <suresh.gupta@nxp.com>
  17  *
  18  * Based on the original fsl-quadspi.c spi-nor driver:
  19  * Author: Freescale Semiconductor, Inc.
  20  *
  21  */
  22 
  23 #include <linux/bitops.h>
  24 #include <linux/clk.h>
  25 #include <linux/completion.h>
  26 #include <linux/delay.h>
  27 #include <linux/err.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/iopoll.h>
  32 #include <linux/jiffies.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/mutex.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/pm_qos.h>
  40 #include <linux/sizes.h>
  41 
  42 #include <linux/spi/spi.h>
  43 #include <linux/spi/spi-mem.h>
  44 
  45 /*
  46  * The driver only uses one single LUT entry, that is updated on
  47  * each call of exec_op(). Index 0 is preset at boot with a basic
  48  * read operation, so let's use the last entry (15).
  49  */
  50 #define SEQID_LUT                       15
  51 
  52 /* Registers used by the driver */
  53 #define QUADSPI_MCR                     0x00
  54 #define QUADSPI_MCR_RESERVED_MASK       GENMASK(19, 16)
  55 #define QUADSPI_MCR_MDIS_MASK           BIT(14)
  56 #define QUADSPI_MCR_CLR_TXF_MASK        BIT(11)
  57 #define QUADSPI_MCR_CLR_RXF_MASK        BIT(10)
  58 #define QUADSPI_MCR_DDR_EN_MASK         BIT(7)
  59 #define QUADSPI_MCR_END_CFG_MASK        GENMASK(3, 2)
  60 #define QUADSPI_MCR_SWRSTHD_MASK        BIT(1)
  61 #define QUADSPI_MCR_SWRSTSD_MASK        BIT(0)
  62 
  63 #define QUADSPI_IPCR                    0x08
  64 #define QUADSPI_IPCR_SEQID(x)           ((x) << 24)
  65 
  66 #define QUADSPI_FLSHCR                  0x0c
  67 #define QUADSPI_FLSHCR_TCSS_MASK        GENMASK(3, 0)
  68 #define QUADSPI_FLSHCR_TCSH_MASK        GENMASK(11, 8)
  69 #define QUADSPI_FLSHCR_TDH_MASK         GENMASK(17, 16)
  70 
  71 #define QUADSPI_BUF3CR                  0x1c
  72 #define QUADSPI_BUF3CR_ALLMST_MASK      BIT(31)
  73 #define QUADSPI_BUF3CR_ADATSZ(x)        ((x) << 8)
  74 #define QUADSPI_BUF3CR_ADATSZ_MASK      GENMASK(15, 8)
  75 
  76 #define QUADSPI_BFGENCR                 0x20
  77 #define QUADSPI_BFGENCR_SEQID(x)        ((x) << 12)
  78 
  79 #define QUADSPI_BUF0IND                 0x30
  80 #define QUADSPI_BUF1IND                 0x34
  81 #define QUADSPI_BUF2IND                 0x38
  82 #define QUADSPI_SFAR                    0x100
  83 
  84 #define QUADSPI_SMPR                    0x108
  85 #define QUADSPI_SMPR_DDRSMP_MASK        GENMASK(18, 16)
  86 #define QUADSPI_SMPR_FSDLY_MASK         BIT(6)
  87 #define QUADSPI_SMPR_FSPHS_MASK         BIT(5)
  88 #define QUADSPI_SMPR_HSENA_MASK         BIT(0)
  89 
  90 #define QUADSPI_RBCT                    0x110
  91 #define QUADSPI_RBCT_WMRK_MASK          GENMASK(4, 0)
  92 #define QUADSPI_RBCT_RXBRD_USEIPS       BIT(8)
  93 
  94 #define QUADSPI_TBDR                    0x154
  95 
  96 #define QUADSPI_SR                      0x15c
  97 #define QUADSPI_SR_IP_ACC_MASK          BIT(1)
  98 #define QUADSPI_SR_AHB_ACC_MASK         BIT(2)
  99 
 100 #define QUADSPI_FR                      0x160
 101 #define QUADSPI_FR_TFF_MASK             BIT(0)
 102 
 103 #define QUADSPI_RSER                    0x164
 104 #define QUADSPI_RSER_TFIE               BIT(0)
 105 
 106 #define QUADSPI_SPTRCLR                 0x16c
 107 #define QUADSPI_SPTRCLR_IPPTRC          BIT(8)
 108 #define QUADSPI_SPTRCLR_BFPTRC          BIT(0)
 109 
 110 #define QUADSPI_SFA1AD                  0x180
 111 #define QUADSPI_SFA2AD                  0x184
 112 #define QUADSPI_SFB1AD                  0x188
 113 #define QUADSPI_SFB2AD                  0x18c
 114 #define QUADSPI_RBDR(x)                 (0x200 + ((x) * 4))
 115 
 116 #define QUADSPI_LUTKEY                  0x300
 117 #define QUADSPI_LUTKEY_VALUE            0x5AF05AF0
 118 
 119 #define QUADSPI_LCKCR                   0x304
 120 #define QUADSPI_LCKER_LOCK              BIT(0)
 121 #define QUADSPI_LCKER_UNLOCK            BIT(1)
 122 
 123 #define QUADSPI_LUT_BASE                0x310
 124 #define QUADSPI_LUT_OFFSET              (SEQID_LUT * 4 * 4)
 125 #define QUADSPI_LUT_REG(idx) \
 126         (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
 127 
 128 /* Instruction set for the LUT register */
 129 #define LUT_STOP                0
 130 #define LUT_CMD                 1
 131 #define LUT_ADDR                2
 132 #define LUT_DUMMY               3
 133 #define LUT_MODE                4
 134 #define LUT_MODE2               5
 135 #define LUT_MODE4               6
 136 #define LUT_FSL_READ            7
 137 #define LUT_FSL_WRITE           8
 138 #define LUT_JMP_ON_CS           9
 139 #define LUT_ADDR_DDR            10
 140 #define LUT_MODE_DDR            11
 141 #define LUT_MODE2_DDR           12
 142 #define LUT_MODE4_DDR           13
 143 #define LUT_FSL_READ_DDR        14
 144 #define LUT_FSL_WRITE_DDR       15
 145 #define LUT_DATA_LEARN          16
 146 
 147 /*
 148  * The PAD definitions for LUT register.
 149  *
 150  * The pad stands for the number of IO lines [0:3].
 151  * For example, the quad read needs four IO lines,
 152  * so you should use LUT_PAD(4).
 153  */
 154 #define LUT_PAD(x) (fls(x) - 1)
 155 
 156 /*
 157  * Macro for constructing the LUT entries with the following
 158  * register layout:
 159  *
 160  *  ---------------------------------------------------
 161  *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
 162  *  ---------------------------------------------------
 163  */
 164 #define LUT_DEF(idx, ins, pad, opr)                                     \
 165         ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
 166 
 167 /* Controller needs driver to swap endianness */
 168 #define QUADSPI_QUIRK_SWAP_ENDIAN       BIT(0)
 169 
 170 /* Controller needs 4x internal clock */
 171 #define QUADSPI_QUIRK_4X_INT_CLK        BIT(1)
 172 
 173 /*
 174  * TKT253890, the controller needs the driver to fill the txfifo with
 175  * 16 bytes at least to trigger a data transfer, even though the extra
 176  * data won't be transferred.
 177  */
 178 #define QUADSPI_QUIRK_TKT253890         BIT(2)
 179 
 180 /* TKT245618, the controller cannot wake up from wait mode */
 181 #define QUADSPI_QUIRK_TKT245618         BIT(3)
 182 
 183 /*
 184  * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
 185  * internally. No need to add it when setting SFXXAD and SFAR registers
 186  */
 187 #define QUADSPI_QUIRK_BASE_INTERNAL     BIT(4)
 188 
 189 /*
 190  * Controller uses TDH bits in register QUADSPI_FLSHCR.
 191  * They need to be set in accordance with the DDR/SDR mode.
 192  */
 193 #define QUADSPI_QUIRK_USE_TDH_SETTING   BIT(5)
 194 
 195 struct fsl_qspi_devtype_data {
 196         unsigned int rxfifo;
 197         unsigned int txfifo;
 198         unsigned int ahb_buf_size;
 199         unsigned int quirks;
 200         bool little_endian;
 201 };
 202 
 203 static const struct fsl_qspi_devtype_data vybrid_data = {
 204         .rxfifo = SZ_128,
 205         .txfifo = SZ_64,
 206         .ahb_buf_size = SZ_1K,
 207         .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
 208         .little_endian = true,
 209 };
 210 
 211 static const struct fsl_qspi_devtype_data imx6sx_data = {
 212         .rxfifo = SZ_128,
 213         .txfifo = SZ_512,
 214         .ahb_buf_size = SZ_1K,
 215         .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
 216         .little_endian = true,
 217 };
 218 
 219 static const struct fsl_qspi_devtype_data imx7d_data = {
 220         .rxfifo = SZ_128,
 221         .txfifo = SZ_512,
 222         .ahb_buf_size = SZ_1K,
 223         .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
 224                   QUADSPI_QUIRK_USE_TDH_SETTING,
 225         .little_endian = true,
 226 };
 227 
 228 static const struct fsl_qspi_devtype_data imx6ul_data = {
 229         .rxfifo = SZ_128,
 230         .txfifo = SZ_512,
 231         .ahb_buf_size = SZ_1K,
 232         .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
 233                   QUADSPI_QUIRK_USE_TDH_SETTING,
 234         .little_endian = true,
 235 };
 236 
 237 static const struct fsl_qspi_devtype_data ls1021a_data = {
 238         .rxfifo = SZ_128,
 239         .txfifo = SZ_64,
 240         .ahb_buf_size = SZ_1K,
 241         .quirks = 0,
 242         .little_endian = false,
 243 };
 244 
 245 static const struct fsl_qspi_devtype_data ls2080a_data = {
 246         .rxfifo = SZ_128,
 247         .txfifo = SZ_64,
 248         .ahb_buf_size = SZ_1K,
 249         .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
 250         .little_endian = true,
 251 };
 252 
 253 struct fsl_qspi {
 254         void __iomem *iobase;
 255         void __iomem *ahb_addr;
 256         u32 memmap_phy;
 257         struct clk *clk, *clk_en;
 258         struct device *dev;
 259         struct completion c;
 260         const struct fsl_qspi_devtype_data *devtype_data;
 261         struct mutex lock;
 262         struct pm_qos_request pm_qos_req;
 263         int selected;
 264 };
 265 
 266 static inline int needs_swap_endian(struct fsl_qspi *q)
 267 {
 268         return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
 269 }
 270 
 271 static inline int needs_4x_clock(struct fsl_qspi *q)
 272 {
 273         return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
 274 }
 275 
 276 static inline int needs_fill_txfifo(struct fsl_qspi *q)
 277 {
 278         return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
 279 }
 280 
 281 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
 282 {
 283         return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
 284 }
 285 
 286 static inline int needs_amba_base_offset(struct fsl_qspi *q)
 287 {
 288         return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
 289 }
 290 
 291 static inline int needs_tdh_setting(struct fsl_qspi *q)
 292 {
 293         return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
 294 }
 295 
 296 /*
 297  * An IC bug makes it necessary to rearrange the 32-bit data.
 298  * Later chips, such as IMX6SLX, have fixed this bug.
 299  */
 300 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
 301 {
 302         return needs_swap_endian(q) ? __swab32(a) : a;
 303 }
 304 
 305 /*
 306  * R/W functions for big- or little-endian registers:
 307  * The QSPI controller's endianness is independent of
 308  * the CPU core's endianness. So far, although the CPU
 309  * core is little-endian the QSPI controller can use
 310  * big-endian or little-endian.
 311  */
 312 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
 313 {
 314         if (q->devtype_data->little_endian)
 315                 iowrite32(val, addr);
 316         else
 317                 iowrite32be(val, addr);
 318 }
 319 
 320 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
 321 {
 322         if (q->devtype_data->little_endian)
 323                 return ioread32(addr);
 324 
 325         return ioread32be(addr);
 326 }
 327 
 328 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
 329 {
 330         struct fsl_qspi *q = dev_id;
 331         u32 reg;
 332 
 333         /* clear interrupt */
 334         reg = qspi_readl(q, q->iobase + QUADSPI_FR);
 335         qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 336 
 337         if (reg & QUADSPI_FR_TFF_MASK)
 338                 complete(&q->c);
 339 
 340         dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
 341         return IRQ_HANDLED;
 342 }
 343 
 344 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
 345 {
 346         switch (width) {
 347         case 1:
 348         case 2:
 349         case 4:
 350                 return 0;
 351         }
 352 
 353         return -ENOTSUPP;
 354 }
 355 
 356 static bool fsl_qspi_supports_op(struct spi_mem *mem,
 357                                  const struct spi_mem_op *op)
 358 {
 359         struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
 360         int ret;
 361 
 362         ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
 363 
 364         if (op->addr.nbytes)
 365                 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
 366 
 367         if (op->dummy.nbytes)
 368                 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
 369 
 370         if (op->data.nbytes)
 371                 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
 372 
 373         if (ret)
 374                 return false;
 375 
 376         /*
 377          * The number of instructions needed for the op, needs
 378          * to fit into a single LUT entry.
 379          */
 380         if (op->addr.nbytes +
 381            (op->dummy.nbytes ? 1:0) +
 382            (op->data.nbytes ? 1:0) > 6)
 383                 return false;
 384 
 385         /* Max 64 dummy clock cycles supported */
 386         if (op->dummy.nbytes &&
 387             (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
 388                 return false;
 389 
 390         /* Max data length, check controller limits and alignment */
 391         if (op->data.dir == SPI_MEM_DATA_IN &&
 392             (op->data.nbytes > q->devtype_data->ahb_buf_size ||
 393              (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
 394               !IS_ALIGNED(op->data.nbytes, 8))))
 395                 return false;
 396 
 397         if (op->data.dir == SPI_MEM_DATA_OUT &&
 398             op->data.nbytes > q->devtype_data->txfifo)
 399                 return false;
 400 
 401         return spi_mem_default_supports_op(mem, op);
 402 }
 403 
 404 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
 405                                  const struct spi_mem_op *op)
 406 {
 407         void __iomem *base = q->iobase;
 408         u32 lutval[4] = {};
 409         int lutidx = 1, i;
 410 
 411         lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
 412                              op->cmd.opcode);
 413 
 414         /*
 415          * For some unknown reason, using LUT_ADDR doesn't work in some
 416          * cases (at least with only one byte long addresses), so
 417          * let's use LUT_MODE to write the address bytes one by one
 418          */
 419         for (i = 0; i < op->addr.nbytes; i++) {
 420                 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
 421 
 422                 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
 423                                               LUT_PAD(op->addr.buswidth),
 424                                               addrbyte);
 425                 lutidx++;
 426         }
 427 
 428         if (op->dummy.nbytes) {
 429                 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
 430                                               LUT_PAD(op->dummy.buswidth),
 431                                               op->dummy.nbytes * 8 /
 432                                               op->dummy.buswidth);
 433                 lutidx++;
 434         }
 435 
 436         if (op->data.nbytes) {
 437                 lutval[lutidx / 2] |= LUT_DEF(lutidx,
 438                                               op->data.dir == SPI_MEM_DATA_IN ?
 439                                               LUT_FSL_READ : LUT_FSL_WRITE,
 440                                               LUT_PAD(op->data.buswidth),
 441                                               0);
 442                 lutidx++;
 443         }
 444 
 445         lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
 446 
 447         /* unlock LUT */
 448         qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
 449         qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 450 
 451         /* fill LUT */
 452         for (i = 0; i < ARRAY_SIZE(lutval); i++)
 453                 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
 454 
 455         /* lock LUT */
 456         qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
 457         qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 458 }
 459 
 460 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
 461 {
 462         int ret;
 463 
 464         ret = clk_prepare_enable(q->clk_en);
 465         if (ret)
 466                 return ret;
 467 
 468         ret = clk_prepare_enable(q->clk);
 469         if (ret) {
 470                 clk_disable_unprepare(q->clk_en);
 471                 return ret;
 472         }
 473 
 474         if (needs_wakeup_wait_mode(q))
 475                 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
 476 
 477         return 0;
 478 }
 479 
 480 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
 481 {
 482         if (needs_wakeup_wait_mode(q))
 483                 pm_qos_remove_request(&q->pm_qos_req);
 484 
 485         clk_disable_unprepare(q->clk);
 486         clk_disable_unprepare(q->clk_en);
 487 }
 488 
 489 /*
 490  * If we have changed the content of the flash by writing or erasing, or if we
 491  * read from flash with a different offset into the page buffer, we need to
 492  * invalidate the AHB buffer. If we do not do so, we may read out the wrong
 493  * data. The spec tells us reset the AHB domain and Serial Flash domain at
 494  * the same time.
 495  */
 496 static void fsl_qspi_invalidate(struct fsl_qspi *q)
 497 {
 498         u32 reg;
 499 
 500         reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
 501         reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
 502         qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 503 
 504         /*
 505          * The minimum delay : 1 AHB + 2 SFCK clocks.
 506          * Delay 1 us is enough.
 507          */
 508         udelay(1);
 509 
 510         reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
 511         qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 512 }
 513 
 514 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
 515 {
 516         unsigned long rate = spi->max_speed_hz;
 517         int ret;
 518 
 519         if (q->selected == spi->chip_select)
 520                 return;
 521 
 522         if (needs_4x_clock(q))
 523                 rate *= 4;
 524 
 525         fsl_qspi_clk_disable_unprep(q);
 526 
 527         ret = clk_set_rate(q->clk, rate);
 528         if (ret)
 529                 return;
 530 
 531         ret = fsl_qspi_clk_prep_enable(q);
 532         if (ret)
 533                 return;
 534 
 535         q->selected = spi->chip_select;
 536 
 537         fsl_qspi_invalidate(q);
 538 }
 539 
 540 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
 541 {
 542         memcpy_fromio(op->data.buf.in,
 543                       q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
 544                       op->data.nbytes);
 545 }
 546 
 547 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
 548                                  const struct spi_mem_op *op)
 549 {
 550         void __iomem *base = q->iobase;
 551         int i;
 552         u32 val;
 553 
 554         for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
 555                 memcpy(&val, op->data.buf.out + i, 4);
 556                 val = fsl_qspi_endian_xchg(q, val);
 557                 qspi_writel(q, val, base + QUADSPI_TBDR);
 558         }
 559 
 560         if (i < op->data.nbytes) {
 561                 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
 562                 val = fsl_qspi_endian_xchg(q, val);
 563                 qspi_writel(q, val, base + QUADSPI_TBDR);
 564         }
 565 
 566         if (needs_fill_txfifo(q)) {
 567                 for (i = op->data.nbytes; i < 16; i += 4)
 568                         qspi_writel(q, 0, base + QUADSPI_TBDR);
 569         }
 570 }
 571 
 572 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
 573                           const struct spi_mem_op *op)
 574 {
 575         void __iomem *base = q->iobase;
 576         int i;
 577         u8 *buf = op->data.buf.in;
 578         u32 val;
 579 
 580         for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
 581                 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
 582                 val = fsl_qspi_endian_xchg(q, val);
 583                 memcpy(buf + i, &val, 4);
 584         }
 585 
 586         if (i < op->data.nbytes) {
 587                 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
 588                 val = fsl_qspi_endian_xchg(q, val);
 589                 memcpy(buf + i, &val, op->data.nbytes - i);
 590         }
 591 }
 592 
 593 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
 594 {
 595         void __iomem *base = q->iobase;
 596         int err = 0;
 597 
 598         init_completion(&q->c);
 599 
 600         /*
 601          * Always start the sequence at the same index since we update
 602          * the LUT at each exec_op() call. And also specify the DATA
 603          * length, since it's has not been specified in the LUT.
 604          */
 605         qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
 606                     base + QUADSPI_IPCR);
 607 
 608         /* Wait for the interrupt. */
 609         if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
 610                 err = -ETIMEDOUT;
 611 
 612         if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
 613                 fsl_qspi_read_rxfifo(q, op);
 614 
 615         return err;
 616 }
 617 
 618 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
 619                                     u32 mask, u32 delay_us, u32 timeout_us)
 620 {
 621         u32 reg;
 622 
 623         if (!q->devtype_data->little_endian)
 624                 mask = (u32)cpu_to_be32(mask);
 625 
 626         return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
 627                                   timeout_us);
 628 }
 629 
 630 static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 631 {
 632         struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
 633         void __iomem *base = q->iobase;
 634         u32 addr_offset = 0;
 635         int err = 0;
 636 
 637         mutex_lock(&q->lock);
 638 
 639         /* wait for the controller being ready */
 640         fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
 641                                  QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
 642 
 643         fsl_qspi_select_mem(q, mem->spi);
 644 
 645         if (needs_amba_base_offset(q))
 646                 addr_offset = q->memmap_phy;
 647 
 648         qspi_writel(q,
 649                     q->selected * q->devtype_data->ahb_buf_size + addr_offset,
 650                     base + QUADSPI_SFAR);
 651 
 652         qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
 653                     QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
 654                     base + QUADSPI_MCR);
 655 
 656         qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
 657                     base + QUADSPI_SPTRCLR);
 658 
 659         fsl_qspi_prepare_lut(q, op);
 660 
 661         /*
 662          * If we have large chunks of data, we read them through the AHB bus
 663          * by accessing the mapped memory. In all other cases we use
 664          * IP commands to access the flash.
 665          */
 666         if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
 667             op->data.dir == SPI_MEM_DATA_IN) {
 668                 fsl_qspi_read_ahb(q, op);
 669         } else {
 670                 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
 671                             QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
 672 
 673                 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
 674                         fsl_qspi_fill_txfifo(q, op);
 675 
 676                 err = fsl_qspi_do_op(q, op);
 677         }
 678 
 679         /* Invalidate the data in the AHB buffer. */
 680         fsl_qspi_invalidate(q);
 681 
 682         mutex_unlock(&q->lock);
 683 
 684         return err;
 685 }
 686 
 687 static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 688 {
 689         struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
 690 
 691         if (op->data.dir == SPI_MEM_DATA_OUT) {
 692                 if (op->data.nbytes > q->devtype_data->txfifo)
 693                         op->data.nbytes = q->devtype_data->txfifo;
 694         } else {
 695                 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
 696                         op->data.nbytes = q->devtype_data->ahb_buf_size;
 697                 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
 698                         op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
 699         }
 700 
 701         return 0;
 702 }
 703 
 704 static int fsl_qspi_default_setup(struct fsl_qspi *q)
 705 {
 706         void __iomem *base = q->iobase;
 707         u32 reg, addr_offset = 0;
 708         int ret;
 709 
 710         /* disable and unprepare clock to avoid glitch pass to controller */
 711         fsl_qspi_clk_disable_unprep(q);
 712 
 713         /* the default frequency, we will change it later if necessary. */
 714         ret = clk_set_rate(q->clk, 66000000);
 715         if (ret)
 716                 return ret;
 717 
 718         ret = fsl_qspi_clk_prep_enable(q);
 719         if (ret)
 720                 return ret;
 721 
 722         /* Reset the module */
 723         qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
 724                     base + QUADSPI_MCR);
 725         udelay(1);
 726 
 727         /* Disable the module */
 728         qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
 729                     base + QUADSPI_MCR);
 730 
 731         /*
 732          * Previous boot stages (BootROM, bootloader) might have used DDR
 733          * mode and did not clear the TDH bits. As we currently use SDR mode
 734          * only, clear the TDH bits if necessary.
 735          */
 736         if (needs_tdh_setting(q))
 737                 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
 738                             ~QUADSPI_FLSHCR_TDH_MASK,
 739                             base + QUADSPI_FLSHCR);
 740 
 741         reg = qspi_readl(q, base + QUADSPI_SMPR);
 742         qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
 743                         | QUADSPI_SMPR_FSPHS_MASK
 744                         | QUADSPI_SMPR_HSENA_MASK
 745                         | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
 746 
 747         /* We only use the buffer3 for AHB read */
 748         qspi_writel(q, 0, base + QUADSPI_BUF0IND);
 749         qspi_writel(q, 0, base + QUADSPI_BUF1IND);
 750         qspi_writel(q, 0, base + QUADSPI_BUF2IND);
 751 
 752         qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
 753                     q->iobase + QUADSPI_BFGENCR);
 754         qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
 755         qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
 756                     QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
 757                     base + QUADSPI_BUF3CR);
 758 
 759         if (needs_amba_base_offset(q))
 760                 addr_offset = q->memmap_phy;
 761 
 762         /*
 763          * In HW there can be a maximum of four chips on two buses with
 764          * two chip selects on each bus. We use four chip selects in SW
 765          * to differentiate between the four chips.
 766          * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
 767          * SFB2AD accordingly.
 768          */
 769         qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
 770                     base + QUADSPI_SFA1AD);
 771         qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
 772                     base + QUADSPI_SFA2AD);
 773         qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
 774                     base + QUADSPI_SFB1AD);
 775         qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
 776                     base + QUADSPI_SFB2AD);
 777 
 778         q->selected = -1;
 779 
 780         /* Enable the module */
 781         qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
 782                     base + QUADSPI_MCR);
 783 
 784         /* clear all interrupt status */
 785         qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
 786 
 787         /* enable the interrupt */
 788         qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
 789 
 790         return 0;
 791 }
 792 
 793 static const char *fsl_qspi_get_name(struct spi_mem *mem)
 794 {
 795         struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
 796         struct device *dev = &mem->spi->dev;
 797         const char *name;
 798 
 799         /*
 800          * In order to keep mtdparts compatible with the old MTD driver at
 801          * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
 802          * platform_device of the controller.
 803          */
 804         if (of_get_available_child_count(q->dev->of_node) == 1)
 805                 return dev_name(q->dev);
 806 
 807         name = devm_kasprintf(dev, GFP_KERNEL,
 808                               "%s-%d", dev_name(q->dev),
 809                               mem->spi->chip_select);
 810 
 811         if (!name) {
 812                 dev_err(dev, "failed to get memory for custom flash name\n");
 813                 return ERR_PTR(-ENOMEM);
 814         }
 815 
 816         return name;
 817 }
 818 
 819 static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
 820         .adjust_op_size = fsl_qspi_adjust_op_size,
 821         .supports_op = fsl_qspi_supports_op,
 822         .exec_op = fsl_qspi_exec_op,
 823         .get_name = fsl_qspi_get_name,
 824 };
 825 
 826 static int fsl_qspi_probe(struct platform_device *pdev)
 827 {
 828         struct spi_controller *ctlr;
 829         struct device *dev = &pdev->dev;
 830         struct device_node *np = dev->of_node;
 831         struct resource *res;
 832         struct fsl_qspi *q;
 833         int ret;
 834 
 835         ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
 836         if (!ctlr)
 837                 return -ENOMEM;
 838 
 839         ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
 840                           SPI_TX_DUAL | SPI_TX_QUAD;
 841 
 842         q = spi_controller_get_devdata(ctlr);
 843         q->dev = dev;
 844         q->devtype_data = of_device_get_match_data(dev);
 845         if (!q->devtype_data) {
 846                 ret = -ENODEV;
 847                 goto err_put_ctrl;
 848         }
 849 
 850         platform_set_drvdata(pdev, q);
 851 
 852         /* find the resources */
 853         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
 854         q->iobase = devm_ioremap_resource(dev, res);
 855         if (IS_ERR(q->iobase)) {
 856                 ret = PTR_ERR(q->iobase);
 857                 goto err_put_ctrl;
 858         }
 859 
 860         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 861                                         "QuadSPI-memory");
 862         q->ahb_addr = devm_ioremap_resource(dev, res);
 863         if (IS_ERR(q->ahb_addr)) {
 864                 ret = PTR_ERR(q->ahb_addr);
 865                 goto err_put_ctrl;
 866         }
 867 
 868         q->memmap_phy = res->start;
 869 
 870         /* find the clocks */
 871         q->clk_en = devm_clk_get(dev, "qspi_en");
 872         if (IS_ERR(q->clk_en)) {
 873                 ret = PTR_ERR(q->clk_en);
 874                 goto err_put_ctrl;
 875         }
 876 
 877         q->clk = devm_clk_get(dev, "qspi");
 878         if (IS_ERR(q->clk)) {
 879                 ret = PTR_ERR(q->clk);
 880                 goto err_put_ctrl;
 881         }
 882 
 883         ret = fsl_qspi_clk_prep_enable(q);
 884         if (ret) {
 885                 dev_err(dev, "can not enable the clock\n");
 886                 goto err_put_ctrl;
 887         }
 888 
 889         /* find the irq */
 890         ret = platform_get_irq(pdev, 0);
 891         if (ret < 0)
 892                 goto err_disable_clk;
 893 
 894         ret = devm_request_irq(dev, ret,
 895                         fsl_qspi_irq_handler, 0, pdev->name, q);
 896         if (ret) {
 897                 dev_err(dev, "failed to request irq: %d\n", ret);
 898                 goto err_disable_clk;
 899         }
 900 
 901         mutex_init(&q->lock);
 902 
 903         ctlr->bus_num = -1;
 904         ctlr->num_chipselect = 4;
 905         ctlr->mem_ops = &fsl_qspi_mem_ops;
 906 
 907         fsl_qspi_default_setup(q);
 908 
 909         ctlr->dev.of_node = np;
 910 
 911         ret = devm_spi_register_controller(dev, ctlr);
 912         if (ret)
 913                 goto err_destroy_mutex;
 914 
 915         return 0;
 916 
 917 err_destroy_mutex:
 918         mutex_destroy(&q->lock);
 919 
 920 err_disable_clk:
 921         fsl_qspi_clk_disable_unprep(q);
 922 
 923 err_put_ctrl:
 924         spi_controller_put(ctlr);
 925 
 926         dev_err(dev, "Freescale QuadSPI probe failed\n");
 927         return ret;
 928 }
 929 
 930 static int fsl_qspi_remove(struct platform_device *pdev)
 931 {
 932         struct fsl_qspi *q = platform_get_drvdata(pdev);
 933 
 934         /* disable the hardware */
 935         qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
 936         qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
 937 
 938         fsl_qspi_clk_disable_unprep(q);
 939 
 940         mutex_destroy(&q->lock);
 941 
 942         return 0;
 943 }
 944 
 945 static int fsl_qspi_suspend(struct device *dev)
 946 {
 947         return 0;
 948 }
 949 
 950 static int fsl_qspi_resume(struct device *dev)
 951 {
 952         struct fsl_qspi *q = dev_get_drvdata(dev);
 953 
 954         fsl_qspi_default_setup(q);
 955 
 956         return 0;
 957 }
 958 
 959 static const struct of_device_id fsl_qspi_dt_ids[] = {
 960         { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
 961         { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
 962         { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
 963         { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
 964         { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
 965         { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
 966         { /* sentinel */ }
 967 };
 968 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
 969 
 970 static const struct dev_pm_ops fsl_qspi_pm_ops = {
 971         .suspend        = fsl_qspi_suspend,
 972         .resume         = fsl_qspi_resume,
 973 };
 974 
 975 static struct platform_driver fsl_qspi_driver = {
 976         .driver = {
 977                 .name   = "fsl-quadspi",
 978                 .of_match_table = fsl_qspi_dt_ids,
 979                 .pm =   &fsl_qspi_pm_ops,
 980         },
 981         .probe          = fsl_qspi_probe,
 982         .remove         = fsl_qspi_remove,
 983 };
 984 module_platform_driver(fsl_qspi_driver);
 985 
 986 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
 987 MODULE_AUTHOR("Freescale Semiconductor Inc.");
 988 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
 989 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
 990 MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>");
 991 MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>");
 992 MODULE_LICENSE("GPL v2");
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root/drivers/spi/spi-fsl-qspi.c

DEFINITIONS
