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11 #ifndef __LINUX_IMX21_HCD_H__
12 #define __LINUX_IMX21_HCD_H__
13
14 #ifdef CONFIG_DYNAMIC_DEBUG
15 #define DEBUG
16 #endif
17
18 #include <linux/platform_data/usb-mx2.h>
19
20 #define NUM_ISO_ETDS 2
21 #define USB_NUM_ETD 32
22 #define DMEM_SIZE 4096
23
24
25 #define USBOTG_HWMODE 0x00
26 #define USBOTG_HWMODE_ANASDBEN (1 << 14)
27 #define USBOTG_HWMODE_OTGXCVR_SHIFT 6
28 #define USBOTG_HWMODE_OTGXCVR_MASK (3 << 6)
29 #define USBOTG_HWMODE_OTGXCVR_TD_RD (0 << 6)
30 #define USBOTG_HWMODE_OTGXCVR_TS_RD (2 << 6)
31 #define USBOTG_HWMODE_OTGXCVR_TD_RS (1 << 6)
32 #define USBOTG_HWMODE_OTGXCVR_TS_RS (3 << 6)
33 #define USBOTG_HWMODE_HOSTXCVR_SHIFT 4
34 #define USBOTG_HWMODE_HOSTXCVR_MASK (3 << 4)
35 #define USBOTG_HWMODE_HOSTXCVR_TD_RD (0 << 4)
36 #define USBOTG_HWMODE_HOSTXCVR_TS_RD (2 << 4)
37 #define USBOTG_HWMODE_HOSTXCVR_TD_RS (1 << 4)
38 #define USBOTG_HWMODE_HOSTXCVR_TS_RS (3 << 4)
39 #define USBOTG_HWMODE_CRECFG_MASK (3 << 0)
40 #define USBOTG_HWMODE_CRECFG_HOST (1 << 0)
41 #define USBOTG_HWMODE_CRECFG_FUNC (2 << 0)
42 #define USBOTG_HWMODE_CRECFG_HNP (3 << 0)
43
44 #define USBOTG_CINT_STAT 0x04
45 #define USBOTG_CINT_STEN 0x08
46 #define USBOTG_ASHNPINT (1 << 5)
47 #define USBOTG_ASFCINT (1 << 4)
48 #define USBOTG_ASHCINT (1 << 3)
49 #define USBOTG_SHNPINT (1 << 2)
50 #define USBOTG_FCINT (1 << 1)
51 #define USBOTG_HCINT (1 << 0)
52
53 #define USBOTG_CLK_CTRL 0x0c
54 #define USBOTG_CLK_CTRL_FUNC (1 << 2)
55 #define USBOTG_CLK_CTRL_HST (1 << 1)
56 #define USBOTG_CLK_CTRL_MAIN (1 << 0)
57
58 #define USBOTG_RST_CTRL 0x10
59 #define USBOTG_RST_RSTI2C (1 << 15)
60 #define USBOTG_RST_RSTCTRL (1 << 5)
61 #define USBOTG_RST_RSTFC (1 << 4)
62 #define USBOTG_RST_RSTFSKE (1 << 3)
63 #define USBOTG_RST_RSTRH (1 << 2)
64 #define USBOTG_RST_RSTHSIE (1 << 1)
65 #define USBOTG_RST_RSTHC (1 << 0)
66
67 #define USBOTG_FRM_INTVL 0x14
68 #define USBOTG_FRM_REMAIN 0x18
69 #define USBOTG_HNP_CSR 0x1c
70 #define USBOTG_HNP_ISR 0x2c
71 #define USBOTG_HNP_IEN 0x30
72
73 #define USBOTG_I2C_TXCVR_REG(x) (0x100 + (x))
74 #define USBOTG_I2C_XCVR_DEVAD 0x118
75 #define USBOTG_I2C_SEQ_OP_REG 0x119
76 #define USBOTG_I2C_SEQ_RD_STARTAD 0x11a
77 #define USBOTG_I2C_OP_CTRL_REG 0x11b
78 #define USBOTG_I2C_SCLK_TO_SCK_HPER 0x11e
79 #define USBOTG_I2C_MASTER_INT_REG 0x11f
80
81 #define USBH_HOST_CTRL 0x80
82 #define USBH_HOST_CTRL_HCRESET (1 << 31)
83 #define USBH_HOST_CTRL_SCHDOVR(x) ((x) << 16)
84 #define USBH_HOST_CTRL_RMTWUEN (1 << 4)
85 #define USBH_HOST_CTRL_HCUSBSTE_RESET (0 << 2)
86 #define USBH_HOST_CTRL_HCUSBSTE_RESUME (1 << 2)
87 #define USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL (2 << 2)
88 #define USBH_HOST_CTRL_HCUSBSTE_SUSPEND (3 << 2)
89 #define USBH_HOST_CTRL_CTLBLKSR_1 (0 << 0)
90 #define USBH_HOST_CTRL_CTLBLKSR_2 (1 << 0)
91 #define USBH_HOST_CTRL_CTLBLKSR_3 (2 << 0)
92 #define USBH_HOST_CTRL_CTLBLKSR_4 (3 << 0)
93
94 #define USBH_SYSISR 0x88
95 #define USBH_SYSISR_PSCINT (1 << 6)
96 #define USBH_SYSISR_FMOFINT (1 << 5)
97 #define USBH_SYSISR_HERRINT (1 << 4)
98 #define USBH_SYSISR_RESDETINT (1 << 3)
99 #define USBH_SYSISR_SOFINT (1 << 2)
100 #define USBH_SYSISR_DONEINT (1 << 1)
101 #define USBH_SYSISR_SORINT (1 << 0)
102
103 #define USBH_SYSIEN 0x8c
104 #define USBH_SYSIEN_PSCINT (1 << 6)
105 #define USBH_SYSIEN_FMOFINT (1 << 5)
106 #define USBH_SYSIEN_HERRINT (1 << 4)
107 #define USBH_SYSIEN_RESDETINT (1 << 3)
108 #define USBH_SYSIEN_SOFINT (1 << 2)
109 #define USBH_SYSIEN_DONEINT (1 << 1)
110 #define USBH_SYSIEN_SORINT (1 << 0)
111
112 #define USBH_XBUFSTAT 0x98
113 #define USBH_YBUFSTAT 0x9c
114 #define USBH_XYINTEN 0xa0
115 #define USBH_XFILLSTAT 0xa8
116 #define USBH_YFILLSTAT 0xac
117 #define USBH_ETDENSET 0xc0
118 #define USBH_ETDENCLR 0xc4
119 #define USBH_IMMEDINT 0xcc
120 #define USBH_ETDDONESTAT 0xd0
121 #define USBH_ETDDONEEN 0xd4
122 #define USBH_FRMNUB 0xe0
123 #define USBH_LSTHRESH 0xe4
124
125 #define USBH_ROOTHUBA 0xe8
126 #define USBH_ROOTHUBA_PWRTOGOOD_MASK (0xff)
127 #define USBH_ROOTHUBA_PWRTOGOOD_SHIFT (24)
128 #define USBH_ROOTHUBA_NOOVRCURP (1 << 12)
129 #define USBH_ROOTHUBA_OVRCURPM (1 << 11)
130 #define USBH_ROOTHUBA_DEVTYPE (1 << 10)
131 #define USBH_ROOTHUBA_PWRSWTMD (1 << 9)
132 #define USBH_ROOTHUBA_NOPWRSWT (1 << 8)
133 #define USBH_ROOTHUBA_NDNSTMPRT_MASK (0xff)
134
135 #define USBH_ROOTHUBB 0xec
136 #define USBH_ROOTHUBB_PRTPWRCM(x) (1 << ((x) + 16))
137 #define USBH_ROOTHUBB_DEVREMOVE(x) (1 << (x))
138
139 #define USBH_ROOTSTAT 0xf0
140 #define USBH_ROOTSTAT_CLRRMTWUE (1 << 31)
141 #define USBH_ROOTSTAT_OVRCURCHG (1 << 17)
142 #define USBH_ROOTSTAT_DEVCONWUE (1 << 15)
143 #define USBH_ROOTSTAT_OVRCURI (1 << 1)
144 #define USBH_ROOTSTAT_LOCPWRS (1 << 0)
145
146 #define USBH_PORTSTAT(x) (0xf4 + ((x) * 4))
147 #define USBH_PORTSTAT_PRTRSTSC (1 << 20)
148 #define USBH_PORTSTAT_OVRCURIC (1 << 19)
149 #define USBH_PORTSTAT_PRTSTATSC (1 << 18)
150 #define USBH_PORTSTAT_PRTENBLSC (1 << 17)
151 #define USBH_PORTSTAT_CONNECTSC (1 << 16)
152 #define USBH_PORTSTAT_LSDEVCON (1 << 9)
153 #define USBH_PORTSTAT_PRTPWRST (1 << 8)
154 #define USBH_PORTSTAT_PRTRSTST (1 << 4)
155 #define USBH_PORTSTAT_PRTOVRCURI (1 << 3)
156 #define USBH_PORTSTAT_PRTSUSPST (1 << 2)
157 #define USBH_PORTSTAT_PRTENABST (1 << 1)
158 #define USBH_PORTSTAT_CURCONST (1 << 0)
159
160 #define USB_DMAREV 0x800
161 #define USB_DMAINTSTAT 0x804
162 #define USB_DMAINTSTAT_EPERR (1 << 1)
163 #define USB_DMAINTSTAT_ETDERR (1 << 0)
164
165 #define USB_DMAINTEN 0x808
166 #define USB_DMAINTEN_EPERRINTEN (1 << 1)
167 #define USB_DMAINTEN_ETDERRINTEN (1 << 0)
168
169 #define USB_ETDDMAERSTAT 0x80c
170 #define USB_EPDMAERSTAT 0x810
171 #define USB_ETDDMAEN 0x820
172 #define USB_EPDMAEN 0x824
173 #define USB_ETDDMAXTEN 0x828
174 #define USB_EPDMAXTEN 0x82c
175 #define USB_ETDDMAENXYT 0x830
176 #define USB_EPDMAENXYT 0x834
177 #define USB_ETDDMABST4EN 0x838
178 #define USB_EPDMABST4EN 0x83c
179
180 #define USB_MISCCONTROL 0x840
181 #define USB_MISCCONTROL_ISOPREVFRM (1 << 3)
182 #define USB_MISCCONTROL_SKPRTRY (1 << 2)
183 #define USB_MISCCONTROL_ARBMODE (1 << 1)
184 #define USB_MISCCONTROL_FILTCC (1 << 0)
185
186 #define USB_ETDDMACHANLCLR 0x848
187 #define USB_EPDMACHANLCLR 0x84c
188 #define USB_ETDSMSA(x) (0x900 + ((x) * 4))
189 #define USB_EPSMSA(x) (0x980 + ((x) * 4))
190 #define USB_ETDDMABUFPTR(x) (0xa00 + ((x) * 4))
191 #define USB_EPDMABUFPTR(x) (0xa80 + ((x) * 4))
192
193 #define USB_ETD_DWORD(x, w) (0x200 + ((x) * 16) + ((w) * 4))
194 #define DW0_ADDRESS 0
195 #define DW0_ENDPNT 7
196 #define DW0_DIRECT 11
197 #define DW0_SPEED 13
198 #define DW0_FORMAT 14
199 #define DW0_MAXPKTSIZ 16
200 #define DW0_HALTED 27
201 #define DW0_TOGCRY 28
202 #define DW0_SNDNAK 30
203
204 #define DW1_XBUFSRTAD 0
205 #define DW1_YBUFSRTAD 16
206
207 #define DW2_RTRYDELAY 0
208 #define DW2_POLINTERV 0
209 #define DW2_STARTFRM 0
210 #define DW2_RELPOLPOS 8
211 #define DW2_DIRPID 16
212 #define DW2_BUFROUND 18
213 #define DW2_DELAYINT 19
214 #define DW2_DATATOG 22
215 #define DW2_ERRORCNT 24
216 #define DW2_COMPCODE 28
217
218 #define DW3_TOTBYECNT 0
219 #define DW3_PKTLEN0 0
220 #define DW3_COMPCODE0 12
221 #define DW3_PKTLEN1 16
222 #define DW3_BUFSIZE 21
223 #define DW3_COMPCODE1 28
224
225 #define USBCTRL 0x600
226 #define USBCTRL_I2C_WU_INT_STAT (1 << 27)
227 #define USBCTRL_OTG_WU_INT_STAT (1 << 26)
228 #define USBCTRL_HOST_WU_INT_STAT (1 << 25)
229 #define USBCTRL_FNT_WU_INT_STAT (1 << 24)
230 #define USBCTRL_I2C_WU_INT_EN (1 << 19)
231 #define USBCTRL_OTG_WU_INT_EN (1 << 18)
232 #define USBCTRL_HOST_WU_INT_EN (1 << 17)
233 #define USBCTRL_FNT_WU_INT_EN (1 << 16)
234 #define USBCTRL_OTC_RCV_RXDP (1 << 13)
235 #define USBCTRL_HOST1_BYP_TLL (1 << 12)
236 #define USBCTRL_OTG_BYP_VAL(x) ((x) << 10)
237 #define USBCTRL_HOST1_BYP_VAL(x) ((x) << 8)
238 #define USBCTRL_OTG_PWR_MASK (1 << 6)
239 #define USBCTRL_HOST1_PWR_MASK (1 << 5)
240 #define USBCTRL_HOST2_PWR_MASK (1 << 4)
241 #define USBCTRL_USB_BYP (1 << 2)
242 #define USBCTRL_HOST1_TXEN_OE (1 << 1)
243
244 #define USBOTG_DMEM 0x1000
245
246
247 #define TD_DIR_SETUP 0
248 #define TD_DIR_OUT 1
249 #define TD_DIR_IN 2
250 #define TD_FORMAT_CONTROL 0
251 #define TD_FORMAT_ISO 1
252 #define TD_FORMAT_BULK 2
253 #define TD_FORMAT_INT 3
254 #define TD_TOGGLE_CARRY 0
255 #define TD_TOGGLE_DATA0 2
256 #define TD_TOGGLE_DATA1 3
257
258
259 #define US_CTRL_SETUP 2
260 #define US_CTRL_DATA 1
261 #define US_CTRL_ACK 0
262
263
264 #define US_BULK 1
265 #define US_BULK0 0
266
267
268 #define IMX_FMT_CTRL 0x0
269 #define IMX_FMT_ISO 0x1
270 #define IMX_FMT_BULK 0x2
271 #define IMX_FMT_INT 0x3
272
273 static char fmt_urb_to_etd[4] = {
274 IMX_FMT_ISO,
275 IMX_FMT_INT,
276 IMX_FMT_CTRL,
277 IMX_FMT_BULK
278 };
279
280
281
282 #define TD_CC_NOERROR 0x00
283 #define TD_CC_CRC 0x01
284 #define TD_CC_BITSTUFFING 0x02
285 #define TD_CC_DATATOGGLEM 0x03
286 #define TD_CC_STALL 0x04
287 #define TD_DEVNOTRESP 0x05
288 #define TD_PIDCHECKFAIL 0x06
289
290 #define TD_DATAOVERRUN 0x08
291 #define TD_DATAUNDERRUN 0x09
292 #define TD_BUFFEROVERRUN 0x0C
293 #define TD_BUFFERUNDERRUN 0x0D
294 #define TD_SCHEDULEOVERRUN 0x0E
295 #define TD_NOTACCESSED 0x0F
296
297 static const int cc_to_error[16] = {
298 0,
299 -EILSEQ,
300 -EPROTO,
301 -EILSEQ,
302 -EPIPE,
303 -ETIMEDOUT,
304 -EPROTO,
305 -EPROTO,
306 -EOVERFLOW,
307 -EREMOTEIO,
308 -EIO,
309 -EIO,
310 -ECOMM,
311 -ENOSR,
312 -ENOSPC,
313 -EALREADY
314 };
315
316
317 struct urb_priv {
318 struct urb *urb;
319 struct usb_host_endpoint *ep;
320 int active;
321 int state;
322 struct td *isoc_td;
323 int isoc_remaining;
324 int isoc_status;
325 };
326
327
328 struct ep_priv {
329 struct usb_host_endpoint *ep;
330 struct list_head td_list;
331 struct list_head queue;
332 int etd[NUM_ISO_ETDS];
333 int waiting_etd;
334 };
335
336
337 struct td {
338 struct list_head list;
339 struct urb *urb;
340 struct usb_host_endpoint *ep;
341 dma_addr_t dma_handle;
342 void *cpu_buffer;
343 int len;
344 int frame;
345 int isoc_index;
346 };
347
348
349 struct etd_priv {
350 struct usb_host_endpoint *ep;
351 struct urb *urb;
352 struct td *td;
353 struct list_head queue;
354 dma_addr_t dma_handle;
355 void *cpu_buffer;
356 void *bounce_buffer;
357 int alloc;
358 int len;
359 int dmem_size;
360 int dmem_offset;
361 int active_count;
362 #ifdef DEBUG
363 int activated_frame;
364 int disactivated_frame;
365 int last_int_frame;
366 int last_req_frame;
367 u32 submitted_dwords[4];
368 #endif
369 };
370
371
372 struct imx21_dmem_area {
373 struct usb_host_endpoint *ep;
374 unsigned int offset;
375 unsigned int size;
376 struct list_head list;
377 };
378
379 #ifdef DEBUG
380 struct debug_usage_stats {
381 unsigned int value;
382 unsigned int maximum;
383 };
384
385 struct debug_stats {
386 unsigned long submitted;
387 unsigned long completed_ok;
388 unsigned long completed_failed;
389 unsigned long unlinked;
390 unsigned long queue_etd;
391 unsigned long queue_dmem;
392 };
393
394 struct debug_isoc_trace {
395 int schedule_frame;
396 int submit_frame;
397 int request_len;
398 int done_frame;
399 int done_len;
400 int cc;
401 struct td *td;
402 };
403 #endif
404
405
406 struct imx21 {
407 spinlock_t lock;
408 struct device *dev;
409 struct usb_hcd *hcd;
410 struct mx21_usbh_platform_data *pdata;
411 struct list_head dmem_list;
412 struct list_head queue_for_etd;
413 struct list_head queue_for_dmem;
414 struct etd_priv etd[USB_NUM_ETD];
415 struct clk *clk;
416 void __iomem *regs;
417 #ifdef DEBUG
418 struct dentry *debug_root;
419 struct debug_stats nonisoc_stats;
420 struct debug_stats isoc_stats;
421 struct debug_usage_stats etd_usage;
422 struct debug_usage_stats dmem_usage;
423 struct debug_isoc_trace isoc_trace[20];
424 struct debug_isoc_trace isoc_trace_failed[20];
425 unsigned long debug_unblocks;
426 int isoc_trace_index;
427 int isoc_trace_index_failed;
428 #endif
429 };
430
431 #endif