This source file includes following definitions.
- to_smmu_as
- smmu_writel
- smmu_readl
- iova_pd_index
- iova_pt_index
- smmu_dma_addr_valid
- smmu_pde_to_dma
- smmu_flush_ptc_all
- smmu_flush_ptc
- smmu_flush_tlb
- smmu_flush_tlb_asid
- smmu_flush_tlb_section
- smmu_flush_tlb_group
- smmu_flush
- tegra_smmu_alloc_asid
- tegra_smmu_free_asid
- tegra_smmu_capable
- tegra_smmu_domain_alloc
- tegra_smmu_domain_free
- tegra_smmu_find_swgroup
- tegra_smmu_enable
- tegra_smmu_disable
- tegra_smmu_as_prepare
- tegra_smmu_as_unprepare
- tegra_smmu_attach_dev
- tegra_smmu_detach_dev
- tegra_smmu_set_pde
- tegra_smmu_pte_offset
- tegra_smmu_pte_lookup
- as_get_pte
- tegra_smmu_pte_get_use
- tegra_smmu_pte_put_use
- tegra_smmu_set_pte
- tegra_smmu_map
- tegra_smmu_unmap
- tegra_smmu_iova_to_phys
- tegra_smmu_find
- tegra_smmu_configure
- tegra_smmu_add_device
- tegra_smmu_remove_device
- tegra_smmu_find_group
- tegra_smmu_group_get
- tegra_smmu_device_group
- tegra_smmu_of_xlate
- tegra_smmu_ahb_enable
- tegra_smmu_swgroups_show
- tegra_smmu_clients_show
- tegra_smmu_debugfs_init
- tegra_smmu_debugfs_exit
- tegra_smmu_probe
- tegra_smmu_remove
1
2
3
4
5
6 #include <linux/bitops.h>
7 #include <linux/debugfs.h>
8 #include <linux/err.h>
9 #include <linux/iommu.h>
10 #include <linux/kernel.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/dma-mapping.h>
16
17 #include <soc/tegra/ahb.h>
18 #include <soc/tegra/mc.h>
19
20 struct tegra_smmu_group {
21 struct list_head list;
22 const struct tegra_smmu_group_soc *soc;
23 struct iommu_group *group;
24 };
25
26 struct tegra_smmu {
27 void __iomem *regs;
28 struct device *dev;
29
30 struct tegra_mc *mc;
31 const struct tegra_smmu_soc *soc;
32
33 struct list_head groups;
34
35 unsigned long pfn_mask;
36 unsigned long tlb_mask;
37
38 unsigned long *asids;
39 struct mutex lock;
40
41 struct list_head list;
42
43 struct dentry *debugfs;
44
45 struct iommu_device iommu;
46 };
47
48 struct tegra_smmu_as {
49 struct iommu_domain domain;
50 struct tegra_smmu *smmu;
51 unsigned int use_count;
52 u32 *count;
53 struct page **pts;
54 struct page *pd;
55 dma_addr_t pd_dma;
56 unsigned id;
57 u32 attr;
58 };
59
60 static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
61 {
62 return container_of(dom, struct tegra_smmu_as, domain);
63 }
64
65 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
66 unsigned long offset)
67 {
68 writel(value, smmu->regs + offset);
69 }
70
71 static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
72 {
73 return readl(smmu->regs + offset);
74 }
75
76 #define SMMU_CONFIG 0x010
77 #define SMMU_CONFIG_ENABLE (1 << 0)
78
79 #define SMMU_TLB_CONFIG 0x14
80 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
81 #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
82 #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \
83 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
84
85 #define SMMU_PTC_CONFIG 0x18
86 #define SMMU_PTC_CONFIG_ENABLE (1 << 29)
87 #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
88 #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
89
90 #define SMMU_PTB_ASID 0x01c
91 #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
92
93 #define SMMU_PTB_DATA 0x020
94 #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
95
96 #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
97
98 #define SMMU_TLB_FLUSH 0x030
99 #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
100 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
101 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
102 #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
103 SMMU_TLB_FLUSH_VA_MATCH_SECTION)
104 #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
105 SMMU_TLB_FLUSH_VA_MATCH_GROUP)
106 #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
107
108 #define SMMU_PTC_FLUSH 0x034
109 #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
110 #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
111
112 #define SMMU_PTC_FLUSH_HI 0x9b8
113 #define SMMU_PTC_FLUSH_HI_MASK 0x3
114
115
116 #define SMMU_ASID_ENABLE (1 << 31)
117 #define SMMU_ASID_MASK 0x7f
118 #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
119
120
121 #define SMMU_NUM_PDE 1024
122 #define SMMU_NUM_PTE 1024
123
124 #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
125 #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
126
127 #define SMMU_PDE_SHIFT 22
128 #define SMMU_PTE_SHIFT 12
129
130 #define SMMU_PD_READABLE (1 << 31)
131 #define SMMU_PD_WRITABLE (1 << 30)
132 #define SMMU_PD_NONSECURE (1 << 29)
133
134 #define SMMU_PDE_READABLE (1 << 31)
135 #define SMMU_PDE_WRITABLE (1 << 30)
136 #define SMMU_PDE_NONSECURE (1 << 29)
137 #define SMMU_PDE_NEXT (1 << 28)
138
139 #define SMMU_PTE_READABLE (1 << 31)
140 #define SMMU_PTE_WRITABLE (1 << 30)
141 #define SMMU_PTE_NONSECURE (1 << 29)
142
143 #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
144 SMMU_PDE_NONSECURE)
145
146 static unsigned int iova_pd_index(unsigned long iova)
147 {
148 return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1);
149 }
150
151 static unsigned int iova_pt_index(unsigned long iova)
152 {
153 return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1);
154 }
155
156 static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
157 {
158 addr >>= 12;
159 return (addr & smmu->pfn_mask) == addr;
160 }
161
162 static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde)
163 {
164 return (dma_addr_t)(pde & smmu->pfn_mask) << 12;
165 }
166
167 static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
168 {
169 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
170 }
171
172 static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma,
173 unsigned long offset)
174 {
175 u32 value;
176
177 offset &= ~(smmu->mc->soc->atom_size - 1);
178
179 if (smmu->mc->soc->num_address_bits > 32) {
180 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
181 value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
182 #else
183 value = 0;
184 #endif
185 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
186 }
187
188 value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
189 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
190 }
191
192 static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
193 {
194 smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
195 }
196
197 static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
198 unsigned long asid)
199 {
200 u32 value;
201
202 if (smmu->soc->num_asids == 4)
203 value = (asid & 0x3) << 29;
204 else
205 value = (asid & 0x7f) << 24;
206
207 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
208 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
209 }
210
211 static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
212 unsigned long asid,
213 unsigned long iova)
214 {
215 u32 value;
216
217 if (smmu->soc->num_asids == 4)
218 value = (asid & 0x3) << 29;
219 else
220 value = (asid & 0x7f) << 24;
221
222 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
223 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
224 }
225
226 static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
227 unsigned long asid,
228 unsigned long iova)
229 {
230 u32 value;
231
232 if (smmu->soc->num_asids == 4)
233 value = (asid & 0x3) << 29;
234 else
235 value = (asid & 0x7f) << 24;
236
237 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
238 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
239 }
240
241 static inline void smmu_flush(struct tegra_smmu *smmu)
242 {
243 smmu_readl(smmu, SMMU_CONFIG);
244 }
245
246 static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
247 {
248 unsigned long id;
249
250 mutex_lock(&smmu->lock);
251
252 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
253 if (id >= smmu->soc->num_asids) {
254 mutex_unlock(&smmu->lock);
255 return -ENOSPC;
256 }
257
258 set_bit(id, smmu->asids);
259 *idp = id;
260
261 mutex_unlock(&smmu->lock);
262 return 0;
263 }
264
265 static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
266 {
267 mutex_lock(&smmu->lock);
268 clear_bit(id, smmu->asids);
269 mutex_unlock(&smmu->lock);
270 }
271
272 static bool tegra_smmu_capable(enum iommu_cap cap)
273 {
274 return false;
275 }
276
277 static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
278 {
279 struct tegra_smmu_as *as;
280
281 if (type != IOMMU_DOMAIN_UNMANAGED)
282 return NULL;
283
284 as = kzalloc(sizeof(*as), GFP_KERNEL);
285 if (!as)
286 return NULL;
287
288 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
289
290 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
291 if (!as->pd) {
292 kfree(as);
293 return NULL;
294 }
295
296 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL);
297 if (!as->count) {
298 __free_page(as->pd);
299 kfree(as);
300 return NULL;
301 }
302
303 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL);
304 if (!as->pts) {
305 kfree(as->count);
306 __free_page(as->pd);
307 kfree(as);
308 return NULL;
309 }
310
311
312 as->domain.geometry.aperture_start = 0;
313 as->domain.geometry.aperture_end = 0xffffffff;
314 as->domain.geometry.force_aperture = true;
315
316 return &as->domain;
317 }
318
319 static void tegra_smmu_domain_free(struct iommu_domain *domain)
320 {
321 struct tegra_smmu_as *as = to_smmu_as(domain);
322
323
324
325 WARN_ON_ONCE(as->use_count);
326 kfree(as->count);
327 kfree(as->pts);
328 kfree(as);
329 }
330
331 static const struct tegra_smmu_swgroup *
332 tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
333 {
334 const struct tegra_smmu_swgroup *group = NULL;
335 unsigned int i;
336
337 for (i = 0; i < smmu->soc->num_swgroups; i++) {
338 if (smmu->soc->swgroups[i].swgroup == swgroup) {
339 group = &smmu->soc->swgroups[i];
340 break;
341 }
342 }
343
344 return group;
345 }
346
347 static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
348 unsigned int asid)
349 {
350 const struct tegra_smmu_swgroup *group;
351 unsigned int i;
352 u32 value;
353
354 for (i = 0; i < smmu->soc->num_clients; i++) {
355 const struct tegra_mc_client *client = &smmu->soc->clients[i];
356
357 if (client->swgroup != swgroup)
358 continue;
359
360 value = smmu_readl(smmu, client->smmu.reg);
361 value |= BIT(client->smmu.bit);
362 smmu_writel(smmu, value, client->smmu.reg);
363 }
364
365 group = tegra_smmu_find_swgroup(smmu, swgroup);
366 if (group) {
367 value = smmu_readl(smmu, group->reg);
368 value &= ~SMMU_ASID_MASK;
369 value |= SMMU_ASID_VALUE(asid);
370 value |= SMMU_ASID_ENABLE;
371 smmu_writel(smmu, value, group->reg);
372 }
373 }
374
375 static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
376 unsigned int asid)
377 {
378 const struct tegra_smmu_swgroup *group;
379 unsigned int i;
380 u32 value;
381
382 group = tegra_smmu_find_swgroup(smmu, swgroup);
383 if (group) {
384 value = smmu_readl(smmu, group->reg);
385 value &= ~SMMU_ASID_MASK;
386 value |= SMMU_ASID_VALUE(asid);
387 value &= ~SMMU_ASID_ENABLE;
388 smmu_writel(smmu, value, group->reg);
389 }
390
391 for (i = 0; i < smmu->soc->num_clients; i++) {
392 const struct tegra_mc_client *client = &smmu->soc->clients[i];
393
394 if (client->swgroup != swgroup)
395 continue;
396
397 value = smmu_readl(smmu, client->smmu.reg);
398 value &= ~BIT(client->smmu.bit);
399 smmu_writel(smmu, value, client->smmu.reg);
400 }
401 }
402
403 static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
404 struct tegra_smmu_as *as)
405 {
406 u32 value;
407 int err;
408
409 if (as->use_count > 0) {
410 as->use_count++;
411 return 0;
412 }
413
414 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
415 DMA_TO_DEVICE);
416 if (dma_mapping_error(smmu->dev, as->pd_dma))
417 return -ENOMEM;
418
419
420 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
421 err = -ENOMEM;
422 goto err_unmap;
423 }
424
425 err = tegra_smmu_alloc_asid(smmu, &as->id);
426 if (err < 0)
427 goto err_unmap;
428
429 smmu_flush_ptc(smmu, as->pd_dma, 0);
430 smmu_flush_tlb_asid(smmu, as->id);
431
432 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
433 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
434 smmu_writel(smmu, value, SMMU_PTB_DATA);
435 smmu_flush(smmu);
436
437 as->smmu = smmu;
438 as->use_count++;
439
440 return 0;
441
442 err_unmap:
443 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
444 return err;
445 }
446
447 static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
448 struct tegra_smmu_as *as)
449 {
450 if (--as->use_count > 0)
451 return;
452
453 tegra_smmu_free_asid(smmu, as->id);
454
455 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
456
457 as->smmu = NULL;
458 }
459
460 static int tegra_smmu_attach_dev(struct iommu_domain *domain,
461 struct device *dev)
462 {
463 struct tegra_smmu *smmu = dev->archdata.iommu;
464 struct tegra_smmu_as *as = to_smmu_as(domain);
465 struct device_node *np = dev->of_node;
466 struct of_phandle_args args;
467 unsigned int index = 0;
468 int err = 0;
469
470 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
471 &args)) {
472 unsigned int swgroup = args.args[0];
473
474 if (args.np != smmu->dev->of_node) {
475 of_node_put(args.np);
476 continue;
477 }
478
479 of_node_put(args.np);
480
481 err = tegra_smmu_as_prepare(smmu, as);
482 if (err < 0)
483 return err;
484
485 tegra_smmu_enable(smmu, swgroup, as->id);
486 index++;
487 }
488
489 if (index == 0)
490 return -ENODEV;
491
492 return 0;
493 }
494
495 static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
496 {
497 struct tegra_smmu_as *as = to_smmu_as(domain);
498 struct device_node *np = dev->of_node;
499 struct tegra_smmu *smmu = as->smmu;
500 struct of_phandle_args args;
501 unsigned int index = 0;
502
503 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
504 &args)) {
505 unsigned int swgroup = args.args[0];
506
507 if (args.np != smmu->dev->of_node) {
508 of_node_put(args.np);
509 continue;
510 }
511
512 of_node_put(args.np);
513
514 tegra_smmu_disable(smmu, swgroup, as->id);
515 tegra_smmu_as_unprepare(smmu, as);
516 index++;
517 }
518 }
519
520 static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova,
521 u32 value)
522 {
523 unsigned int pd_index = iova_pd_index(iova);
524 struct tegra_smmu *smmu = as->smmu;
525 u32 *pd = page_address(as->pd);
526 unsigned long offset = pd_index * sizeof(*pd);
527
528
529 pd[pd_index] = value;
530
531
532 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
533 sizeof(*pd), DMA_TO_DEVICE);
534
535
536 smmu_flush_ptc(smmu, as->pd_dma, offset);
537 smmu_flush_tlb_section(smmu, as->id, iova);
538 smmu_flush(smmu);
539 }
540
541 static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova)
542 {
543 u32 *pt = page_address(pt_page);
544
545 return pt + iova_pt_index(iova);
546 }
547
548 static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
549 dma_addr_t *dmap)
550 {
551 unsigned int pd_index = iova_pd_index(iova);
552 struct tegra_smmu *smmu = as->smmu;
553 struct page *pt_page;
554 u32 *pd;
555
556 pt_page = as->pts[pd_index];
557 if (!pt_page)
558 return NULL;
559
560 pd = page_address(as->pd);
561 *dmap = smmu_pde_to_dma(smmu, pd[pd_index]);
562
563 return tegra_smmu_pte_offset(pt_page, iova);
564 }
565
566 static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
567 dma_addr_t *dmap)
568 {
569 unsigned int pde = iova_pd_index(iova);
570 struct tegra_smmu *smmu = as->smmu;
571
572 if (!as->pts[pde]) {
573 struct page *page;
574 dma_addr_t dma;
575
576 page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
577 if (!page)
578 return NULL;
579
580 dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT,
581 DMA_TO_DEVICE);
582 if (dma_mapping_error(smmu->dev, dma)) {
583 __free_page(page);
584 return NULL;
585 }
586
587 if (!smmu_dma_addr_valid(smmu, dma)) {
588 dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT,
589 DMA_TO_DEVICE);
590 __free_page(page);
591 return NULL;
592 }
593
594 as->pts[pde] = page;
595
596 tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR |
597 SMMU_PDE_NEXT));
598
599 *dmap = dma;
600 } else {
601 u32 *pd = page_address(as->pd);
602
603 *dmap = smmu_pde_to_dma(smmu, pd[pde]);
604 }
605
606 return tegra_smmu_pte_offset(as->pts[pde], iova);
607 }
608
609 static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova)
610 {
611 unsigned int pd_index = iova_pd_index(iova);
612
613 as->count[pd_index]++;
614 }
615
616 static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
617 {
618 unsigned int pde = iova_pd_index(iova);
619 struct page *page = as->pts[pde];
620
621
622
623
624
625 if (--as->count[pde] == 0) {
626 struct tegra_smmu *smmu = as->smmu;
627 u32 *pd = page_address(as->pd);
628 dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]);
629
630 tegra_smmu_set_pde(as, iova, 0);
631
632 dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE);
633 __free_page(page);
634 as->pts[pde] = NULL;
635 }
636 }
637
638 static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
639 u32 *pte, dma_addr_t pte_dma, u32 val)
640 {
641 struct tegra_smmu *smmu = as->smmu;
642 unsigned long offset = offset_in_page(pte);
643
644 *pte = val;
645
646 dma_sync_single_range_for_device(smmu->dev, pte_dma, offset,
647 4, DMA_TO_DEVICE);
648 smmu_flush_ptc(smmu, pte_dma, offset);
649 smmu_flush_tlb_group(smmu, as->id, iova);
650 smmu_flush(smmu);
651 }
652
653 static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
654 phys_addr_t paddr, size_t size, int prot)
655 {
656 struct tegra_smmu_as *as = to_smmu_as(domain);
657 dma_addr_t pte_dma;
658 u32 pte_attrs;
659 u32 *pte;
660
661 pte = as_get_pte(as, iova, &pte_dma);
662 if (!pte)
663 return -ENOMEM;
664
665
666 if (*pte == 0)
667 tegra_smmu_pte_get_use(as, iova);
668
669 pte_attrs = SMMU_PTE_NONSECURE;
670
671 if (prot & IOMMU_READ)
672 pte_attrs |= SMMU_PTE_READABLE;
673
674 if (prot & IOMMU_WRITE)
675 pte_attrs |= SMMU_PTE_WRITABLE;
676
677 tegra_smmu_set_pte(as, iova, pte, pte_dma,
678 __phys_to_pfn(paddr) | pte_attrs);
679
680 return 0;
681 }
682
683 static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
684 size_t size, struct iommu_iotlb_gather *gather)
685 {
686 struct tegra_smmu_as *as = to_smmu_as(domain);
687 dma_addr_t pte_dma;
688 u32 *pte;
689
690 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
691 if (!pte || !*pte)
692 return 0;
693
694 tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
695 tegra_smmu_pte_put_use(as, iova);
696
697 return size;
698 }
699
700 static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
701 dma_addr_t iova)
702 {
703 struct tegra_smmu_as *as = to_smmu_as(domain);
704 unsigned long pfn;
705 dma_addr_t pte_dma;
706 u32 *pte;
707
708 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
709 if (!pte || !*pte)
710 return 0;
711
712 pfn = *pte & as->smmu->pfn_mask;
713
714 return PFN_PHYS(pfn);
715 }
716
717 static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
718 {
719 struct platform_device *pdev;
720 struct tegra_mc *mc;
721
722 pdev = of_find_device_by_node(np);
723 if (!pdev)
724 return NULL;
725
726 mc = platform_get_drvdata(pdev);
727 if (!mc)
728 return NULL;
729
730 return mc->smmu;
731 }
732
733 static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev,
734 struct of_phandle_args *args)
735 {
736 const struct iommu_ops *ops = smmu->iommu.ops;
737 int err;
738
739 err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops);
740 if (err < 0) {
741 dev_err(dev, "failed to initialize fwspec: %d\n", err);
742 return err;
743 }
744
745 err = ops->of_xlate(dev, args);
746 if (err < 0) {
747 dev_err(dev, "failed to parse SW group ID: %d\n", err);
748 iommu_fwspec_free(dev);
749 return err;
750 }
751
752 return 0;
753 }
754
755 static int tegra_smmu_add_device(struct device *dev)
756 {
757 struct device_node *np = dev->of_node;
758 struct tegra_smmu *smmu = NULL;
759 struct iommu_group *group;
760 struct of_phandle_args args;
761 unsigned int index = 0;
762 int err;
763
764 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
765 &args) == 0) {
766 smmu = tegra_smmu_find(args.np);
767 if (smmu) {
768 err = tegra_smmu_configure(smmu, dev, &args);
769 of_node_put(args.np);
770
771 if (err < 0)
772 return err;
773
774
775
776
777
778
779 dev->archdata.iommu = smmu;
780
781 iommu_device_link(&smmu->iommu, dev);
782
783 break;
784 }
785
786 of_node_put(args.np);
787 index++;
788 }
789
790 if (!smmu)
791 return -ENODEV;
792
793 group = iommu_group_get_for_dev(dev);
794 if (IS_ERR(group))
795 return PTR_ERR(group);
796
797 iommu_group_put(group);
798
799 return 0;
800 }
801
802 static void tegra_smmu_remove_device(struct device *dev)
803 {
804 struct tegra_smmu *smmu = dev->archdata.iommu;
805
806 if (smmu)
807 iommu_device_unlink(&smmu->iommu, dev);
808
809 dev->archdata.iommu = NULL;
810 iommu_group_remove_device(dev);
811 }
812
813 static const struct tegra_smmu_group_soc *
814 tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup)
815 {
816 unsigned int i, j;
817
818 for (i = 0; i < smmu->soc->num_groups; i++)
819 for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++)
820 if (smmu->soc->groups[i].swgroups[j] == swgroup)
821 return &smmu->soc->groups[i];
822
823 return NULL;
824 }
825
826 static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu,
827 unsigned int swgroup)
828 {
829 const struct tegra_smmu_group_soc *soc;
830 struct tegra_smmu_group *group;
831
832 soc = tegra_smmu_find_group(smmu, swgroup);
833 if (!soc)
834 return NULL;
835
836 mutex_lock(&smmu->lock);
837
838 list_for_each_entry(group, &smmu->groups, list)
839 if (group->soc == soc) {
840 mutex_unlock(&smmu->lock);
841 return group->group;
842 }
843
844 group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL);
845 if (!group) {
846 mutex_unlock(&smmu->lock);
847 return NULL;
848 }
849
850 INIT_LIST_HEAD(&group->list);
851 group->soc = soc;
852
853 group->group = iommu_group_alloc();
854 if (IS_ERR(group->group)) {
855 devm_kfree(smmu->dev, group);
856 mutex_unlock(&smmu->lock);
857 return NULL;
858 }
859
860 list_add_tail(&group->list, &smmu->groups);
861 mutex_unlock(&smmu->lock);
862
863 return group->group;
864 }
865
866 static struct iommu_group *tegra_smmu_device_group(struct device *dev)
867 {
868 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
869 struct tegra_smmu *smmu = dev->archdata.iommu;
870 struct iommu_group *group;
871
872 group = tegra_smmu_group_get(smmu, fwspec->ids[0]);
873 if (!group)
874 group = generic_device_group(dev);
875
876 return group;
877 }
878
879 static int tegra_smmu_of_xlate(struct device *dev,
880 struct of_phandle_args *args)
881 {
882 u32 id = args->args[0];
883
884 return iommu_fwspec_add_ids(dev, &id, 1);
885 }
886
887 static const struct iommu_ops tegra_smmu_ops = {
888 .capable = tegra_smmu_capable,
889 .domain_alloc = tegra_smmu_domain_alloc,
890 .domain_free = tegra_smmu_domain_free,
891 .attach_dev = tegra_smmu_attach_dev,
892 .detach_dev = tegra_smmu_detach_dev,
893 .add_device = tegra_smmu_add_device,
894 .remove_device = tegra_smmu_remove_device,
895 .device_group = tegra_smmu_device_group,
896 .map = tegra_smmu_map,
897 .unmap = tegra_smmu_unmap,
898 .iova_to_phys = tegra_smmu_iova_to_phys,
899 .of_xlate = tegra_smmu_of_xlate,
900 .pgsize_bitmap = SZ_4K,
901 };
902
903 static void tegra_smmu_ahb_enable(void)
904 {
905 static const struct of_device_id ahb_match[] = {
906 { .compatible = "nvidia,tegra30-ahb", },
907 { }
908 };
909 struct device_node *ahb;
910
911 ahb = of_find_matching_node(NULL, ahb_match);
912 if (ahb) {
913 tegra_ahb_enable_smmu(ahb);
914 of_node_put(ahb);
915 }
916 }
917
918 static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
919 {
920 struct tegra_smmu *smmu = s->private;
921 unsigned int i;
922 u32 value;
923
924 seq_printf(s, "swgroup enabled ASID\n");
925 seq_printf(s, "------------------------\n");
926
927 for (i = 0; i < smmu->soc->num_swgroups; i++) {
928 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
929 const char *status;
930 unsigned int asid;
931
932 value = smmu_readl(smmu, group->reg);
933
934 if (value & SMMU_ASID_ENABLE)
935 status = "yes";
936 else
937 status = "no";
938
939 asid = value & SMMU_ASID_MASK;
940
941 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
942 asid);
943 }
944
945 return 0;
946 }
947
948 DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups);
949
950 static int tegra_smmu_clients_show(struct seq_file *s, void *data)
951 {
952 struct tegra_smmu *smmu = s->private;
953 unsigned int i;
954 u32 value;
955
956 seq_printf(s, "client enabled\n");
957 seq_printf(s, "--------------------\n");
958
959 for (i = 0; i < smmu->soc->num_clients; i++) {
960 const struct tegra_mc_client *client = &smmu->soc->clients[i];
961 const char *status;
962
963 value = smmu_readl(smmu, client->smmu.reg);
964
965 if (value & BIT(client->smmu.bit))
966 status = "yes";
967 else
968 status = "no";
969
970 seq_printf(s, "%-12s %s\n", client->name, status);
971 }
972
973 return 0;
974 }
975
976 DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients);
977
978 static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
979 {
980 smmu->debugfs = debugfs_create_dir("smmu", NULL);
981 if (!smmu->debugfs)
982 return;
983
984 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
985 &tegra_smmu_swgroups_fops);
986 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
987 &tegra_smmu_clients_fops);
988 }
989
990 static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
991 {
992 debugfs_remove_recursive(smmu->debugfs);
993 }
994
995 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
996 const struct tegra_smmu_soc *soc,
997 struct tegra_mc *mc)
998 {
999 struct tegra_smmu *smmu;
1000 size_t size;
1001 u32 value;
1002 int err;
1003
1004 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1005 if (!smmu)
1006 return ERR_PTR(-ENOMEM);
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016 mc->smmu = smmu;
1017
1018 size = BITS_TO_LONGS(soc->num_asids) * sizeof(long);
1019
1020 smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL);
1021 if (!smmu->asids)
1022 return ERR_PTR(-ENOMEM);
1023
1024 INIT_LIST_HEAD(&smmu->groups);
1025 mutex_init(&smmu->lock);
1026
1027 smmu->regs = mc->regs;
1028 smmu->soc = soc;
1029 smmu->dev = dev;
1030 smmu->mc = mc;
1031
1032 smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
1033 dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
1034 mc->soc->num_address_bits, smmu->pfn_mask);
1035 smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1;
1036 dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
1037 smmu->tlb_mask);
1038
1039 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
1040
1041 if (soc->supports_request_limit)
1042 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
1043
1044 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
1045
1046 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
1047 SMMU_TLB_CONFIG_ACTIVE_LINES(smmu);
1048
1049 if (soc->supports_round_robin_arbitration)
1050 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
1051
1052 smmu_writel(smmu, value, SMMU_TLB_CONFIG);
1053
1054 smmu_flush_ptc_all(smmu);
1055 smmu_flush_tlb(smmu);
1056 smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
1057 smmu_flush(smmu);
1058
1059 tegra_smmu_ahb_enable();
1060
1061 err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev));
1062 if (err)
1063 return ERR_PTR(err);
1064
1065 iommu_device_set_ops(&smmu->iommu, &tegra_smmu_ops);
1066 iommu_device_set_fwnode(&smmu->iommu, dev->fwnode);
1067
1068 err = iommu_device_register(&smmu->iommu);
1069 if (err) {
1070 iommu_device_sysfs_remove(&smmu->iommu);
1071 return ERR_PTR(err);
1072 }
1073
1074 err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
1075 if (err < 0) {
1076 iommu_device_unregister(&smmu->iommu);
1077 iommu_device_sysfs_remove(&smmu->iommu);
1078 return ERR_PTR(err);
1079 }
1080
1081 if (IS_ENABLED(CONFIG_DEBUG_FS))
1082 tegra_smmu_debugfs_init(smmu);
1083
1084 return smmu;
1085 }
1086
1087 void tegra_smmu_remove(struct tegra_smmu *smmu)
1088 {
1089 iommu_device_unregister(&smmu->iommu);
1090 iommu_device_sysfs_remove(&smmu->iommu);
1091
1092 if (IS_ENABLED(CONFIG_DEBUG_FS))
1093 tegra_smmu_debugfs_exit(smmu);
1094 }