This source file includes following definitions.
- ad5592r_gpio_get
- ad5592r_gpio_set
- ad5592r_gpio_direction_input
- ad5592r_gpio_direction_output
- ad5592r_gpio_request
- ad5592r_gpio_init
- ad5592r_gpio_cleanup
- ad5592r_reset
- ad5592r_get_vref
- ad5592r_set_channel_modes
- ad5592r_reset_channel_modes
- ad5592r_write_raw
- ad5592r_read_raw
- ad5592r_write_raw_get_fmt
- ad5592r_show_scale_available
- ad5592r_setup_channel
- ad5592r_alloc_channels
- ad5592r_init_scales
- ad5592r_probe
- ad5592r_remove
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9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/iio/iio.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/of.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/gpio.h>
19 #include <linux/property.h>
20
21 #include <dt-bindings/iio/adi,ad5592r.h>
22
23 #include "ad5592r-base.h"
24
25 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
26 {
27 struct ad5592r_state *st = gpiochip_get_data(chip);
28 int ret = 0;
29 u8 val;
30
31 mutex_lock(&st->gpio_lock);
32
33 if (st->gpio_out & BIT(offset))
34 val = st->gpio_val;
35 else
36 ret = st->ops->gpio_read(st, &val);
37
38 mutex_unlock(&st->gpio_lock);
39
40 if (ret < 0)
41 return ret;
42
43 return !!(val & BIT(offset));
44 }
45
46 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
47 {
48 struct ad5592r_state *st = gpiochip_get_data(chip);
49
50 mutex_lock(&st->gpio_lock);
51
52 if (value)
53 st->gpio_val |= BIT(offset);
54 else
55 st->gpio_val &= ~BIT(offset);
56
57 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
58
59 mutex_unlock(&st->gpio_lock);
60 }
61
62 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
63 {
64 struct ad5592r_state *st = gpiochip_get_data(chip);
65 int ret;
66
67 mutex_lock(&st->gpio_lock);
68
69 st->gpio_out &= ~BIT(offset);
70 st->gpio_in |= BIT(offset);
71
72 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
73 if (ret < 0)
74 goto err_unlock;
75
76 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
77
78 err_unlock:
79 mutex_unlock(&st->gpio_lock);
80
81 return ret;
82 }
83
84 static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
86 {
87 struct ad5592r_state *st = gpiochip_get_data(chip);
88 int ret;
89
90 mutex_lock(&st->gpio_lock);
91
92 if (value)
93 st->gpio_val |= BIT(offset);
94 else
95 st->gpio_val &= ~BIT(offset);
96
97 st->gpio_in &= ~BIT(offset);
98 st->gpio_out |= BIT(offset);
99
100 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
101 if (ret < 0)
102 goto err_unlock;
103
104 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
105 if (ret < 0)
106 goto err_unlock;
107
108 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
109
110 err_unlock:
111 mutex_unlock(&st->gpio_lock);
112
113 return ret;
114 }
115
116 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
117 {
118 struct ad5592r_state *st = gpiochip_get_data(chip);
119
120 if (!(st->gpio_map & BIT(offset))) {
121 dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
122 offset);
123 return -ENODEV;
124 }
125
126 return 0;
127 }
128
129 static int ad5592r_gpio_init(struct ad5592r_state *st)
130 {
131 if (!st->gpio_map)
132 return 0;
133
134 st->gpiochip.label = dev_name(st->dev);
135 st->gpiochip.base = -1;
136 st->gpiochip.ngpio = 8;
137 st->gpiochip.parent = st->dev;
138 st->gpiochip.can_sleep = true;
139 st->gpiochip.direction_input = ad5592r_gpio_direction_input;
140 st->gpiochip.direction_output = ad5592r_gpio_direction_output;
141 st->gpiochip.get = ad5592r_gpio_get;
142 st->gpiochip.set = ad5592r_gpio_set;
143 st->gpiochip.request = ad5592r_gpio_request;
144 st->gpiochip.owner = THIS_MODULE;
145
146 mutex_init(&st->gpio_lock);
147
148 return gpiochip_add_data(&st->gpiochip, st);
149 }
150
151 static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
152 {
153 if (st->gpio_map)
154 gpiochip_remove(&st->gpiochip);
155 }
156
157 static int ad5592r_reset(struct ad5592r_state *st)
158 {
159 struct gpio_desc *gpio;
160 struct iio_dev *iio_dev = iio_priv_to_dev(st);
161
162 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
163 if (IS_ERR(gpio))
164 return PTR_ERR(gpio);
165
166 if (gpio) {
167 udelay(1);
168 gpiod_set_value(gpio, 1);
169 } else {
170 mutex_lock(&iio_dev->mlock);
171
172 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
173 mutex_unlock(&iio_dev->mlock);
174 }
175
176 udelay(250);
177
178 return 0;
179 }
180
181 static int ad5592r_get_vref(struct ad5592r_state *st)
182 {
183 int ret;
184
185 if (st->reg) {
186 ret = regulator_get_voltage(st->reg);
187 if (ret < 0)
188 return ret;
189
190 return ret / 1000;
191 } else {
192 return 2500;
193 }
194 }
195
196 static int ad5592r_set_channel_modes(struct ad5592r_state *st)
197 {
198 const struct ad5592r_rw_ops *ops = st->ops;
199 int ret;
200 unsigned i;
201 struct iio_dev *iio_dev = iio_priv_to_dev(st);
202 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
203 u16 read_back;
204
205 for (i = 0; i < st->num_channels; i++) {
206 switch (st->channel_modes[i]) {
207 case CH_MODE_DAC:
208 dac |= BIT(i);
209 break;
210
211 case CH_MODE_ADC:
212 adc |= BIT(i);
213 break;
214
215 case CH_MODE_DAC_AND_ADC:
216 dac |= BIT(i);
217 adc |= BIT(i);
218 break;
219
220 case CH_MODE_GPIO:
221 st->gpio_map |= BIT(i);
222 st->gpio_in |= BIT(i);
223 break;
224
225 case CH_MODE_UNUSED:
226
227 default:
228 switch (st->channel_offstate[i]) {
229 case CH_OFFSTATE_OUT_TRISTATE:
230 tristate |= BIT(i);
231 break;
232
233 case CH_OFFSTATE_OUT_LOW:
234 st->gpio_out |= BIT(i);
235 break;
236
237 case CH_OFFSTATE_OUT_HIGH:
238 st->gpio_out |= BIT(i);
239 st->gpio_val |= BIT(i);
240 break;
241
242 case CH_OFFSTATE_PULLDOWN:
243
244 default:
245 pulldown |= BIT(i);
246 break;
247 }
248 }
249 }
250
251 mutex_lock(&iio_dev->mlock);
252
253
254 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
255 if (ret)
256 goto err_unlock;
257
258 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
259 if (ret)
260 goto err_unlock;
261
262
263 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
264 if (ret)
265 goto err_unlock;
266
267 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
268 if (ret)
269 goto err_unlock;
270
271 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
272 if (ret)
273 goto err_unlock;
274
275 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
276 if (ret)
277 goto err_unlock;
278
279 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
280 if (ret)
281 goto err_unlock;
282
283
284 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
285 if (!ret && (read_back & 0xff) != adc)
286 ret = -EIO;
287
288 err_unlock:
289 mutex_unlock(&iio_dev->mlock);
290 return ret;
291 }
292
293 static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
294 {
295 int i;
296
297 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
298 st->channel_modes[i] = CH_MODE_UNUSED;
299
300 return ad5592r_set_channel_modes(st);
301 }
302
303 static int ad5592r_write_raw(struct iio_dev *iio_dev,
304 struct iio_chan_spec const *chan, int val, int val2, long mask)
305 {
306 struct ad5592r_state *st = iio_priv(iio_dev);
307 int ret;
308
309 switch (mask) {
310 case IIO_CHAN_INFO_RAW:
311
312 if (val >= (1 << chan->scan_type.realbits) || val < 0)
313 return -EINVAL;
314
315 if (!chan->output)
316 return -EINVAL;
317
318 mutex_lock(&iio_dev->mlock);
319 ret = st->ops->write_dac(st, chan->channel, val);
320 if (!ret)
321 st->cached_dac[chan->channel] = val;
322 mutex_unlock(&iio_dev->mlock);
323 return ret;
324 case IIO_CHAN_INFO_SCALE:
325 if (chan->type == IIO_VOLTAGE) {
326 bool gain;
327
328 if (val == st->scale_avail[0][0] &&
329 val2 == st->scale_avail[0][1])
330 gain = false;
331 else if (val == st->scale_avail[1][0] &&
332 val2 == st->scale_avail[1][1])
333 gain = true;
334 else
335 return -EINVAL;
336
337 mutex_lock(&iio_dev->mlock);
338
339 ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
340 &st->cached_gp_ctrl);
341 if (ret < 0) {
342 mutex_unlock(&iio_dev->mlock);
343 return ret;
344 }
345
346 if (chan->output) {
347 if (gain)
348 st->cached_gp_ctrl |=
349 AD5592R_REG_CTRL_DAC_RANGE;
350 else
351 st->cached_gp_ctrl &=
352 ~AD5592R_REG_CTRL_DAC_RANGE;
353 } else {
354 if (gain)
355 st->cached_gp_ctrl |=
356 AD5592R_REG_CTRL_ADC_RANGE;
357 else
358 st->cached_gp_ctrl &=
359 ~AD5592R_REG_CTRL_ADC_RANGE;
360 }
361
362 ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
363 st->cached_gp_ctrl);
364 mutex_unlock(&iio_dev->mlock);
365
366 return ret;
367 }
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 return 0;
374 }
375
376 static int ad5592r_read_raw(struct iio_dev *iio_dev,
377 struct iio_chan_spec const *chan,
378 int *val, int *val2, long m)
379 {
380 struct ad5592r_state *st = iio_priv(iio_dev);
381 u16 read_val;
382 int ret;
383
384 switch (m) {
385 case IIO_CHAN_INFO_RAW:
386 mutex_lock(&iio_dev->mlock);
387
388 if (!chan->output) {
389 ret = st->ops->read_adc(st, chan->channel, &read_val);
390 if (ret)
391 goto unlock;
392
393 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
394 dev_err(st->dev, "Error while reading channel %u\n",
395 chan->channel);
396 ret = -EIO;
397 goto unlock;
398 }
399
400 read_val &= GENMASK(11, 0);
401
402 } else {
403 read_val = st->cached_dac[chan->channel];
404 }
405
406 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
407 chan->channel, read_val);
408
409 *val = (int) read_val;
410 ret = IIO_VAL_INT;
411 break;
412 case IIO_CHAN_INFO_SCALE:
413 *val = ad5592r_get_vref(st);
414
415 if (chan->type == IIO_TEMP) {
416 s64 tmp = *val * (3767897513LL / 25LL);
417 *val = div_s64_rem(tmp, 1000000000LL, val2);
418
419 ret = IIO_VAL_INT_PLUS_MICRO;
420 } else {
421 int mult;
422
423 mutex_lock(&iio_dev->mlock);
424
425 if (chan->output)
426 mult = !!(st->cached_gp_ctrl &
427 AD5592R_REG_CTRL_DAC_RANGE);
428 else
429 mult = !!(st->cached_gp_ctrl &
430 AD5592R_REG_CTRL_ADC_RANGE);
431
432 *val *= ++mult;
433
434 *val2 = chan->scan_type.realbits;
435 ret = IIO_VAL_FRACTIONAL_LOG2;
436 }
437 break;
438 case IIO_CHAN_INFO_OFFSET:
439 ret = ad5592r_get_vref(st);
440
441 mutex_lock(&iio_dev->mlock);
442
443 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
444 *val = (-34365 * 25) / ret;
445 else
446 *val = (-75365 * 25) / ret;
447 ret = IIO_VAL_INT;
448 break;
449 default:
450 ret = -EINVAL;
451 }
452
453 unlock:
454 mutex_unlock(&iio_dev->mlock);
455 return ret;
456 }
457
458 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
459 struct iio_chan_spec const *chan, long mask)
460 {
461 switch (mask) {
462 case IIO_CHAN_INFO_SCALE:
463 return IIO_VAL_INT_PLUS_NANO;
464
465 default:
466 return IIO_VAL_INT_PLUS_MICRO;
467 }
468
469 return -EINVAL;
470 }
471
472 static const struct iio_info ad5592r_info = {
473 .read_raw = ad5592r_read_raw,
474 .write_raw = ad5592r_write_raw,
475 .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
476 };
477
478 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
479 uintptr_t private,
480 const struct iio_chan_spec *chan,
481 char *buf)
482 {
483 struct ad5592r_state *st = iio_priv(iio_dev);
484
485 return sprintf(buf, "%d.%09u %d.%09u\n",
486 st->scale_avail[0][0], st->scale_avail[0][1],
487 st->scale_avail[1][0], st->scale_avail[1][1]);
488 }
489
490 static struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
491 {
492 .name = "scale_available",
493 .read = ad5592r_show_scale_available,
494 .shared = true,
495 },
496 {},
497 };
498
499 static void ad5592r_setup_channel(struct iio_dev *iio_dev,
500 struct iio_chan_spec *chan, bool output, unsigned id)
501 {
502 chan->type = IIO_VOLTAGE;
503 chan->indexed = 1;
504 chan->output = output;
505 chan->channel = id;
506 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
507 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
508 chan->scan_type.sign = 'u';
509 chan->scan_type.realbits = 12;
510 chan->scan_type.storagebits = 16;
511 chan->ext_info = ad5592r_ext_info;
512 }
513
514 static int ad5592r_alloc_channels(struct ad5592r_state *st)
515 {
516 unsigned i, curr_channel = 0,
517 num_channels = st->num_channels;
518 struct iio_dev *iio_dev = iio_priv_to_dev(st);
519 struct iio_chan_spec *channels;
520 struct fwnode_handle *child;
521 u32 reg, tmp;
522 int ret;
523
524 device_for_each_child_node(st->dev, child) {
525 ret = fwnode_property_read_u32(child, "reg", ®);
526 if (ret || reg >= ARRAY_SIZE(st->channel_modes))
527 continue;
528
529 ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
530 if (!ret)
531 st->channel_modes[reg] = tmp;
532
533 fwnode_property_read_u32(child, "adi,off-state", &tmp);
534 if (!ret)
535 st->channel_offstate[reg] = tmp;
536 }
537
538 channels = devm_kcalloc(st->dev,
539 1 + 2 * num_channels, sizeof(*channels),
540 GFP_KERNEL);
541 if (!channels)
542 return -ENOMEM;
543
544 for (i = 0; i < num_channels; i++) {
545 switch (st->channel_modes[i]) {
546 case CH_MODE_DAC:
547 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
548 true, i);
549 curr_channel++;
550 break;
551
552 case CH_MODE_ADC:
553 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
554 false, i);
555 curr_channel++;
556 break;
557
558 case CH_MODE_DAC_AND_ADC:
559 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
560 true, i);
561 curr_channel++;
562 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
563 false, i);
564 curr_channel++;
565 break;
566
567 default:
568 continue;
569 }
570 }
571
572 channels[curr_channel].type = IIO_TEMP;
573 channels[curr_channel].channel = 8;
574 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
575 BIT(IIO_CHAN_INFO_SCALE) |
576 BIT(IIO_CHAN_INFO_OFFSET);
577 curr_channel++;
578
579 iio_dev->num_channels = curr_channel;
580 iio_dev->channels = channels;
581
582 return 0;
583 }
584
585 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
586 {
587 s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
588
589 st->scale_avail[0][0] =
590 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
591 st->scale_avail[1][0] =
592 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
593 }
594
595 int ad5592r_probe(struct device *dev, const char *name,
596 const struct ad5592r_rw_ops *ops)
597 {
598 struct iio_dev *iio_dev;
599 struct ad5592r_state *st;
600 int ret;
601
602 iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
603 if (!iio_dev)
604 return -ENOMEM;
605
606 st = iio_priv(iio_dev);
607 st->dev = dev;
608 st->ops = ops;
609 st->num_channels = 8;
610 dev_set_drvdata(dev, iio_dev);
611
612 st->reg = devm_regulator_get_optional(dev, "vref");
613 if (IS_ERR(st->reg)) {
614 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node)
615 return PTR_ERR(st->reg);
616
617 st->reg = NULL;
618 } else {
619 ret = regulator_enable(st->reg);
620 if (ret)
621 return ret;
622 }
623
624 iio_dev->dev.parent = dev;
625 iio_dev->name = name;
626 iio_dev->info = &ad5592r_info;
627 iio_dev->modes = INDIO_DIRECT_MODE;
628
629 ad5592r_init_scales(st, ad5592r_get_vref(st));
630
631 ret = ad5592r_reset(st);
632 if (ret)
633 goto error_disable_reg;
634
635 ret = ops->reg_write(st, AD5592R_REG_PD,
636 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
637 if (ret)
638 goto error_disable_reg;
639
640 ret = ad5592r_alloc_channels(st);
641 if (ret)
642 goto error_disable_reg;
643
644 ret = ad5592r_set_channel_modes(st);
645 if (ret)
646 goto error_reset_ch_modes;
647
648 ret = iio_device_register(iio_dev);
649 if (ret)
650 goto error_reset_ch_modes;
651
652 ret = ad5592r_gpio_init(st);
653 if (ret)
654 goto error_dev_unregister;
655
656 return 0;
657
658 error_dev_unregister:
659 iio_device_unregister(iio_dev);
660
661 error_reset_ch_modes:
662 ad5592r_reset_channel_modes(st);
663
664 error_disable_reg:
665 if (st->reg)
666 regulator_disable(st->reg);
667
668 return ret;
669 }
670 EXPORT_SYMBOL_GPL(ad5592r_probe);
671
672 int ad5592r_remove(struct device *dev)
673 {
674 struct iio_dev *iio_dev = dev_get_drvdata(dev);
675 struct ad5592r_state *st = iio_priv(iio_dev);
676
677 iio_device_unregister(iio_dev);
678 ad5592r_reset_channel_modes(st);
679 ad5592r_gpio_cleanup(st);
680
681 if (st->reg)
682 regulator_disable(st->reg);
683
684 return 0;
685 }
686 EXPORT_SYMBOL_GPL(ad5592r_remove);
687
688 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
689 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
690 MODULE_LICENSE("GPL v2");