This source file includes following definitions.
- lpc32xx_read_raw
- lpc32xx_adc_isr
- lpc32xx_adc_probe
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10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/err.h>
13 #include <linux/iio/iio.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19
20
21
22
23 #define LPC32XXAD_SELECT(x) ((x) + 0x04)
24 #define LPC32XXAD_CTRL(x) ((x) + 0x08)
25 #define LPC32XXAD_VALUE(x) ((x) + 0x48)
26
27
28
29 #define LPC32XXAD_REFm 0x00000200
30
31 #define LPC32XXAD_REFp 0x00000080
32
33 #define LPC32XXAD_IN 0x00000010
34
35 #define LPC32XXAD_INTERNAL 0x00000004
36
37
38 #define LPC32XXAD_STROBE 0x00000002
39 #define LPC32XXAD_PDN_CTRL 0x00000004
40
41
42 #define LPC32XXAD_VALUE_MASK 0x000003FF
43
44 #define LPC32XXAD_NAME "lpc32xx-adc"
45
46 struct lpc32xx_adc_state {
47 void __iomem *adc_base;
48 struct clk *clk;
49 struct completion completion;
50 struct regulator *vref;
51
52 u32 value;
53 };
54
55 static int lpc32xx_read_raw(struct iio_dev *indio_dev,
56 struct iio_chan_spec const *chan,
57 int *val,
58 int *val2,
59 long mask)
60 {
61 struct lpc32xx_adc_state *st = iio_priv(indio_dev);
62 int ret;
63
64 switch (mask) {
65 case IIO_CHAN_INFO_RAW:
66 mutex_lock(&indio_dev->mlock);
67 ret = clk_prepare_enable(st->clk);
68 if (ret) {
69 mutex_unlock(&indio_dev->mlock);
70 return ret;
71 }
72
73 __raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
74 LPC32XXAD_REFp | LPC32XXAD_REFm,
75 LPC32XXAD_SELECT(st->adc_base));
76
77 __raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
78 LPC32XXAD_CTRL(st->adc_base));
79 wait_for_completion(&st->completion);
80 clk_disable_unprepare(st->clk);
81 *val = st->value;
82 mutex_unlock(&indio_dev->mlock);
83
84 return IIO_VAL_INT;
85
86 case IIO_CHAN_INFO_SCALE:
87 *val = regulator_get_voltage(st->vref) / 1000;
88 *val2 = 10;
89
90 return IIO_VAL_FRACTIONAL_LOG2;
91 default:
92 return -EINVAL;
93 }
94 }
95
96 static const struct iio_info lpc32xx_adc_iio_info = {
97 .read_raw = &lpc32xx_read_raw,
98 };
99
100 #define LPC32XX_ADC_CHANNEL_BASE(_index) \
101 .type = IIO_VOLTAGE, \
102 .indexed = 1, \
103 .channel = _index, \
104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
105 .address = LPC32XXAD_IN * _index, \
106 .scan_index = _index,
107
108 #define LPC32XX_ADC_CHANNEL(_index) { \
109 LPC32XX_ADC_CHANNEL_BASE(_index) \
110 }
111
112 #define LPC32XX_ADC_SCALE_CHANNEL(_index) { \
113 LPC32XX_ADC_CHANNEL_BASE(_index) \
114 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
115 }
116
117 static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
118 LPC32XX_ADC_CHANNEL(0),
119 LPC32XX_ADC_CHANNEL(1),
120 LPC32XX_ADC_CHANNEL(2),
121 };
122
123 static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
124 LPC32XX_ADC_SCALE_CHANNEL(0),
125 LPC32XX_ADC_SCALE_CHANNEL(1),
126 LPC32XX_ADC_SCALE_CHANNEL(2),
127 };
128
129 static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
130 {
131 struct lpc32xx_adc_state *st = dev_id;
132
133
134 st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
135 LPC32XXAD_VALUE_MASK;
136 complete(&st->completion);
137
138 return IRQ_HANDLED;
139 }
140
141 static int lpc32xx_adc_probe(struct platform_device *pdev)
142 {
143 struct lpc32xx_adc_state *st = NULL;
144 struct resource *res;
145 int retval = -ENODEV;
146 struct iio_dev *iodev = NULL;
147 int irq;
148
149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
150 if (!res) {
151 dev_err(&pdev->dev, "failed to get platform I/O memory\n");
152 return -ENXIO;
153 }
154
155 iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
156 if (!iodev)
157 return -ENOMEM;
158
159 st = iio_priv(iodev);
160
161 st->adc_base = devm_ioremap(&pdev->dev, res->start,
162 resource_size(res));
163 if (!st->adc_base) {
164 dev_err(&pdev->dev, "failed mapping memory\n");
165 return -EBUSY;
166 }
167
168 st->clk = devm_clk_get(&pdev->dev, NULL);
169 if (IS_ERR(st->clk)) {
170 dev_err(&pdev->dev, "failed getting clock\n");
171 return PTR_ERR(st->clk);
172 }
173
174 irq = platform_get_irq(pdev, 0);
175 if (irq <= 0)
176 return -ENXIO;
177
178 retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
179 LPC32XXAD_NAME, st);
180 if (retval < 0) {
181 dev_err(&pdev->dev, "failed requesting interrupt\n");
182 return retval;
183 }
184
185 st->vref = devm_regulator_get(&pdev->dev, "vref");
186 if (IS_ERR(st->vref)) {
187 iodev->channels = lpc32xx_adc_iio_channels;
188 dev_info(&pdev->dev,
189 "Missing vref regulator: No scaling available\n");
190 } else {
191 iodev->channels = lpc32xx_adc_iio_scale_channels;
192 }
193
194 platform_set_drvdata(pdev, iodev);
195
196 init_completion(&st->completion);
197
198 iodev->name = LPC32XXAD_NAME;
199 iodev->dev.parent = &pdev->dev;
200 iodev->info = &lpc32xx_adc_iio_info;
201 iodev->modes = INDIO_DIRECT_MODE;
202 iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
203
204 retval = devm_iio_device_register(&pdev->dev, iodev);
205 if (retval)
206 return retval;
207
208 dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
209
210 return 0;
211 }
212
213 #ifdef CONFIG_OF
214 static const struct of_device_id lpc32xx_adc_match[] = {
215 { .compatible = "nxp,lpc3220-adc" },
216 {},
217 };
218 MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
219 #endif
220
221 static struct platform_driver lpc32xx_adc_driver = {
222 .probe = lpc32xx_adc_probe,
223 .driver = {
224 .name = LPC32XXAD_NAME,
225 .of_match_table = of_match_ptr(lpc32xx_adc_match),
226 },
227 };
228
229 module_platform_driver(lpc32xx_adc_driver);
230
231 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
232 MODULE_DESCRIPTION("LPC32XX ADC driver");
233 MODULE_LICENSE("GPL");