drivers/vfio/pci/vfio_pci

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This source file includes following definitions.
vfio_user_config_read
vfio_user_config_write
vfio_default_config_read
vfio_default_config_write
vfio_direct_config_read
vfio_raw_config_write
vfio_raw_config_read
vfio_virt_config_write
vfio_virt_config_read
free_perm_bits
alloc_perm_bits
p_setb
p_setw
p_setd
vfio_bar_restore
vfio_generate_bar_flags
vfio_bar_fixup
vfio_basic_config_read
vfio_need_bar_restore
vfio_basic_config_write
init_pci_cap_basic_perm
vfio_pm_config_write
init_pci_cap_pm_perm
vfio_vpd_config_write
init_pci_cap_vpd_perm
init_pci_cap_pcix_perm
vfio_exp_config_write
init_pci_cap_exp_perm
vfio_af_config_write
init_pci_cap_af_perm
init_pci_ext_cap_err_perm
init_pci_ext_cap_pwr_perm
vfio_pci_uninit_perm_bits
vfio_pci_init_perm_bits
vfio_find_cap_start
vfio_msi_config_read
vfio_msi_config_write
init_pci_cap_msi_perm
vfio_msi_cap_len
vfio_vc_cap_len
vfio_cap_len
vfio_ext_cap_len
vfio_fill_vconfig_bytes
vfio_cap_init
vfio_ecap_init
vfio_config_init
vfio_config_free
vfio_pci_cap_remaining_dword
vfio_config_do_rw
vfio_pci_config_rw
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * VFIO PCI config space virtualization
   4  *
   5  * Copyright (C) 2012 Red Hat, Inc.  All rights reserved.
   6  *     Author: Alex Williamson <alex.williamson@redhat.com>
   7  *
   8  * Derived from original vfio:
   9  * Copyright 2010 Cisco Systems, Inc.  All rights reserved.
  10  * Author: Tom Lyon, pugs@cisco.com
  11  */
  12 
  13 /*
  14  * This code handles reading and writing of PCI configuration registers.
  15  * This is hairy because we want to allow a lot of flexibility to the
  16  * user driver, but cannot trust it with all of the config fields.
  17  * Tables determine which fields can be read and written, as well as
  18  * which fields are 'virtualized' - special actions and translations to
  19  * make it appear to the user that he has control, when in fact things
  20  * must be negotiated with the underlying OS.
  21  */
  22 
  23 #include <linux/fs.h>
  24 #include <linux/pci.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/vfio.h>
  27 #include <linux/slab.h>
  28 
  29 #include "vfio_pci_private.h"
  30 
  31 /* Fake capability ID for standard config space */
  32 #define PCI_CAP_ID_BASIC        0
  33 
  34 #define is_bar(offset)  \
  35         ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
  36          (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
  37 
  38 /*
  39  * Lengths of PCI Config Capabilities
  40  *   0: Removed from the user visible capability list
  41  *   FF: Variable length
  42  */
  43 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
  44         [PCI_CAP_ID_BASIC]      = PCI_STD_HEADER_SIZEOF, /* pci config header */
  45         [PCI_CAP_ID_PM]         = PCI_PM_SIZEOF,
  46         [PCI_CAP_ID_AGP]        = PCI_AGP_SIZEOF,
  47         [PCI_CAP_ID_VPD]        = PCI_CAP_VPD_SIZEOF,
  48         [PCI_CAP_ID_SLOTID]     = 0,            /* bridge - don't care */
  49         [PCI_CAP_ID_MSI]        = 0xFF,         /* 10, 14, 20, or 24 */
  50         [PCI_CAP_ID_CHSWP]      = 0,            /* cpci - not yet */
  51         [PCI_CAP_ID_PCIX]       = 0xFF,         /* 8 or 24 */
  52         [PCI_CAP_ID_HT]         = 0xFF,         /* hypertransport */
  53         [PCI_CAP_ID_VNDR]       = 0xFF,         /* variable */
  54         [PCI_CAP_ID_DBG]        = 0,            /* debug - don't care */
  55         [PCI_CAP_ID_CCRC]       = 0,            /* cpci - not yet */
  56         [PCI_CAP_ID_SHPC]       = 0,            /* hotswap - not yet */
  57         [PCI_CAP_ID_SSVID]      = 0,            /* bridge - don't care */
  58         [PCI_CAP_ID_AGP3]       = 0,            /* AGP8x - not yet */
  59         [PCI_CAP_ID_SECDEV]     = 0,            /* secure device not yet */
  60         [PCI_CAP_ID_EXP]        = 0xFF,         /* 20 or 44 */
  61         [PCI_CAP_ID_MSIX]       = PCI_CAP_MSIX_SIZEOF,
  62         [PCI_CAP_ID_SATA]       = 0xFF,
  63         [PCI_CAP_ID_AF]         = PCI_CAP_AF_SIZEOF,
  64 };
  65 
  66 /*
  67  * Lengths of PCIe/PCI-X Extended Config Capabilities
  68  *   0: Removed or masked from the user visible capability list
  69  *   FF: Variable length
  70  */
  71 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
  72         [PCI_EXT_CAP_ID_ERR]    =       PCI_ERR_ROOT_COMMAND,
  73         [PCI_EXT_CAP_ID_VC]     =       0xFF,
  74         [PCI_EXT_CAP_ID_DSN]    =       PCI_EXT_CAP_DSN_SIZEOF,
  75         [PCI_EXT_CAP_ID_PWR]    =       PCI_EXT_CAP_PWR_SIZEOF,
  76         [PCI_EXT_CAP_ID_RCLD]   =       0,      /* root only - don't care */
  77         [PCI_EXT_CAP_ID_RCILC]  =       0,      /* root only - don't care */
  78         [PCI_EXT_CAP_ID_RCEC]   =       0,      /* root only - don't care */
  79         [PCI_EXT_CAP_ID_MFVC]   =       0xFF,
  80         [PCI_EXT_CAP_ID_VC9]    =       0xFF,   /* same as CAP_ID_VC */
  81         [PCI_EXT_CAP_ID_RCRB]   =       0,      /* root only - don't care */
  82         [PCI_EXT_CAP_ID_VNDR]   =       0xFF,
  83         [PCI_EXT_CAP_ID_CAC]    =       0,      /* obsolete */
  84         [PCI_EXT_CAP_ID_ACS]    =       0xFF,
  85         [PCI_EXT_CAP_ID_ARI]    =       PCI_EXT_CAP_ARI_SIZEOF,
  86         [PCI_EXT_CAP_ID_ATS]    =       PCI_EXT_CAP_ATS_SIZEOF,
  87         [PCI_EXT_CAP_ID_SRIOV]  =       PCI_EXT_CAP_SRIOV_SIZEOF,
  88         [PCI_EXT_CAP_ID_MRIOV]  =       0,      /* not yet */
  89         [PCI_EXT_CAP_ID_MCAST]  =       PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
  90         [PCI_EXT_CAP_ID_PRI]    =       PCI_EXT_CAP_PRI_SIZEOF,
  91         [PCI_EXT_CAP_ID_AMD_XXX] =      0,      /* not yet */
  92         [PCI_EXT_CAP_ID_REBAR]  =       0xFF,
  93         [PCI_EXT_CAP_ID_DPA]    =       0xFF,
  94         [PCI_EXT_CAP_ID_TPH]    =       0xFF,
  95         [PCI_EXT_CAP_ID_LTR]    =       PCI_EXT_CAP_LTR_SIZEOF,
  96         [PCI_EXT_CAP_ID_SECPCI] =       0,      /* not yet */
  97         [PCI_EXT_CAP_ID_PMUX]   =       0,      /* not yet */
  98         [PCI_EXT_CAP_ID_PASID]  =       0,      /* not yet */
  99 };
 100 
 101 /*
 102  * Read/Write Permission Bits - one bit for each bit in capability
 103  * Any field can be read if it exists, but what is read depends on
 104  * whether the field is 'virtualized', or just pass thru to the
 105  * hardware.  Any virtualized field is also virtualized for writes.
 106  * Writes are only permitted if they have a 1 bit here.
 107  */
 108 struct perm_bits {
 109         u8      *virt;          /* read/write virtual data, not hw */
 110         u8      *write;         /* writeable bits */
 111         int     (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
 112                           struct perm_bits *perm, int offset, __le32 *val);
 113         int     (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
 114                            struct perm_bits *perm, int offset, __le32 val);
 115 };
 116 
 117 #define NO_VIRT         0
 118 #define ALL_VIRT        0xFFFFFFFFU
 119 #define NO_WRITE        0
 120 #define ALL_WRITE       0xFFFFFFFFU
 121 
 122 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
 123                                  __le32 *val, int count)
 124 {
 125         int ret = -EINVAL;
 126         u32 tmp_val = 0;
 127 
 128         switch (count) {
 129         case 1:
 130         {
 131                 u8 tmp;
 132                 ret = pci_user_read_config_byte(pdev, offset, &tmp);
 133                 tmp_val = tmp;
 134                 break;
 135         }
 136         case 2:
 137         {
 138                 u16 tmp;
 139                 ret = pci_user_read_config_word(pdev, offset, &tmp);
 140                 tmp_val = tmp;
 141                 break;
 142         }
 143         case 4:
 144                 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
 145                 break;
 146         }
 147 
 148         *val = cpu_to_le32(tmp_val);
 149 
 150         return ret;
 151 }
 152 
 153 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
 154                                   __le32 val, int count)
 155 {
 156         int ret = -EINVAL;
 157         u32 tmp_val = le32_to_cpu(val);
 158 
 159         switch (count) {
 160         case 1:
 161                 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
 162                 break;
 163         case 2:
 164                 ret = pci_user_write_config_word(pdev, offset, tmp_val);
 165                 break;
 166         case 4:
 167                 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
 168                 break;
 169         }
 170 
 171         return ret;
 172 }
 173 
 174 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
 175                                     int count, struct perm_bits *perm,
 176                                     int offset, __le32 *val)
 177 {
 178         __le32 virt = 0;
 179 
 180         memcpy(val, vdev->vconfig + pos, count);
 181 
 182         memcpy(&virt, perm->virt + offset, count);
 183 
 184         /* Any non-virtualized bits? */
 185         if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
 186                 struct pci_dev *pdev = vdev->pdev;
 187                 __le32 phys_val = 0;
 188                 int ret;
 189 
 190                 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
 191                 if (ret)
 192                         return ret;
 193 
 194                 *val = (phys_val & ~virt) | (*val & virt);
 195         }
 196 
 197         return count;
 198 }
 199 
 200 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
 201                                      int count, struct perm_bits *perm,
 202                                      int offset, __le32 val)
 203 {
 204         __le32 virt = 0, write = 0;
 205 
 206         memcpy(&write, perm->write + offset, count);
 207 
 208         if (!write)
 209                 return count; /* drop, no writable bits */
 210 
 211         memcpy(&virt, perm->virt + offset, count);
 212 
 213         /* Virtualized and writable bits go to vconfig */
 214         if (write & virt) {
 215                 __le32 virt_val = 0;
 216 
 217                 memcpy(&virt_val, vdev->vconfig + pos, count);
 218 
 219                 virt_val &= ~(write & virt);
 220                 virt_val |= (val & (write & virt));
 221 
 222                 memcpy(vdev->vconfig + pos, &virt_val, count);
 223         }
 224 
 225         /* Non-virtualzed and writable bits go to hardware */
 226         if (write & ~virt) {
 227                 struct pci_dev *pdev = vdev->pdev;
 228                 __le32 phys_val = 0;
 229                 int ret;
 230 
 231                 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
 232                 if (ret)
 233                         return ret;
 234 
 235                 phys_val &= ~(write & ~virt);
 236                 phys_val |= (val & (write & ~virt));
 237 
 238                 ret = vfio_user_config_write(pdev, pos, phys_val, count);
 239                 if (ret)
 240                         return ret;
 241         }
 242 
 243         return count;
 244 }
 245 
 246 /* Allow direct read from hardware, except for capability next pointer */
 247 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
 248                                    int count, struct perm_bits *perm,
 249                                    int offset, __le32 *val)
 250 {
 251         int ret;
 252 
 253         ret = vfio_user_config_read(vdev->pdev, pos, val, count);
 254         if (ret)
 255                 return ret;
 256 
 257         if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
 258                 if (offset < 4)
 259                         memcpy(val, vdev->vconfig + pos, count);
 260         } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
 261                 if (offset == PCI_CAP_LIST_ID && count > 1)
 262                         memcpy(val, vdev->vconfig + pos,
 263                                min(PCI_CAP_FLAGS, count));
 264                 else if (offset == PCI_CAP_LIST_NEXT)
 265                         memcpy(val, vdev->vconfig + pos, 1);
 266         }
 267 
 268         return count;
 269 }
 270 
 271 /* Raw access skips any kind of virtualization */
 272 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
 273                                  int count, struct perm_bits *perm,
 274                                  int offset, __le32 val)
 275 {
 276         int ret;
 277 
 278         ret = vfio_user_config_write(vdev->pdev, pos, val, count);
 279         if (ret)
 280                 return ret;
 281 
 282         return count;
 283 }
 284 
 285 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
 286                                 int count, struct perm_bits *perm,
 287                                 int offset, __le32 *val)
 288 {
 289         int ret;
 290 
 291         ret = vfio_user_config_read(vdev->pdev, pos, val, count);
 292         if (ret)
 293                 return ret;
 294 
 295         return count;
 296 }
 297 
 298 /* Virt access uses only virtualization */
 299 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
 300                                   int count, struct perm_bits *perm,
 301                                   int offset, __le32 val)
 302 {
 303         memcpy(vdev->vconfig + pos, &val, count);
 304         return count;
 305 }
 306 
 307 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
 308                                  int count, struct perm_bits *perm,
 309                                  int offset, __le32 *val)
 310 {
 311         memcpy(val, vdev->vconfig + pos, count);
 312         return count;
 313 }
 314 
 315 /* Default capability regions to read-only, no-virtualization */
 316 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
 317         [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
 318 };
 319 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
 320         [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
 321 };
 322 /*
 323  * Default unassigned regions to raw read-write access.  Some devices
 324  * require this to function as they hide registers between the gaps in
 325  * config space (be2net).  Like MMIO and I/O port registers, we have
 326  * to trust the hardware isolation.
 327  */
 328 static struct perm_bits unassigned_perms = {
 329         .readfn = vfio_raw_config_read,
 330         .writefn = vfio_raw_config_write
 331 };
 332 
 333 static struct perm_bits virt_perms = {
 334         .readfn = vfio_virt_config_read,
 335         .writefn = vfio_virt_config_write
 336 };
 337 
 338 static void free_perm_bits(struct perm_bits *perm)
 339 {
 340         kfree(perm->virt);
 341         kfree(perm->write);
 342         perm->virt = NULL;
 343         perm->write = NULL;
 344 }
 345 
 346 static int alloc_perm_bits(struct perm_bits *perm, int size)
 347 {
 348         /*
 349          * Round up all permission bits to the next dword, this lets us
 350          * ignore whether a read/write exceeds the defined capability
 351          * structure.  We can do this because:
 352          *  - Standard config space is already dword aligned
 353          *  - Capabilities are all dword aligned (bits 0:1 of next reserved)
 354          *  - Express capabilities defined as dword aligned
 355          */
 356         size = round_up(size, 4);
 357 
 358         /*
 359          * Zero state is
 360          * - All Readable, None Writeable, None Virtualized
 361          */
 362         perm->virt = kzalloc(size, GFP_KERNEL);
 363         perm->write = kzalloc(size, GFP_KERNEL);
 364         if (!perm->virt || !perm->write) {
 365                 free_perm_bits(perm);
 366                 return -ENOMEM;
 367         }
 368 
 369         perm->readfn = vfio_default_config_read;
 370         perm->writefn = vfio_default_config_write;
 371 
 372         return 0;
 373 }
 374 
 375 /*
 376  * Helper functions for filling in permission tables
 377  */
 378 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
 379 {
 380         p->virt[off] = virt;
 381         p->write[off] = write;
 382 }
 383 
 384 /* Handle endian-ness - pci and tables are little-endian */
 385 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
 386 {
 387         *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
 388         *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
 389 }
 390 
 391 /* Handle endian-ness - pci and tables are little-endian */
 392 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
 393 {
 394         *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
 395         *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
 396 }
 397 
 398 /*
 399  * Restore the *real* BARs after we detect a FLR or backdoor reset.
 400  * (backdoor = some device specific technique that we didn't catch)
 401  */
 402 static void vfio_bar_restore(struct vfio_pci_device *vdev)
 403 {
 404         struct pci_dev *pdev = vdev->pdev;
 405         u32 *rbar = vdev->rbar;
 406         u16 cmd;
 407         int i;
 408 
 409         if (pdev->is_virtfn)
 410                 return;
 411 
 412         pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__);
 413 
 414         for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
 415                 pci_user_write_config_dword(pdev, i, *rbar);
 416 
 417         pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
 418 
 419         if (vdev->nointx) {
 420                 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
 421                 cmd |= PCI_COMMAND_INTX_DISABLE;
 422                 pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
 423         }
 424 }
 425 
 426 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
 427 {
 428         unsigned long flags = pci_resource_flags(pdev, bar);
 429         u32 val;
 430 
 431         if (flags & IORESOURCE_IO)
 432                 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
 433 
 434         val = PCI_BASE_ADDRESS_SPACE_MEMORY;
 435 
 436         if (flags & IORESOURCE_PREFETCH)
 437                 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
 438 
 439         if (flags & IORESOURCE_MEM_64)
 440                 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
 441 
 442         return cpu_to_le32(val);
 443 }
 444 
 445 /*
 446  * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
 447  * to reflect the hardware capabilities.  This implements BAR sizing.
 448  */
 449 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
 450 {
 451         struct pci_dev *pdev = vdev->pdev;
 452         int i;
 453         __le32 *bar;
 454         u64 mask;
 455 
 456         bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
 457 
 458         for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
 459                 if (!pci_resource_start(pdev, i)) {
 460                         *bar = 0; /* Unmapped by host = unimplemented to user */
 461                         continue;
 462                 }
 463 
 464                 mask = ~(pci_resource_len(pdev, i) - 1);
 465 
 466                 *bar &= cpu_to_le32((u32)mask);
 467                 *bar |= vfio_generate_bar_flags(pdev, i);
 468 
 469                 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 470                         bar++;
 471                         *bar &= cpu_to_le32((u32)(mask >> 32));
 472                         i++;
 473                 }
 474         }
 475 
 476         bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
 477 
 478         /*
 479          * NB. REGION_INFO will have reported zero size if we weren't able
 480          * to read the ROM, but we still return the actual BAR size here if
 481          * it exists (or the shadow ROM space).
 482          */
 483         if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
 484                 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
 485                 mask |= PCI_ROM_ADDRESS_ENABLE;
 486                 *bar &= cpu_to_le32((u32)mask);
 487         } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
 488                                         IORESOURCE_ROM_SHADOW) {
 489                 mask = ~(0x20000 - 1);
 490                 mask |= PCI_ROM_ADDRESS_ENABLE;
 491                 *bar &= cpu_to_le32((u32)mask);
 492         } else
 493                 *bar = 0;
 494 
 495         vdev->bardirty = false;
 496 }
 497 
 498 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
 499                                   int count, struct perm_bits *perm,
 500                                   int offset, __le32 *val)
 501 {
 502         if (is_bar(offset)) /* pos == offset for basic config */
 503                 vfio_bar_fixup(vdev);
 504 
 505         count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
 506 
 507         /* Mask in virtual memory enable for SR-IOV devices */
 508         if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
 509                 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
 510                 u32 tmp_val = le32_to_cpu(*val);
 511 
 512                 tmp_val |= cmd & PCI_COMMAND_MEMORY;
 513                 *val = cpu_to_le32(tmp_val);
 514         }
 515 
 516         return count;
 517 }
 518 
 519 /* Test whether BARs match the value we think they should contain */
 520 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
 521 {
 522         int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
 523         u32 bar;
 524 
 525         for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
 526                 if (vdev->rbar[i]) {
 527                         ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
 528                         if (ret || vdev->rbar[i] != bar)
 529                                 return true;
 530                 }
 531         }
 532 
 533         return false;
 534 }
 535 
 536 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
 537                                    int count, struct perm_bits *perm,
 538                                    int offset, __le32 val)
 539 {
 540         struct pci_dev *pdev = vdev->pdev;
 541         __le16 *virt_cmd;
 542         u16 new_cmd = 0;
 543         int ret;
 544 
 545         virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
 546 
 547         if (offset == PCI_COMMAND) {
 548                 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
 549                 u16 phys_cmd;
 550 
 551                 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
 552                 if (ret)
 553                         return ret;
 554 
 555                 new_cmd = le32_to_cpu(val);
 556 
 557                 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
 558                 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
 559                 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
 560 
 561                 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
 562                 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
 563                 new_io = !!(new_cmd & PCI_COMMAND_IO);
 564 
 565                 /*
 566                  * If the user is writing mem/io enable (new_mem/io) and we
 567                  * think it's already enabled (virt_mem/io), but the hardware
 568                  * shows it disabled (phys_mem/io, then the device has
 569                  * undergone some kind of backdoor reset and needs to be
 570                  * restored before we allow it to enable the bars.
 571                  * SR-IOV devices will trigger this, but we catch them later
 572                  */
 573                 if ((new_mem && virt_mem && !phys_mem) ||
 574                     (new_io && virt_io && !phys_io) ||
 575                     vfio_need_bar_restore(vdev))
 576                         vfio_bar_restore(vdev);
 577         }
 578 
 579         count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
 580         if (count < 0)
 581                 return count;
 582 
 583         /*
 584          * Save current memory/io enable bits in vconfig to allow for
 585          * the test above next time.
 586          */
 587         if (offset == PCI_COMMAND) {
 588                 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 589 
 590                 *virt_cmd &= cpu_to_le16(~mask);
 591                 *virt_cmd |= cpu_to_le16(new_cmd & mask);
 592         }
 593 
 594         /* Emulate INTx disable */
 595         if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
 596                 bool virt_intx_disable;
 597 
 598                 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
 599                                        PCI_COMMAND_INTX_DISABLE);
 600 
 601                 if (virt_intx_disable && !vdev->virq_disabled) {
 602                         vdev->virq_disabled = true;
 603                         vfio_pci_intx_mask(vdev);
 604                 } else if (!virt_intx_disable && vdev->virq_disabled) {
 605                         vdev->virq_disabled = false;
 606                         vfio_pci_intx_unmask(vdev);
 607                 }
 608         }
 609 
 610         if (is_bar(offset))
 611                 vdev->bardirty = true;
 612 
 613         return count;
 614 }
 615 
 616 /* Permissions for the Basic PCI Header */
 617 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
 618 {
 619         if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
 620                 return -ENOMEM;
 621 
 622         perm->readfn = vfio_basic_config_read;
 623         perm->writefn = vfio_basic_config_write;
 624 
 625         /* Virtualized for SR-IOV functions, which just have FFFF */
 626         p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
 627         p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
 628 
 629         /*
 630          * Virtualize INTx disable, we use it internally for interrupt
 631          * control and can emulate it for non-PCI 2.3 devices.
 632          */
 633         p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
 634 
 635         /* Virtualize capability list, we might want to skip/disable */
 636         p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
 637 
 638         /* No harm to write */
 639         p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
 640         p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
 641         p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
 642 
 643         /* Virtualize all bars, can't touch the real ones */
 644         p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
 645         p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
 646         p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
 647         p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
 648         p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
 649         p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
 650         p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
 651 
 652         /* Allow us to adjust capability chain */
 653         p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
 654 
 655         /* Sometimes used by sw, just virtualize */
 656         p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
 657 
 658         /* Virtualize interrupt pin to allow hiding INTx */
 659         p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
 660 
 661         return 0;
 662 }
 663 
 664 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
 665                                 int count, struct perm_bits *perm,
 666                                 int offset, __le32 val)
 667 {
 668         count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
 669         if (count < 0)
 670                 return count;
 671 
 672         if (offset == PCI_PM_CTRL) {
 673                 pci_power_t state;
 674 
 675                 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
 676                 case 0:
 677                         state = PCI_D0;
 678                         break;
 679                 case 1:
 680                         state = PCI_D1;
 681                         break;
 682                 case 2:
 683                         state = PCI_D2;
 684                         break;
 685                 case 3:
 686                         state = PCI_D3hot;
 687                         break;
 688                 }
 689 
 690                 vfio_pci_set_power_state(vdev, state);
 691         }
 692 
 693         return count;
 694 }
 695 
 696 /* Permissions for the Power Management capability */
 697 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
 698 {
 699         if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
 700                 return -ENOMEM;
 701 
 702         perm->writefn = vfio_pm_config_write;
 703 
 704         /*
 705          * We always virtualize the next field so we can remove
 706          * capabilities from the chain if we want to.
 707          */
 708         p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
 709 
 710         /*
 711          * Power management is defined *per function*, so we can let
 712          * the user change power state, but we trap and initiate the
 713          * change ourselves, so the state bits are read-only.
 714          */
 715         p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
 716         return 0;
 717 }
 718 
 719 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
 720                                  int count, struct perm_bits *perm,
 721                                  int offset, __le32 val)
 722 {
 723         struct pci_dev *pdev = vdev->pdev;
 724         __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
 725         __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
 726         u16 addr;
 727         u32 data;
 728 
 729         /*
 730          * Write through to emulation.  If the write includes the upper byte
 731          * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
 732          * have work to do.
 733          */
 734         count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
 735         if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
 736             offset + count <= PCI_VPD_ADDR + 1)
 737                 return count;
 738 
 739         addr = le16_to_cpu(*paddr);
 740 
 741         if (addr & PCI_VPD_ADDR_F) {
 742                 data = le32_to_cpu(*pdata);
 743                 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
 744                         return count;
 745         } else {
 746                 data = 0;
 747                 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
 748                         return count;
 749                 *pdata = cpu_to_le32(data);
 750         }
 751 
 752         /*
 753          * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
 754          * signal completion.  If an error occurs above, we assume that not
 755          * toggling this bit will induce a driver timeout.
 756          */
 757         addr ^= PCI_VPD_ADDR_F;
 758         *paddr = cpu_to_le16(addr);
 759 
 760         return count;
 761 }
 762 
 763 /* Permissions for Vital Product Data capability */
 764 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
 765 {
 766         if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
 767                 return -ENOMEM;
 768 
 769         perm->writefn = vfio_vpd_config_write;
 770 
 771         /*
 772          * We always virtualize the next field so we can remove
 773          * capabilities from the chain if we want to.
 774          */
 775         p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
 776 
 777         /*
 778          * Both the address and data registers are virtualized to
 779          * enable access through the pci_vpd_read/write functions
 780          */
 781         p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
 782         p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
 783 
 784         return 0;
 785 }
 786 
 787 /* Permissions for PCI-X capability */
 788 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
 789 {
 790         /* Alloc 24, but only 8 are used in v0 */
 791         if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
 792                 return -ENOMEM;
 793 
 794         p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
 795 
 796         p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
 797         p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
 798         return 0;
 799 }
 800 
 801 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
 802                                  int count, struct perm_bits *perm,
 803                                  int offset, __le32 val)
 804 {
 805         __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
 806                                   offset + PCI_EXP_DEVCTL);
 807         int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
 808 
 809         count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
 810         if (count < 0)
 811                 return count;
 812 
 813         /*
 814          * The FLR bit is virtualized, if set and the device supports PCIe
 815          * FLR, issue a reset_function.  Regardless, clear the bit, the spec
 816          * requires it to be always read as zero.  NB, reset_function might
 817          * not use a PCIe FLR, we don't have that level of granularity.
 818          */
 819         if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
 820                 u32 cap;
 821                 int ret;
 822 
 823                 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
 824 
 825                 ret = pci_user_read_config_dword(vdev->pdev,
 826                                                  pos - offset + PCI_EXP_DEVCAP,
 827                                                  &cap);
 828 
 829                 if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
 830                         pci_try_reset_function(vdev->pdev);
 831         }
 832 
 833         /*
 834          * MPS is virtualized to the user, writes do not change the physical
 835          * register since determining a proper MPS value requires a system wide
 836          * device view.  The MRRS is largely independent of MPS, but since the
 837          * user does not have that system-wide view, they might set a safe, but
 838          * inefficiently low value.  Here we allow writes through to hardware,
 839          * but we set the floor to the physical device MPS setting, so that
 840          * we can at least use full TLPs, as defined by the MPS value.
 841          *
 842          * NB, if any devices actually depend on an artificially low MRRS
 843          * setting, this will need to be revisited, perhaps with a quirk
 844          * though pcie_set_readrq().
 845          */
 846         if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
 847                 readrq = 128 <<
 848                         ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
 849                 readrq = max(readrq, pcie_get_mps(vdev->pdev));
 850 
 851                 pcie_set_readrq(vdev->pdev, readrq);
 852         }
 853 
 854         return count;
 855 }
 856 
 857 /* Permissions for PCI Express capability */
 858 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
 859 {
 860         /* Alloc largest of possible sizes */
 861         if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
 862                 return -ENOMEM;
 863 
 864         perm->writefn = vfio_exp_config_write;
 865 
 866         p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
 867 
 868         /*
 869          * Allow writes to device control fields, except devctl_phantom,
 870          * which could confuse IOMMU, MPS, which can break communication
 871          * with other physical devices, and the ARI bit in devctl2, which
 872          * is set at probe time.  FLR and MRRS get virtualized via our
 873          * writefn.
 874          */
 875         p_setw(perm, PCI_EXP_DEVCTL,
 876                PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
 877                PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
 878         p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
 879         return 0;
 880 }
 881 
 882 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
 883                                 int count, struct perm_bits *perm,
 884                                 int offset, __le32 val)
 885 {
 886         u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
 887 
 888         count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
 889         if (count < 0)
 890                 return count;
 891 
 892         /*
 893          * The FLR bit is virtualized, if set and the device supports AF
 894          * FLR, issue a reset_function.  Regardless, clear the bit, the spec
 895          * requires it to be always read as zero.  NB, reset_function might
 896          * not use an AF FLR, we don't have that level of granularity.
 897          */
 898         if (*ctrl & PCI_AF_CTRL_FLR) {
 899                 u8 cap;
 900                 int ret;
 901 
 902                 *ctrl &= ~PCI_AF_CTRL_FLR;
 903 
 904                 ret = pci_user_read_config_byte(vdev->pdev,
 905                                                 pos - offset + PCI_AF_CAP,
 906                                                 &cap);
 907 
 908                 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
 909                         pci_try_reset_function(vdev->pdev);
 910         }
 911 
 912         return count;
 913 }
 914 
 915 /* Permissions for Advanced Function capability */
 916 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
 917 {
 918         if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
 919                 return -ENOMEM;
 920 
 921         perm->writefn = vfio_af_config_write;
 922 
 923         p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
 924         p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
 925         return 0;
 926 }
 927 
 928 /* Permissions for Advanced Error Reporting extended capability */
 929 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
 930 {
 931         u32 mask;
 932 
 933         if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
 934                 return -ENOMEM;
 935 
 936         /*
 937          * Virtualize the first dword of all express capabilities
 938          * because it includes the next pointer.  This lets us later
 939          * remove capabilities from the chain if we need to.
 940          */
 941         p_setd(perm, 0, ALL_VIRT, NO_WRITE);
 942 
 943         /* Writable bits mask */
 944         mask =  PCI_ERR_UNC_UND |               /* Undefined */
 945                 PCI_ERR_UNC_DLP |               /* Data Link Protocol */
 946                 PCI_ERR_UNC_SURPDN |            /* Surprise Down */
 947                 PCI_ERR_UNC_POISON_TLP |        /* Poisoned TLP */
 948                 PCI_ERR_UNC_FCP |               /* Flow Control Protocol */
 949                 PCI_ERR_UNC_COMP_TIME |         /* Completion Timeout */
 950                 PCI_ERR_UNC_COMP_ABORT |        /* Completer Abort */
 951                 PCI_ERR_UNC_UNX_COMP |          /* Unexpected Completion */
 952                 PCI_ERR_UNC_RX_OVER |           /* Receiver Overflow */
 953                 PCI_ERR_UNC_MALF_TLP |          /* Malformed TLP */
 954                 PCI_ERR_UNC_ECRC |              /* ECRC Error Status */
 955                 PCI_ERR_UNC_UNSUP |             /* Unsupported Request */
 956                 PCI_ERR_UNC_ACSV |              /* ACS Violation */
 957                 PCI_ERR_UNC_INTN |              /* internal error */
 958                 PCI_ERR_UNC_MCBTLP |            /* MC blocked TLP */
 959                 PCI_ERR_UNC_ATOMEG |            /* Atomic egress blocked */
 960                 PCI_ERR_UNC_TLPPRE;             /* TLP prefix blocked */
 961         p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
 962         p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
 963         p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
 964 
 965         mask =  PCI_ERR_COR_RCVR |              /* Receiver Error Status */
 966                 PCI_ERR_COR_BAD_TLP |           /* Bad TLP Status */
 967                 PCI_ERR_COR_BAD_DLLP |          /* Bad DLLP Status */
 968                 PCI_ERR_COR_REP_ROLL |          /* REPLAY_NUM Rollover */
 969                 PCI_ERR_COR_REP_TIMER |         /* Replay Timer Timeout */
 970                 PCI_ERR_COR_ADV_NFAT |          /* Advisory Non-Fatal */
 971                 PCI_ERR_COR_INTERNAL |          /* Corrected Internal */
 972                 PCI_ERR_COR_LOG_OVER;           /* Header Log Overflow */
 973         p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
 974         p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
 975 
 976         mask =  PCI_ERR_CAP_ECRC_GENE |         /* ECRC Generation Enable */
 977                 PCI_ERR_CAP_ECRC_CHKE;          /* ECRC Check Enable */
 978         p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
 979         return 0;
 980 }
 981 
 982 /* Permissions for Power Budgeting extended capability */
 983 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
 984 {
 985         if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
 986                 return -ENOMEM;
 987 
 988         p_setd(perm, 0, ALL_VIRT, NO_WRITE);
 989 
 990         /* Writing the data selector is OK, the info is still read-only */
 991         p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
 992         return 0;
 993 }
 994 
 995 /*
 996  * Initialize the shared permission tables
 997  */
 998 void vfio_pci_uninit_perm_bits(void)
 999 {
1000         free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
1001 
1002         free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
1003         free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
1004         free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
1005         free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
1006         free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
1007 
1008         free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1009         free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1010 }
1011 
1012 int __init vfio_pci_init_perm_bits(void)
1013 {
1014         int ret;
1015 
1016         /* Basic config space */
1017         ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
1018 
1019         /* Capabilities */
1020         ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1021         ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1022         ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1023         cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1024         ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1025         ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1026 
1027         /* Extended capabilities */
1028         ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1029         ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1030         ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1031 
1032         if (ret)
1033                 vfio_pci_uninit_perm_bits();
1034 
1035         return ret;
1036 }
1037 
1038 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
1039 {
1040         u8 cap;
1041         int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1042                                                  PCI_STD_HEADER_SIZEOF;
1043         cap = vdev->pci_config_map[pos];
1044 
1045         if (cap == PCI_CAP_ID_BASIC)
1046                 return 0;
1047 
1048         /* XXX Can we have to abutting capabilities of the same type? */
1049         while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1050                 pos--;
1051 
1052         return pos;
1053 }
1054 
1055 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1056                                 int count, struct perm_bits *perm,
1057                                 int offset, __le32 *val)
1058 {
1059         /* Update max available queue size from msi_qmax */
1060         if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1061                 __le16 *flags;
1062                 int start;
1063 
1064                 start = vfio_find_cap_start(vdev, pos);
1065 
1066                 flags = (__le16 *)&vdev->vconfig[start];
1067 
1068                 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1069                 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1070         }
1071 
1072         return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1073 }
1074 
1075 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1076                                  int count, struct perm_bits *perm,
1077                                  int offset, __le32 val)
1078 {
1079         count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1080         if (count < 0)
1081                 return count;
1082 
1083         /* Fixup and write configured queue size and enable to hardware */
1084         if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1085                 __le16 *pflags;
1086                 u16 flags;
1087                 int start, ret;
1088 
1089                 start = vfio_find_cap_start(vdev, pos);
1090 
1091                 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1092 
1093                 flags = le16_to_cpu(*pflags);
1094 
1095                 /* MSI is enabled via ioctl */
1096                 if  (!is_msi(vdev))
1097                         flags &= ~PCI_MSI_FLAGS_ENABLE;
1098 
1099                 /* Check queue size */
1100                 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1101                         flags &= ~PCI_MSI_FLAGS_QSIZE;
1102                         flags |= vdev->msi_qmax << 4;
1103                 }
1104 
1105                 /* Write back to virt and to hardware */
1106                 *pflags = cpu_to_le16(flags);
1107                 ret = pci_user_write_config_word(vdev->pdev,
1108                                                  start + PCI_MSI_FLAGS,
1109                                                  flags);
1110                 if (ret)
1111                         return ret;
1112         }
1113 
1114         return count;
1115 }
1116 
1117 /*
1118  * MSI determination is per-device, so this routine gets used beyond
1119  * initialization time. Don't add __init
1120  */
1121 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1122 {
1123         if (alloc_perm_bits(perm, len))
1124                 return -ENOMEM;
1125 
1126         perm->readfn = vfio_msi_config_read;
1127         perm->writefn = vfio_msi_config_write;
1128 
1129         p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1130 
1131         /*
1132          * The upper byte of the control register is reserved,
1133          * just setup the lower byte.
1134          */
1135         p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1136         p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1137         if (flags & PCI_MSI_FLAGS_64BIT) {
1138                 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1139                 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1140                 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1141                         p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1142                         p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1143                 }
1144         } else {
1145                 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1146                 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1147                         p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1148                         p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1149                 }
1150         }
1151         return 0;
1152 }
1153 
1154 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1155 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1156 {
1157         struct pci_dev *pdev = vdev->pdev;
1158         int len, ret;
1159         u16 flags;
1160 
1161         ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1162         if (ret)
1163                 return pcibios_err_to_errno(ret);
1164 
1165         len = 10; /* Minimum size */
1166         if (flags & PCI_MSI_FLAGS_64BIT)
1167                 len += 4;
1168         if (flags & PCI_MSI_FLAGS_MASKBIT)
1169                 len += 10;
1170 
1171         if (vdev->msi_perm)
1172                 return len;
1173 
1174         vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1175         if (!vdev->msi_perm)
1176                 return -ENOMEM;
1177 
1178         ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1179         if (ret) {
1180                 kfree(vdev->msi_perm);
1181                 return ret;
1182         }
1183 
1184         return len;
1185 }
1186 
1187 /* Determine extended capability length for VC (2 & 9) and MFVC */
1188 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1189 {
1190         struct pci_dev *pdev = vdev->pdev;
1191         u32 tmp;
1192         int ret, evcc, phases, vc_arb;
1193         int len = PCI_CAP_VC_BASE_SIZEOF;
1194 
1195         ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1196         if (ret)
1197                 return pcibios_err_to_errno(ret);
1198 
1199         evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1200         ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1201         if (ret)
1202                 return pcibios_err_to_errno(ret);
1203 
1204         if (tmp & PCI_VC_CAP2_128_PHASE)
1205                 phases = 128;
1206         else if (tmp & PCI_VC_CAP2_64_PHASE)
1207                 phases = 64;
1208         else if (tmp & PCI_VC_CAP2_32_PHASE)
1209                 phases = 32;
1210         else
1211                 phases = 0;
1212 
1213         vc_arb = phases * 4;
1214 
1215         /*
1216          * Port arbitration tables are root & switch only;
1217          * function arbitration tables are function 0 only.
1218          * In either case, we'll never let user write them so
1219          * we don't care how big they are
1220          */
1221         len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1222         if (vc_arb) {
1223                 len = round_up(len, 16);
1224                 len += vc_arb / 8;
1225         }
1226         return len;
1227 }
1228 
1229 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1230 {
1231         struct pci_dev *pdev = vdev->pdev;
1232         u32 dword;
1233         u16 word;
1234         u8 byte;
1235         int ret;
1236 
1237         switch (cap) {
1238         case PCI_CAP_ID_MSI:
1239                 return vfio_msi_cap_len(vdev, pos);
1240         case PCI_CAP_ID_PCIX:
1241                 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1242                 if (ret)
1243                         return pcibios_err_to_errno(ret);
1244 
1245                 if (PCI_X_CMD_VERSION(word)) {
1246                         if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1247                                 /* Test for extended capabilities */
1248                                 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1249                                                       &dword);
1250                                 vdev->extended_caps = (dword != 0);
1251                         }
1252                         return PCI_CAP_PCIX_SIZEOF_V2;
1253                 } else
1254                         return PCI_CAP_PCIX_SIZEOF_V0;
1255         case PCI_CAP_ID_VNDR:
1256                 /* length follows next field */
1257                 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1258                 if (ret)
1259                         return pcibios_err_to_errno(ret);
1260 
1261                 return byte;
1262         case PCI_CAP_ID_EXP:
1263                 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1264                         /* Test for extended capabilities */
1265                         pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1266                         vdev->extended_caps = (dword != 0);
1267                 }
1268 
1269                 /* length based on version and type */
1270                 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
1271                         if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1272                                 return 0xc; /* "All Devices" only, no link */
1273                         return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1274                 } else {
1275                         if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1276                                 return 0x2c; /* No link */
1277                         return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1278                 }
1279         case PCI_CAP_ID_HT:
1280                 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1281                 if (ret)
1282                         return pcibios_err_to_errno(ret);
1283 
1284                 return (byte & HT_3BIT_CAP_MASK) ?
1285                         HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1286         case PCI_CAP_ID_SATA:
1287                 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1288                 if (ret)
1289                         return pcibios_err_to_errno(ret);
1290 
1291                 byte &= PCI_SATA_REGS_MASK;
1292                 if (byte == PCI_SATA_REGS_INLINE)
1293                         return PCI_SATA_SIZEOF_LONG;
1294                 else
1295                         return PCI_SATA_SIZEOF_SHORT;
1296         default:
1297                 pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n",
1298                          __func__, cap, pos);
1299         }
1300 
1301         return 0;
1302 }
1303 
1304 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1305 {
1306         struct pci_dev *pdev = vdev->pdev;
1307         u8 byte;
1308         u32 dword;
1309         int ret;
1310 
1311         switch (ecap) {
1312         case PCI_EXT_CAP_ID_VNDR:
1313                 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1314                 if (ret)
1315                         return pcibios_err_to_errno(ret);
1316 
1317                 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1318         case PCI_EXT_CAP_ID_VC:
1319         case PCI_EXT_CAP_ID_VC9:
1320         case PCI_EXT_CAP_ID_MFVC:
1321                 return vfio_vc_cap_len(vdev, epos);
1322         case PCI_EXT_CAP_ID_ACS:
1323                 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1324                 if (ret)
1325                         return pcibios_err_to_errno(ret);
1326 
1327                 if (byte & PCI_ACS_EC) {
1328                         int bits;
1329 
1330                         ret = pci_read_config_byte(pdev,
1331                                                    epos + PCI_ACS_EGRESS_BITS,
1332                                                    &byte);
1333                         if (ret)
1334                                 return pcibios_err_to_errno(ret);
1335 
1336                         bits = byte ? round_up(byte, 32) : 256;
1337                         return 8 + (bits / 8);
1338                 }
1339                 return 8;
1340 
1341         case PCI_EXT_CAP_ID_REBAR:
1342                 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1343                 if (ret)
1344                         return pcibios_err_to_errno(ret);
1345 
1346                 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1347                 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1348 
1349                 return 4 + (byte * 8);
1350         case PCI_EXT_CAP_ID_DPA:
1351                 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1352                 if (ret)
1353                         return pcibios_err_to_errno(ret);
1354 
1355                 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1356                 return PCI_DPA_BASE_SIZEOF + byte + 1;
1357         case PCI_EXT_CAP_ID_TPH:
1358                 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1359                 if (ret)
1360                         return pcibios_err_to_errno(ret);
1361 
1362                 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1363                         int sts;
1364 
1365                         sts = dword & PCI_TPH_CAP_ST_MASK;
1366                         sts >>= PCI_TPH_CAP_ST_SHIFT;
1367                         return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1368                 }
1369                 return PCI_TPH_BASE_SIZEOF;
1370         default:
1371                 pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n",
1372                          __func__, ecap, epos);
1373         }
1374 
1375         return 0;
1376 }
1377 
1378 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1379                                    int offset, int size)
1380 {
1381         struct pci_dev *pdev = vdev->pdev;
1382         int ret = 0;
1383 
1384         /*
1385          * We try to read physical config space in the largest chunks
1386          * we can, assuming that all of the fields support dword access.
1387          * pci_save_state() makes this same assumption and seems to do ok.
1388          */
1389         while (size) {
1390                 int filled;
1391 
1392                 if (size >= 4 && !(offset % 4)) {
1393                         __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1394                         u32 dword;
1395 
1396                         ret = pci_read_config_dword(pdev, offset, &dword);
1397                         if (ret)
1398                                 return ret;
1399                         *dwordp = cpu_to_le32(dword);
1400                         filled = 4;
1401                 } else if (size >= 2 && !(offset % 2)) {
1402                         __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1403                         u16 word;
1404 
1405                         ret = pci_read_config_word(pdev, offset, &word);
1406                         if (ret)
1407                                 return ret;
1408                         *wordp = cpu_to_le16(word);
1409                         filled = 2;
1410                 } else {
1411                         u8 *byte = &vdev->vconfig[offset];
1412                         ret = pci_read_config_byte(pdev, offset, byte);
1413                         if (ret)
1414                                 return ret;
1415                         filled = 1;
1416                 }
1417 
1418                 offset += filled;
1419                 size -= filled;
1420         }
1421 
1422         return ret;
1423 }
1424 
1425 static int vfio_cap_init(struct vfio_pci_device *vdev)
1426 {
1427         struct pci_dev *pdev = vdev->pdev;
1428         u8 *map = vdev->pci_config_map;
1429         u16 status;
1430         u8 pos, *prev, cap;
1431         int loops, ret, caps = 0;
1432 
1433         /* Any capabilities? */
1434         ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1435         if (ret)
1436                 return ret;
1437 
1438         if (!(status & PCI_STATUS_CAP_LIST))
1439                 return 0; /* Done */
1440 
1441         ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1442         if (ret)
1443                 return ret;
1444 
1445         /* Mark the previous position in case we want to skip a capability */
1446         prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1447 
1448         /* We can bound our loop, capabilities are dword aligned */
1449         loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1450         while (pos && loops--) {
1451                 u8 next;
1452                 int i, len = 0;
1453 
1454                 ret = pci_read_config_byte(pdev, pos, &cap);
1455                 if (ret)
1456                         return ret;
1457 
1458                 ret = pci_read_config_byte(pdev,
1459                                            pos + PCI_CAP_LIST_NEXT, &next);
1460                 if (ret)
1461                         return ret;
1462 
1463                 if (cap <= PCI_CAP_ID_MAX) {
1464                         len = pci_cap_length[cap];
1465                         if (len == 0xFF) { /* Variable length */
1466                                 len = vfio_cap_len(vdev, cap, pos);
1467                                 if (len < 0)
1468                                         return len;
1469                         }
1470                 }
1471 
1472                 if (!len) {
1473                         pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__,
1474                                  cap, pos);
1475                         *prev = next;
1476                         pos = next;
1477                         continue;
1478                 }
1479 
1480                 /* Sanity check, do we overlap other capabilities? */
1481                 for (i = 0; i < len; i++) {
1482                         if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1483                                 continue;
1484 
1485                         pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n",
1486                                  __func__, pos + i, map[pos + i], cap);
1487                 }
1488 
1489                 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1490 
1491                 memset(map + pos, cap, len);
1492                 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1493                 if (ret)
1494                         return ret;
1495 
1496                 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1497                 pos = next;
1498                 caps++;
1499         }
1500 
1501         /* If we didn't fill any capabilities, clear the status flag */
1502         if (!caps) {
1503                 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1504                 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1505         }
1506 
1507         return 0;
1508 }
1509 
1510 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1511 {
1512         struct pci_dev *pdev = vdev->pdev;
1513         u8 *map = vdev->pci_config_map;
1514         u16 epos;
1515         __le32 *prev = NULL;
1516         int loops, ret, ecaps = 0;
1517 
1518         if (!vdev->extended_caps)
1519                 return 0;
1520 
1521         epos = PCI_CFG_SPACE_SIZE;
1522 
1523         loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1524 
1525         while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1526                 u32 header;
1527                 u16 ecap;
1528                 int i, len = 0;
1529                 bool hidden = false;
1530 
1531                 ret = pci_read_config_dword(pdev, epos, &header);
1532                 if (ret)
1533                         return ret;
1534 
1535                 ecap = PCI_EXT_CAP_ID(header);
1536 
1537                 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1538                         len = pci_ext_cap_length[ecap];
1539                         if (len == 0xFF) {
1540                                 len = vfio_ext_cap_len(vdev, ecap, epos);
1541                                 if (len < 0)
1542                                         return ret;
1543                         }
1544                 }
1545 
1546                 if (!len) {
1547                         pci_info(pdev, "%s: hiding ecap %#x@%#x\n",
1548                                  __func__, ecap, epos);
1549 
1550                         /* If not the first in the chain, we can skip over it */
1551                         if (prev) {
1552                                 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1553                                 *prev &= cpu_to_le32(~(0xffcU << 20));
1554                                 *prev |= cpu_to_le32(val << 20);
1555                                 continue;
1556                         }
1557 
1558                         /*
1559                          * Otherwise, fill in a placeholder, the direct
1560                          * readfn will virtualize this automatically
1561                          */
1562                         len = PCI_CAP_SIZEOF;
1563                         hidden = true;
1564                 }
1565 
1566                 for (i = 0; i < len; i++) {
1567                         if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1568                                 continue;
1569 
1570                         pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n",
1571                                  __func__, epos + i, map[epos + i], ecap);
1572                 }
1573 
1574                 /*
1575                  * Even though ecap is 2 bytes, we're currently a long way
1576                  * from exceeding 1 byte capabilities.  If we ever make it
1577                  * up to 0xFE we'll need to up this to a two-byte, byte map.
1578                  */
1579                 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1580 
1581                 memset(map + epos, ecap, len);
1582                 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1583                 if (ret)
1584                         return ret;
1585 
1586                 /*
1587                  * If we're just using this capability to anchor the list,
1588                  * hide the real ID.  Only count real ecaps.  XXX PCI spec
1589                  * indicates to use cap id = 0, version = 0, next = 0 if
1590                  * ecaps are absent, hope users check all the way to next.
1591                  */
1592                 if (hidden)
1593                         *(__le32 *)&vdev->vconfig[epos] &=
1594                                 cpu_to_le32((0xffcU << 20));
1595                 else
1596                         ecaps++;
1597 
1598                 prev = (__le32 *)&vdev->vconfig[epos];
1599                 epos = PCI_EXT_CAP_NEXT(header);
1600         }
1601 
1602         if (!ecaps)
1603                 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1604 
1605         return 0;
1606 }
1607 
1608 /*
1609  * Nag about hardware bugs, hopefully to have vendors fix them, but at least
1610  * to collect a list of dependencies for the VF INTx pin quirk below.
1611  */
1612 static const struct pci_device_id known_bogus_vf_intx_pin[] = {
1613         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
1614         {}
1615 };
1616 
1617 /*
1618  * For each device we allocate a pci_config_map that indicates the
1619  * capability occupying each dword and thus the struct perm_bits we
1620  * use for read and write.  We also allocate a virtualized config
1621  * space which tracks reads and writes to bits that we emulate for
1622  * the user.  Initial values filled from device.
1623  *
1624  * Using shared struct perm_bits between all vfio-pci devices saves
1625  * us from allocating cfg_size buffers for virt and write for every
1626  * device.  We could remove vconfig and allocate individual buffers
1627  * for each area requiring emulated bits, but the array of pointers
1628  * would be comparable in size (at least for standard config space).
1629  */
1630 int vfio_config_init(struct vfio_pci_device *vdev)
1631 {
1632         struct pci_dev *pdev = vdev->pdev;
1633         u8 *map, *vconfig;
1634         int ret;
1635 
1636         /*
1637          * Config space, caps and ecaps are all dword aligned, so we could
1638          * use one byte per dword to record the type.  However, there are
1639          * no requiremenst on the length of a capability, so the gap between
1640          * capabilities needs byte granularity.
1641          */
1642         map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1643         if (!map)
1644                 return -ENOMEM;
1645 
1646         vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1647         if (!vconfig) {
1648                 kfree(map);
1649                 return -ENOMEM;
1650         }
1651 
1652         vdev->pci_config_map = map;
1653         vdev->vconfig = vconfig;
1654 
1655         memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1656         memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1657                pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1658 
1659         ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1660         if (ret)
1661                 goto out;
1662 
1663         vdev->bardirty = true;
1664 
1665         /*
1666          * XXX can we just pci_load_saved_state/pci_restore_state?
1667          * may need to rebuild vconfig after that
1668          */
1669 
1670         /* For restore after reset */
1671         vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1672         vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1673         vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1674         vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1675         vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1676         vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1677         vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1678 
1679         if (pdev->is_virtfn) {
1680                 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1681                 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1682 
1683                 /*
1684                  * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
1685                  * does not apply to VFs and VFs must implement this register
1686                  * as read-only with value zero.  Userspace is not readily able
1687                  * to identify whether a device is a VF and thus that the pin
1688                  * definition on the device is bogus should it violate this
1689                  * requirement.  We already virtualize the pin register for
1690                  * other purposes, so we simply need to replace the bogus value
1691                  * and consider VFs when we determine INTx IRQ count.
1692                  */
1693                 if (vconfig[PCI_INTERRUPT_PIN] &&
1694                     !pci_match_id(known_bogus_vf_intx_pin, pdev))
1695                         pci_warn(pdev,
1696                                  "Hardware bug: VF reports bogus INTx pin %d\n",
1697                                  vconfig[PCI_INTERRUPT_PIN]);
1698 
1699                 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
1700         }
1701 
1702         if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1703                 vconfig[PCI_INTERRUPT_PIN] = 0;
1704 
1705         ret = vfio_cap_init(vdev);
1706         if (ret)
1707                 goto out;
1708 
1709         ret = vfio_ecap_init(vdev);
1710         if (ret)
1711                 goto out;
1712 
1713         return 0;
1714 
1715 out:
1716         kfree(map);
1717         vdev->pci_config_map = NULL;
1718         kfree(vconfig);
1719         vdev->vconfig = NULL;
1720         return pcibios_err_to_errno(ret);
1721 }
1722 
1723 void vfio_config_free(struct vfio_pci_device *vdev)
1724 {
1725         kfree(vdev->vconfig);
1726         vdev->vconfig = NULL;
1727         kfree(vdev->pci_config_map);
1728         vdev->pci_config_map = NULL;
1729         kfree(vdev->msi_perm);
1730         vdev->msi_perm = NULL;
1731 }
1732 
1733 /*
1734  * Find the remaining number of bytes in a dword that match the given
1735  * position.  Stop at either the end of the capability or the dword boundary.
1736  */
1737 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1738                                            loff_t pos)
1739 {
1740         u8 cap = vdev->pci_config_map[pos];
1741         size_t i;
1742 
1743         for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1744                 /* nop */;
1745 
1746         return i;
1747 }
1748 
1749 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1750                                  size_t count, loff_t *ppos, bool iswrite)
1751 {
1752         struct pci_dev *pdev = vdev->pdev;
1753         struct perm_bits *perm;
1754         __le32 val = 0;
1755         int cap_start = 0, offset;
1756         u8 cap_id;
1757         ssize_t ret;
1758 
1759         if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1760             *ppos + count > pdev->cfg_size)
1761                 return -EFAULT;
1762 
1763         /*
1764          * Chop accesses into aligned chunks containing no more than a
1765          * single capability.  Caller increments to the next chunk.
1766          */
1767         count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1768         if (count >= 4 && !(*ppos % 4))
1769                 count = 4;
1770         else if (count >= 2 && !(*ppos % 2))
1771                 count = 2;
1772         else
1773                 count = 1;
1774 
1775         ret = count;
1776 
1777         cap_id = vdev->pci_config_map[*ppos];
1778 
1779         if (cap_id == PCI_CAP_ID_INVALID) {
1780                 perm = &unassigned_perms;
1781                 cap_start = *ppos;
1782         } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1783                 perm = &virt_perms;
1784                 cap_start = *ppos;
1785         } else {
1786                 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1787                         WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1788 
1789                         perm = &ecap_perms[cap_id];
1790                         cap_start = vfio_find_cap_start(vdev, *ppos);
1791                 } else {
1792                         WARN_ON(cap_id > PCI_CAP_ID_MAX);
1793 
1794                         perm = &cap_perms[cap_id];
1795 
1796                         if (cap_id == PCI_CAP_ID_MSI)
1797                                 perm = vdev->msi_perm;
1798 
1799                         if (cap_id > PCI_CAP_ID_BASIC)
1800                                 cap_start = vfio_find_cap_start(vdev, *ppos);
1801                 }
1802         }
1803 
1804         WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1805         WARN_ON(cap_start > *ppos);
1806 
1807         offset = *ppos - cap_start;
1808 
1809         if (iswrite) {
1810                 if (!perm->writefn)
1811                         return ret;
1812 
1813                 if (copy_from_user(&val, buf, count))
1814                         return -EFAULT;
1815 
1816                 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1817         } else {
1818                 if (perm->readfn) {
1819                         ret = perm->readfn(vdev, *ppos, count,
1820                                            perm, offset, &val);
1821                         if (ret < 0)
1822                                 return ret;
1823                 }
1824 
1825                 if (copy_to_user(buf, &val, count))
1826                         return -EFAULT;
1827         }
1828 
1829         return ret;
1830 }
1831 
1832 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1833                            size_t count, loff_t *ppos, bool iswrite)
1834 {
1835         size_t done = 0;
1836         int ret = 0;
1837         loff_t pos = *ppos;
1838 
1839         pos &= VFIO_PCI_OFFSET_MASK;
1840 
1841         while (count) {
1842                 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
1843                 if (ret < 0)
1844                         return ret;
1845 
1846                 count -= ret;
1847                 done += ret;
1848                 buf += ret;
1849                 pos += ret;
1850         }
1851 
1852         *ppos += done;
1853 
1854         return done;
1855 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/vfio/pci/vfio_pci_config.c

DEFINITIONS
