This source file includes following definitions.
- g12a_cpu_clk_mux_notifier_cb
- g12a_cpu_clk_postmux_notifier_cb
- g12a_sys_pll_notifier_cb
- meson_g12a_dvfs_setup_common
- meson_g12b_dvfs_setup
- meson_g12a_dvfs_setup
- meson_g12a_probe
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13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18
19 #include "clk-mpll.h"
20 #include "clk-pll.h"
21 #include "clk-regmap.h"
22 #include "clk-cpu-dyndiv.h"
23 #include "vid-pll-div.h"
24 #include "meson-eeclk.h"
25 #include "g12a.h"
26
27 static DEFINE_SPINLOCK(meson_clk_lock);
28
29 static struct clk_regmap g12a_fixed_pll_dco = {
30 .data = &(struct meson_clk_pll_data){
31 .en = {
32 .reg_off = HHI_FIX_PLL_CNTL0,
33 .shift = 28,
34 .width = 1,
35 },
36 .m = {
37 .reg_off = HHI_FIX_PLL_CNTL0,
38 .shift = 0,
39 .width = 8,
40 },
41 .n = {
42 .reg_off = HHI_FIX_PLL_CNTL0,
43 .shift = 10,
44 .width = 5,
45 },
46 .frac = {
47 .reg_off = HHI_FIX_PLL_CNTL1,
48 .shift = 0,
49 .width = 17,
50 },
51 .l = {
52 .reg_off = HHI_FIX_PLL_CNTL0,
53 .shift = 31,
54 .width = 1,
55 },
56 .rst = {
57 .reg_off = HHI_FIX_PLL_CNTL0,
58 .shift = 29,
59 .width = 1,
60 },
61 },
62 .hw.init = &(struct clk_init_data){
63 .name = "fixed_pll_dco",
64 .ops = &meson_clk_pll_ro_ops,
65 .parent_data = &(const struct clk_parent_data) {
66 .fw_name = "xtal",
67 },
68 .num_parents = 1,
69 },
70 };
71
72 static struct clk_regmap g12a_fixed_pll = {
73 .data = &(struct clk_regmap_div_data){
74 .offset = HHI_FIX_PLL_CNTL0,
75 .shift = 16,
76 .width = 2,
77 .flags = CLK_DIVIDER_POWER_OF_TWO,
78 },
79 .hw.init = &(struct clk_init_data){
80 .name = "fixed_pll",
81 .ops = &clk_regmap_divider_ro_ops,
82 .parent_hws = (const struct clk_hw *[]) {
83 &g12a_fixed_pll_dco.hw
84 },
85 .num_parents = 1,
86
87
88
89
90 },
91 };
92
93 static const struct pll_mult_range g12a_sys_pll_mult_range = {
94 .min = 128,
95 .max = 250,
96 };
97
98 static struct clk_regmap g12a_sys_pll_dco = {
99 .data = &(struct meson_clk_pll_data){
100 .en = {
101 .reg_off = HHI_SYS_PLL_CNTL0,
102 .shift = 28,
103 .width = 1,
104 },
105 .m = {
106 .reg_off = HHI_SYS_PLL_CNTL0,
107 .shift = 0,
108 .width = 8,
109 },
110 .n = {
111 .reg_off = HHI_SYS_PLL_CNTL0,
112 .shift = 10,
113 .width = 5,
114 },
115 .l = {
116 .reg_off = HHI_SYS_PLL_CNTL0,
117 .shift = 31,
118 .width = 1,
119 },
120 .rst = {
121 .reg_off = HHI_SYS_PLL_CNTL0,
122 .shift = 29,
123 .width = 1,
124 },
125 .range = &g12a_sys_pll_mult_range,
126 },
127 .hw.init = &(struct clk_init_data){
128 .name = "sys_pll_dco",
129 .ops = &meson_clk_pll_ops,
130 .parent_data = &(const struct clk_parent_data) {
131 .fw_name = "xtal",
132 },
133 .num_parents = 1,
134
135 .flags = CLK_IS_CRITICAL,
136 },
137 };
138
139 static struct clk_regmap g12a_sys_pll = {
140 .data = &(struct clk_regmap_div_data){
141 .offset = HHI_SYS_PLL_CNTL0,
142 .shift = 16,
143 .width = 3,
144 .flags = CLK_DIVIDER_POWER_OF_TWO,
145 },
146 .hw.init = &(struct clk_init_data){
147 .name = "sys_pll",
148 .ops = &clk_regmap_divider_ops,
149 .parent_hws = (const struct clk_hw *[]) {
150 &g12a_sys_pll_dco.hw
151 },
152 .num_parents = 1,
153 .flags = CLK_SET_RATE_PARENT,
154 },
155 };
156
157 static struct clk_regmap g12b_sys1_pll_dco = {
158 .data = &(struct meson_clk_pll_data){
159 .en = {
160 .reg_off = HHI_SYS1_PLL_CNTL0,
161 .shift = 28,
162 .width = 1,
163 },
164 .m = {
165 .reg_off = HHI_SYS1_PLL_CNTL0,
166 .shift = 0,
167 .width = 8,
168 },
169 .n = {
170 .reg_off = HHI_SYS1_PLL_CNTL0,
171 .shift = 10,
172 .width = 5,
173 },
174 .l = {
175 .reg_off = HHI_SYS1_PLL_CNTL0,
176 .shift = 31,
177 .width = 1,
178 },
179 .rst = {
180 .reg_off = HHI_SYS1_PLL_CNTL0,
181 .shift = 29,
182 .width = 1,
183 },
184 .range = &g12a_sys_pll_mult_range,
185 },
186 .hw.init = &(struct clk_init_data){
187 .name = "sys1_pll_dco",
188 .ops = &meson_clk_pll_ops,
189 .parent_data = &(const struct clk_parent_data) {
190 .fw_name = "xtal",
191 },
192 .num_parents = 1,
193
194 .flags = CLK_IS_CRITICAL,
195 },
196 };
197
198 static struct clk_regmap g12b_sys1_pll = {
199 .data = &(struct clk_regmap_div_data){
200 .offset = HHI_SYS1_PLL_CNTL0,
201 .shift = 16,
202 .width = 3,
203 .flags = CLK_DIVIDER_POWER_OF_TWO,
204 },
205 .hw.init = &(struct clk_init_data){
206 .name = "sys1_pll",
207 .ops = &clk_regmap_divider_ops,
208 .parent_hws = (const struct clk_hw *[]) {
209 &g12b_sys1_pll_dco.hw
210 },
211 .num_parents = 1,
212 .flags = CLK_SET_RATE_PARENT,
213 },
214 };
215
216 static struct clk_regmap g12a_sys_pll_div16_en = {
217 .data = &(struct clk_regmap_gate_data){
218 .offset = HHI_SYS_CPU_CLK_CNTL1,
219 .bit_idx = 24,
220 },
221 .hw.init = &(struct clk_init_data) {
222 .name = "sys_pll_div16_en",
223 .ops = &clk_regmap_gate_ro_ops,
224 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
225 .num_parents = 1,
226
227
228
229
230 },
231 };
232
233 static struct clk_regmap g12b_sys1_pll_div16_en = {
234 .data = &(struct clk_regmap_gate_data){
235 .offset = HHI_SYS_CPUB_CLK_CNTL1,
236 .bit_idx = 24,
237 },
238 .hw.init = &(struct clk_init_data) {
239 .name = "sys1_pll_div16_en",
240 .ops = &clk_regmap_gate_ro_ops,
241 .parent_hws = (const struct clk_hw *[]) {
242 &g12b_sys1_pll.hw
243 },
244 .num_parents = 1,
245
246
247
248
249 },
250 };
251
252 static struct clk_fixed_factor g12a_sys_pll_div16 = {
253 .mult = 1,
254 .div = 16,
255 .hw.init = &(struct clk_init_data){
256 .name = "sys_pll_div16",
257 .ops = &clk_fixed_factor_ops,
258 .parent_hws = (const struct clk_hw *[]) {
259 &g12a_sys_pll_div16_en.hw
260 },
261 .num_parents = 1,
262 },
263 };
264
265 static struct clk_fixed_factor g12b_sys1_pll_div16 = {
266 .mult = 1,
267 .div = 16,
268 .hw.init = &(struct clk_init_data){
269 .name = "sys1_pll_div16",
270 .ops = &clk_fixed_factor_ops,
271 .parent_hws = (const struct clk_hw *[]) {
272 &g12b_sys1_pll_div16_en.hw
273 },
274 .num_parents = 1,
275 },
276 };
277
278 static struct clk_fixed_factor g12a_fclk_div2_div = {
279 .mult = 1,
280 .div = 2,
281 .hw.init = &(struct clk_init_data){
282 .name = "fclk_div2_div",
283 .ops = &clk_fixed_factor_ops,
284 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
285 .num_parents = 1,
286 },
287 };
288
289 static struct clk_regmap g12a_fclk_div2 = {
290 .data = &(struct clk_regmap_gate_data){
291 .offset = HHI_FIX_PLL_CNTL1,
292 .bit_idx = 24,
293 },
294 .hw.init = &(struct clk_init_data){
295 .name = "fclk_div2",
296 .ops = &clk_regmap_gate_ops,
297 .parent_hws = (const struct clk_hw *[]) {
298 &g12a_fclk_div2_div.hw
299 },
300 .num_parents = 1,
301 },
302 };
303
304 static struct clk_fixed_factor g12a_fclk_div3_div = {
305 .mult = 1,
306 .div = 3,
307 .hw.init = &(struct clk_init_data){
308 .name = "fclk_div3_div",
309 .ops = &clk_fixed_factor_ops,
310 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
311 .num_parents = 1,
312 },
313 };
314
315 static struct clk_regmap g12a_fclk_div3 = {
316 .data = &(struct clk_regmap_gate_data){
317 .offset = HHI_FIX_PLL_CNTL1,
318 .bit_idx = 20,
319 },
320 .hw.init = &(struct clk_init_data){
321 .name = "fclk_div3",
322 .ops = &clk_regmap_gate_ops,
323 .parent_hws = (const struct clk_hw *[]) {
324 &g12a_fclk_div3_div.hw
325 },
326 .num_parents = 1,
327
328
329
330
331
332
333
334
335
336 .flags = CLK_IS_CRITICAL,
337 },
338 };
339
340
341 static struct clk_regmap g12a_cpu_clk_premux0 = {
342 .data = &(struct clk_regmap_mux_data){
343 .offset = HHI_SYS_CPU_CLK_CNTL0,
344 .mask = 0x3,
345 .shift = 0,
346 .flags = CLK_MUX_ROUND_CLOSEST,
347 },
348 .hw.init = &(struct clk_init_data){
349 .name = "cpu_clk_dyn0_sel",
350 .ops = &clk_regmap_mux_ops,
351 .parent_data = (const struct clk_parent_data []) {
352 { .fw_name = "xtal", },
353 { .hw = &g12a_fclk_div2.hw },
354 { .hw = &g12a_fclk_div3.hw },
355 },
356 .num_parents = 3,
357 .flags = CLK_SET_RATE_PARENT,
358 },
359 };
360
361
362 static struct clk_regmap g12a_cpu_clk_premux1 = {
363 .data = &(struct clk_regmap_mux_data){
364 .offset = HHI_SYS_CPU_CLK_CNTL0,
365 .mask = 0x3,
366 .shift = 16,
367 },
368 .hw.init = &(struct clk_init_data){
369 .name = "cpu_clk_dyn1_sel",
370 .ops = &clk_regmap_mux_ops,
371 .parent_data = (const struct clk_parent_data []) {
372 { .fw_name = "xtal", },
373 { .hw = &g12a_fclk_div2.hw },
374 { .hw = &g12a_fclk_div3.hw },
375 },
376 .num_parents = 3,
377
378 .flags = CLK_SET_RATE_NO_REPARENT
379 },
380 };
381
382
383 static struct clk_regmap g12a_cpu_clk_mux0_div = {
384 .data = &(struct meson_clk_cpu_dyndiv_data){
385 .div = {
386 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
387 .shift = 4,
388 .width = 6,
389 },
390 .dyn = {
391 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
392 .shift = 26,
393 .width = 1,
394 },
395 },
396 .hw.init = &(struct clk_init_data){
397 .name = "cpu_clk_dyn0_div",
398 .ops = &meson_clk_cpu_dyndiv_ops,
399 .parent_hws = (const struct clk_hw *[]) {
400 &g12a_cpu_clk_premux0.hw
401 },
402 .num_parents = 1,
403 .flags = CLK_SET_RATE_PARENT,
404 },
405 };
406
407
408 static struct clk_regmap g12a_cpu_clk_postmux0 = {
409 .data = &(struct clk_regmap_mux_data){
410 .offset = HHI_SYS_CPU_CLK_CNTL0,
411 .mask = 0x1,
412 .shift = 2,
413 .flags = CLK_MUX_ROUND_CLOSEST,
414 },
415 .hw.init = &(struct clk_init_data){
416 .name = "cpu_clk_dyn0",
417 .ops = &clk_regmap_mux_ops,
418 .parent_hws = (const struct clk_hw *[]) {
419 &g12a_cpu_clk_premux0.hw,
420 &g12a_cpu_clk_mux0_div.hw,
421 },
422 .num_parents = 2,
423 .flags = CLK_SET_RATE_PARENT,
424 },
425 };
426
427
428 static struct clk_regmap g12a_cpu_clk_mux1_div = {
429 .data = &(struct clk_regmap_div_data){
430 .offset = HHI_SYS_CPU_CLK_CNTL0,
431 .shift = 20,
432 .width = 6,
433 },
434 .hw.init = &(struct clk_init_data){
435 .name = "cpu_clk_dyn1_div",
436 .ops = &clk_regmap_divider_ro_ops,
437 .parent_hws = (const struct clk_hw *[]) {
438 &g12a_cpu_clk_premux1.hw
439 },
440 .num_parents = 1,
441 },
442 };
443
444
445 static struct clk_regmap g12a_cpu_clk_postmux1 = {
446 .data = &(struct clk_regmap_mux_data){
447 .offset = HHI_SYS_CPU_CLK_CNTL0,
448 .mask = 0x1,
449 .shift = 18,
450 },
451 .hw.init = &(struct clk_init_data){
452 .name = "cpu_clk_dyn1",
453 .ops = &clk_regmap_mux_ops,
454 .parent_hws = (const struct clk_hw *[]) {
455 &g12a_cpu_clk_premux1.hw,
456 &g12a_cpu_clk_mux1_div.hw,
457 },
458 .num_parents = 2,
459
460 .flags = CLK_SET_RATE_NO_REPARENT,
461 },
462 };
463
464
465 static struct clk_regmap g12a_cpu_clk_dyn = {
466 .data = &(struct clk_regmap_mux_data){
467 .offset = HHI_SYS_CPU_CLK_CNTL0,
468 .mask = 0x1,
469 .shift = 10,
470 .flags = CLK_MUX_ROUND_CLOSEST,
471 },
472 .hw.init = &(struct clk_init_data){
473 .name = "cpu_clk_dyn",
474 .ops = &clk_regmap_mux_ops,
475 .parent_hws = (const struct clk_hw *[]) {
476 &g12a_cpu_clk_postmux0.hw,
477 &g12a_cpu_clk_postmux1.hw,
478 },
479 .num_parents = 2,
480 .flags = CLK_SET_RATE_PARENT,
481 },
482 };
483
484
485 static struct clk_regmap g12a_cpu_clk = {
486 .data = &(struct clk_regmap_mux_data){
487 .offset = HHI_SYS_CPU_CLK_CNTL0,
488 .mask = 0x1,
489 .shift = 11,
490 .flags = CLK_MUX_ROUND_CLOSEST,
491 },
492 .hw.init = &(struct clk_init_data){
493 .name = "cpu_clk",
494 .ops = &clk_regmap_mux_ops,
495 .parent_hws = (const struct clk_hw *[]) {
496 &g12a_cpu_clk_dyn.hw,
497 &g12a_sys_pll.hw,
498 },
499 .num_parents = 2,
500 .flags = CLK_SET_RATE_PARENT,
501 },
502 };
503
504
505 static struct clk_regmap g12b_cpu_clk = {
506 .data = &(struct clk_regmap_mux_data){
507 .offset = HHI_SYS_CPU_CLK_CNTL0,
508 .mask = 0x1,
509 .shift = 11,
510 .flags = CLK_MUX_ROUND_CLOSEST,
511 },
512 .hw.init = &(struct clk_init_data){
513 .name = "cpu_clk",
514 .ops = &clk_regmap_mux_ops,
515 .parent_hws = (const struct clk_hw *[]) {
516 &g12a_cpu_clk_dyn.hw,
517 &g12b_sys1_pll.hw
518 },
519 .num_parents = 2,
520 .flags = CLK_SET_RATE_PARENT,
521 },
522 };
523
524
525 static struct clk_regmap g12b_cpub_clk_premux0 = {
526 .data = &(struct clk_regmap_mux_data){
527 .offset = HHI_SYS_CPUB_CLK_CNTL,
528 .mask = 0x3,
529 .shift = 0,
530 .flags = CLK_MUX_ROUND_CLOSEST,
531 },
532 .hw.init = &(struct clk_init_data){
533 .name = "cpub_clk_dyn0_sel",
534 .ops = &clk_regmap_mux_ops,
535 .parent_data = (const struct clk_parent_data []) {
536 { .fw_name = "xtal", },
537 { .hw = &g12a_fclk_div2.hw },
538 { .hw = &g12a_fclk_div3.hw },
539 },
540 .num_parents = 3,
541 .flags = CLK_SET_RATE_PARENT,
542 },
543 };
544
545
546 static struct clk_regmap g12b_cpub_clk_mux0_div = {
547 .data = &(struct meson_clk_cpu_dyndiv_data){
548 .div = {
549 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
550 .shift = 4,
551 .width = 6,
552 },
553 .dyn = {
554 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
555 .shift = 26,
556 .width = 1,
557 },
558 },
559 .hw.init = &(struct clk_init_data){
560 .name = "cpub_clk_dyn0_div",
561 .ops = &meson_clk_cpu_dyndiv_ops,
562 .parent_hws = (const struct clk_hw *[]) {
563 &g12b_cpub_clk_premux0.hw
564 },
565 .num_parents = 1,
566 .flags = CLK_SET_RATE_PARENT,
567 },
568 };
569
570
571 static struct clk_regmap g12b_cpub_clk_postmux0 = {
572 .data = &(struct clk_regmap_mux_data){
573 .offset = HHI_SYS_CPUB_CLK_CNTL,
574 .mask = 0x1,
575 .shift = 2,
576 .flags = CLK_MUX_ROUND_CLOSEST,
577 },
578 .hw.init = &(struct clk_init_data){
579 .name = "cpub_clk_dyn0",
580 .ops = &clk_regmap_mux_ops,
581 .parent_hws = (const struct clk_hw *[]) {
582 &g12b_cpub_clk_premux0.hw,
583 &g12b_cpub_clk_mux0_div.hw
584 },
585 .num_parents = 2,
586 .flags = CLK_SET_RATE_PARENT,
587 },
588 };
589
590
591 static struct clk_regmap g12b_cpub_clk_premux1 = {
592 .data = &(struct clk_regmap_mux_data){
593 .offset = HHI_SYS_CPUB_CLK_CNTL,
594 .mask = 0x3,
595 .shift = 16,
596 },
597 .hw.init = &(struct clk_init_data){
598 .name = "cpub_clk_dyn1_sel",
599 .ops = &clk_regmap_mux_ops,
600 .parent_data = (const struct clk_parent_data []) {
601 { .fw_name = "xtal", },
602 { .hw = &g12a_fclk_div2.hw },
603 { .hw = &g12a_fclk_div3.hw },
604 },
605 .num_parents = 3,
606
607 .flags = CLK_SET_RATE_NO_REPARENT,
608 },
609 };
610
611
612 static struct clk_regmap g12b_cpub_clk_mux1_div = {
613 .data = &(struct clk_regmap_div_data){
614 .offset = HHI_SYS_CPUB_CLK_CNTL,
615 .shift = 20,
616 .width = 6,
617 },
618 .hw.init = &(struct clk_init_data){
619 .name = "cpub_clk_dyn1_div",
620 .ops = &clk_regmap_divider_ro_ops,
621 .parent_hws = (const struct clk_hw *[]) {
622 &g12b_cpub_clk_premux1.hw
623 },
624 .num_parents = 1,
625 },
626 };
627
628
629 static struct clk_regmap g12b_cpub_clk_postmux1 = {
630 .data = &(struct clk_regmap_mux_data){
631 .offset = HHI_SYS_CPUB_CLK_CNTL,
632 .mask = 0x1,
633 .shift = 18,
634 },
635 .hw.init = &(struct clk_init_data){
636 .name = "cpub_clk_dyn1",
637 .ops = &clk_regmap_mux_ops,
638 .parent_hws = (const struct clk_hw *[]) {
639 &g12b_cpub_clk_premux1.hw,
640 &g12b_cpub_clk_mux1_div.hw
641 },
642 .num_parents = 2,
643
644 .flags = CLK_SET_RATE_NO_REPARENT,
645 },
646 };
647
648
649 static struct clk_regmap g12b_cpub_clk_dyn = {
650 .data = &(struct clk_regmap_mux_data){
651 .offset = HHI_SYS_CPUB_CLK_CNTL,
652 .mask = 0x1,
653 .shift = 10,
654 .flags = CLK_MUX_ROUND_CLOSEST,
655 },
656 .hw.init = &(struct clk_init_data){
657 .name = "cpub_clk_dyn",
658 .ops = &clk_regmap_mux_ops,
659 .parent_hws = (const struct clk_hw *[]) {
660 &g12b_cpub_clk_postmux0.hw,
661 &g12b_cpub_clk_postmux1.hw
662 },
663 .num_parents = 2,
664 .flags = CLK_SET_RATE_PARENT,
665 },
666 };
667
668
669 static struct clk_regmap g12b_cpub_clk = {
670 .data = &(struct clk_regmap_mux_data){
671 .offset = HHI_SYS_CPUB_CLK_CNTL,
672 .mask = 0x1,
673 .shift = 11,
674 .flags = CLK_MUX_ROUND_CLOSEST,
675 },
676 .hw.init = &(struct clk_init_data){
677 .name = "cpub_clk",
678 .ops = &clk_regmap_mux_ops,
679 .parent_hws = (const struct clk_hw *[]) {
680 &g12b_cpub_clk_dyn.hw,
681 &g12a_sys_pll.hw
682 },
683 .num_parents = 2,
684 .flags = CLK_SET_RATE_PARENT,
685 },
686 };
687
688 static struct clk_regmap sm1_gp1_pll;
689
690
691 static struct clk_regmap sm1_dsu_clk_premux0 = {
692 .data = &(struct clk_regmap_mux_data){
693 .offset = HHI_SYS_CPU_CLK_CNTL5,
694 .mask = 0x3,
695 .shift = 0,
696 },
697 .hw.init = &(struct clk_init_data){
698 .name = "dsu_clk_dyn0_sel",
699 .ops = &clk_regmap_mux_ro_ops,
700 .parent_data = (const struct clk_parent_data []) {
701 { .fw_name = "xtal", },
702 { .hw = &g12a_fclk_div2.hw },
703 { .hw = &g12a_fclk_div3.hw },
704 { .hw = &sm1_gp1_pll.hw },
705 },
706 .num_parents = 4,
707 },
708 };
709
710
711 static struct clk_regmap sm1_dsu_clk_premux1 = {
712 .data = &(struct clk_regmap_mux_data){
713 .offset = HHI_SYS_CPU_CLK_CNTL5,
714 .mask = 0x3,
715 .shift = 16,
716 },
717 .hw.init = &(struct clk_init_data){
718 .name = "dsu_clk_dyn1_sel",
719 .ops = &clk_regmap_mux_ro_ops,
720 .parent_data = (const struct clk_parent_data []) {
721 { .fw_name = "xtal", },
722 { .hw = &g12a_fclk_div2.hw },
723 { .hw = &g12a_fclk_div3.hw },
724 { .hw = &sm1_gp1_pll.hw },
725 },
726 .num_parents = 4,
727 },
728 };
729
730
731 static struct clk_regmap sm1_dsu_clk_mux0_div = {
732 .data = &(struct clk_regmap_div_data){
733 .offset = HHI_SYS_CPU_CLK_CNTL5,
734 .shift = 4,
735 .width = 6,
736 },
737 .hw.init = &(struct clk_init_data){
738 .name = "dsu_clk_dyn0_div",
739 .ops = &clk_regmap_divider_ro_ops,
740 .parent_hws = (const struct clk_hw *[]) {
741 &sm1_dsu_clk_premux0.hw
742 },
743 .num_parents = 1,
744 },
745 };
746
747
748 static struct clk_regmap sm1_dsu_clk_postmux0 = {
749 .data = &(struct clk_regmap_mux_data){
750 .offset = HHI_SYS_CPU_CLK_CNTL5,
751 .mask = 0x1,
752 .shift = 2,
753 },
754 .hw.init = &(struct clk_init_data){
755 .name = "dsu_clk_dyn0",
756 .ops = &clk_regmap_mux_ro_ops,
757 .parent_hws = (const struct clk_hw *[]) {
758 &sm1_dsu_clk_premux0.hw,
759 &sm1_dsu_clk_mux0_div.hw,
760 },
761 .num_parents = 2,
762 },
763 };
764
765
766 static struct clk_regmap sm1_dsu_clk_mux1_div = {
767 .data = &(struct clk_regmap_div_data){
768 .offset = HHI_SYS_CPU_CLK_CNTL5,
769 .shift = 20,
770 .width = 6,
771 },
772 .hw.init = &(struct clk_init_data){
773 .name = "dsu_clk_dyn1_div",
774 .ops = &clk_regmap_divider_ro_ops,
775 .parent_hws = (const struct clk_hw *[]) {
776 &sm1_dsu_clk_premux1.hw
777 },
778 .num_parents = 1,
779 },
780 };
781
782
783 static struct clk_regmap sm1_dsu_clk_postmux1 = {
784 .data = &(struct clk_regmap_mux_data){
785 .offset = HHI_SYS_CPU_CLK_CNTL5,
786 .mask = 0x1,
787 .shift = 18,
788 },
789 .hw.init = &(struct clk_init_data){
790 .name = "dsu_clk_dyn1",
791 .ops = &clk_regmap_mux_ro_ops,
792 .parent_hws = (const struct clk_hw *[]) {
793 &sm1_dsu_clk_premux1.hw,
794 &sm1_dsu_clk_mux1_div.hw,
795 },
796 .num_parents = 2,
797 },
798 };
799
800
801 static struct clk_regmap sm1_dsu_clk_dyn = {
802 .data = &(struct clk_regmap_mux_data){
803 .offset = HHI_SYS_CPU_CLK_CNTL5,
804 .mask = 0x1,
805 .shift = 10,
806 },
807 .hw.init = &(struct clk_init_data){
808 .name = "dsu_clk_dyn",
809 .ops = &clk_regmap_mux_ro_ops,
810 .parent_hws = (const struct clk_hw *[]) {
811 &sm1_dsu_clk_postmux0.hw,
812 &sm1_dsu_clk_postmux1.hw,
813 },
814 .num_parents = 2,
815 },
816 };
817
818
819 static struct clk_regmap sm1_dsu_final_clk = {
820 .data = &(struct clk_regmap_mux_data){
821 .offset = HHI_SYS_CPU_CLK_CNTL5,
822 .mask = 0x1,
823 .shift = 11,
824 },
825 .hw.init = &(struct clk_init_data){
826 .name = "dsu_clk_final",
827 .ops = &clk_regmap_mux_ro_ops,
828 .parent_hws = (const struct clk_hw *[]) {
829 &sm1_dsu_clk_dyn.hw,
830 &g12a_sys_pll.hw,
831 },
832 .num_parents = 2,
833 },
834 };
835
836
837 static struct clk_regmap sm1_cpu1_clk = {
838 .data = &(struct clk_regmap_mux_data){
839 .offset = HHI_SYS_CPU_CLK_CNTL6,
840 .mask = 0x1,
841 .shift = 24,
842 },
843 .hw.init = &(struct clk_init_data){
844 .name = "cpu1_clk",
845 .ops = &clk_regmap_mux_ro_ops,
846 .parent_hws = (const struct clk_hw *[]) {
847 &g12a_cpu_clk.hw,
848
849 },
850 .num_parents = 1,
851 },
852 };
853
854
855 static struct clk_regmap sm1_cpu2_clk = {
856 .data = &(struct clk_regmap_mux_data){
857 .offset = HHI_SYS_CPU_CLK_CNTL6,
858 .mask = 0x1,
859 .shift = 25,
860 },
861 .hw.init = &(struct clk_init_data){
862 .name = "cpu2_clk",
863 .ops = &clk_regmap_mux_ro_ops,
864 .parent_hws = (const struct clk_hw *[]) {
865 &g12a_cpu_clk.hw,
866
867 },
868 .num_parents = 1,
869 },
870 };
871
872
873 static struct clk_regmap sm1_cpu3_clk = {
874 .data = &(struct clk_regmap_mux_data){
875 .offset = HHI_SYS_CPU_CLK_CNTL6,
876 .mask = 0x1,
877 .shift = 26,
878 },
879 .hw.init = &(struct clk_init_data){
880 .name = "cpu3_clk",
881 .ops = &clk_regmap_mux_ro_ops,
882 .parent_hws = (const struct clk_hw *[]) {
883 &g12a_cpu_clk.hw,
884
885 },
886 .num_parents = 1,
887 },
888 };
889
890
891 static struct clk_regmap sm1_dsu_clk = {
892 .data = &(struct clk_regmap_mux_data){
893 .offset = HHI_SYS_CPU_CLK_CNTL6,
894 .mask = 0x1,
895 .shift = 27,
896 },
897 .hw.init = &(struct clk_init_data){
898 .name = "dsu_clk",
899 .ops = &clk_regmap_mux_ro_ops,
900 .parent_hws = (const struct clk_hw *[]) {
901 &g12a_cpu_clk.hw,
902 &sm1_dsu_final_clk.hw,
903 },
904 .num_parents = 2,
905 },
906 };
907
908 static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
909 unsigned long event, void *data)
910 {
911 if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
912
913 udelay(100);
914 return NOTIFY_OK;
915 }
916
917 return NOTIFY_DONE;
918 }
919
920 static struct notifier_block g12a_cpu_clk_mux_nb = {
921 .notifier_call = g12a_cpu_clk_mux_notifier_cb,
922 };
923
924 struct g12a_cpu_clk_postmux_nb_data {
925 struct notifier_block nb;
926 struct clk_hw *xtal;
927 struct clk_hw *cpu_clk_dyn;
928 struct clk_hw *cpu_clk_postmux0;
929 struct clk_hw *cpu_clk_postmux1;
930 struct clk_hw *cpu_clk_premux1;
931 };
932
933 static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
934 unsigned long event, void *data)
935 {
936 struct g12a_cpu_clk_postmux_nb_data *nb_data =
937 container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
938
939 switch (event) {
940 case PRE_RATE_CHANGE:
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956 clk_hw_set_parent(nb_data->cpu_clk_premux1,
957 nb_data->xtal);
958
959
960 clk_hw_set_parent(nb_data->cpu_clk_postmux1,
961 nb_data->cpu_clk_premux1);
962
963
964 clk_hw_set_parent(nb_data->cpu_clk_dyn,
965 nb_data->cpu_clk_postmux1);
966
967
968
969
970
971
972
973
974
975
976 udelay(100);
977
978 return NOTIFY_OK;
979
980 case POST_RATE_CHANGE:
981
982
983
984
985
986
987
988 clk_hw_set_parent(nb_data->cpu_clk_dyn,
989 nb_data->cpu_clk_postmux0);
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004 udelay(100);
1005
1006 return NOTIFY_OK;
1007
1008 default:
1009 return NOTIFY_DONE;
1010 }
1011 }
1012
1013 static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1014 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1015 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1016 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1017 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1018 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1019 };
1020
1021 static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1022 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1023 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1024 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1025 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1026 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1027 };
1028
1029 struct g12a_sys_pll_nb_data {
1030 struct notifier_block nb;
1031 struct clk_hw *sys_pll;
1032 struct clk_hw *cpu_clk;
1033 struct clk_hw *cpu_clk_dyn;
1034 };
1035
1036 static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1037 unsigned long event, void *data)
1038 {
1039 struct g12a_sys_pll_nb_data *nb_data =
1040 container_of(nb, struct g12a_sys_pll_nb_data, nb);
1041
1042 switch (event) {
1043 case PRE_RATE_CHANGE:
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053 clk_hw_set_parent(nb_data->cpu_clk,
1054 nb_data->cpu_clk_dyn);
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067 udelay(100);
1068
1069 return NOTIFY_OK;
1070
1071 case POST_RATE_CHANGE:
1072
1073
1074
1075
1076
1077
1078 clk_hw_set_parent(nb_data->cpu_clk,
1079 nb_data->sys_pll);
1080
1081 udelay(100);
1082
1083
1084
1085
1086
1087
1088
1089 return NOTIFY_OK;
1090
1091 default:
1092 return NOTIFY_DONE;
1093 }
1094 }
1095
1096 static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1097 .sys_pll = &g12a_sys_pll.hw,
1098 .cpu_clk = &g12a_cpu_clk.hw,
1099 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1100 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1101 };
1102
1103
1104 static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1105 .sys_pll = &g12b_sys1_pll.hw,
1106 .cpu_clk = &g12b_cpu_clk.hw,
1107 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1108 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1109 };
1110
1111
1112 static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1113 .sys_pll = &g12a_sys_pll.hw,
1114 .cpu_clk = &g12b_cpub_clk.hw,
1115 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1116 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1117 };
1118
1119 static struct clk_regmap g12a_cpu_clk_div16_en = {
1120 .data = &(struct clk_regmap_gate_data){
1121 .offset = HHI_SYS_CPU_CLK_CNTL1,
1122 .bit_idx = 1,
1123 },
1124 .hw.init = &(struct clk_init_data) {
1125 .name = "cpu_clk_div16_en",
1126 .ops = &clk_regmap_gate_ro_ops,
1127 .parent_hws = (const struct clk_hw *[]) {
1128 &g12a_cpu_clk.hw
1129 },
1130 .num_parents = 1,
1131
1132
1133
1134
1135 },
1136 };
1137
1138 static struct clk_regmap g12b_cpub_clk_div16_en = {
1139 .data = &(struct clk_regmap_gate_data){
1140 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1141 .bit_idx = 1,
1142 },
1143 .hw.init = &(struct clk_init_data) {
1144 .name = "cpub_clk_div16_en",
1145 .ops = &clk_regmap_gate_ro_ops,
1146 .parent_hws = (const struct clk_hw *[]) {
1147 &g12b_cpub_clk.hw
1148 },
1149 .num_parents = 1,
1150
1151
1152
1153
1154 },
1155 };
1156
1157 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1158 .mult = 1,
1159 .div = 16,
1160 .hw.init = &(struct clk_init_data){
1161 .name = "cpu_clk_div16",
1162 .ops = &clk_fixed_factor_ops,
1163 .parent_hws = (const struct clk_hw *[]) {
1164 &g12a_cpu_clk_div16_en.hw
1165 },
1166 .num_parents = 1,
1167 },
1168 };
1169
1170 static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1171 .mult = 1,
1172 .div = 16,
1173 .hw.init = &(struct clk_init_data){
1174 .name = "cpub_clk_div16",
1175 .ops = &clk_fixed_factor_ops,
1176 .parent_hws = (const struct clk_hw *[]) {
1177 &g12b_cpub_clk_div16_en.hw
1178 },
1179 .num_parents = 1,
1180 },
1181 };
1182
1183 static struct clk_regmap g12a_cpu_clk_apb_div = {
1184 .data = &(struct clk_regmap_div_data){
1185 .offset = HHI_SYS_CPU_CLK_CNTL1,
1186 .shift = 3,
1187 .width = 3,
1188 .flags = CLK_DIVIDER_POWER_OF_TWO,
1189 },
1190 .hw.init = &(struct clk_init_data){
1191 .name = "cpu_clk_apb_div",
1192 .ops = &clk_regmap_divider_ro_ops,
1193 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1194 .num_parents = 1,
1195 },
1196 };
1197
1198 static struct clk_regmap g12a_cpu_clk_apb = {
1199 .data = &(struct clk_regmap_gate_data){
1200 .offset = HHI_SYS_CPU_CLK_CNTL1,
1201 .bit_idx = 1,
1202 },
1203 .hw.init = &(struct clk_init_data) {
1204 .name = "cpu_clk_apb",
1205 .ops = &clk_regmap_gate_ro_ops,
1206 .parent_hws = (const struct clk_hw *[]) {
1207 &g12a_cpu_clk_apb_div.hw
1208 },
1209 .num_parents = 1,
1210
1211
1212
1213
1214 },
1215 };
1216
1217 static struct clk_regmap g12a_cpu_clk_atb_div = {
1218 .data = &(struct clk_regmap_div_data){
1219 .offset = HHI_SYS_CPU_CLK_CNTL1,
1220 .shift = 6,
1221 .width = 3,
1222 .flags = CLK_DIVIDER_POWER_OF_TWO,
1223 },
1224 .hw.init = &(struct clk_init_data){
1225 .name = "cpu_clk_atb_div",
1226 .ops = &clk_regmap_divider_ro_ops,
1227 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1228 .num_parents = 1,
1229 },
1230 };
1231
1232 static struct clk_regmap g12a_cpu_clk_atb = {
1233 .data = &(struct clk_regmap_gate_data){
1234 .offset = HHI_SYS_CPU_CLK_CNTL1,
1235 .bit_idx = 17,
1236 },
1237 .hw.init = &(struct clk_init_data) {
1238 .name = "cpu_clk_atb",
1239 .ops = &clk_regmap_gate_ro_ops,
1240 .parent_hws = (const struct clk_hw *[]) {
1241 &g12a_cpu_clk_atb_div.hw
1242 },
1243 .num_parents = 1,
1244
1245
1246
1247
1248 },
1249 };
1250
1251 static struct clk_regmap g12a_cpu_clk_axi_div = {
1252 .data = &(struct clk_regmap_div_data){
1253 .offset = HHI_SYS_CPU_CLK_CNTL1,
1254 .shift = 9,
1255 .width = 3,
1256 .flags = CLK_DIVIDER_POWER_OF_TWO,
1257 },
1258 .hw.init = &(struct clk_init_data){
1259 .name = "cpu_clk_axi_div",
1260 .ops = &clk_regmap_divider_ro_ops,
1261 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1262 .num_parents = 1,
1263 },
1264 };
1265
1266 static struct clk_regmap g12a_cpu_clk_axi = {
1267 .data = &(struct clk_regmap_gate_data){
1268 .offset = HHI_SYS_CPU_CLK_CNTL1,
1269 .bit_idx = 18,
1270 },
1271 .hw.init = &(struct clk_init_data) {
1272 .name = "cpu_clk_axi",
1273 .ops = &clk_regmap_gate_ro_ops,
1274 .parent_hws = (const struct clk_hw *[]) {
1275 &g12a_cpu_clk_axi_div.hw
1276 },
1277 .num_parents = 1,
1278
1279
1280
1281
1282 },
1283 };
1284
1285 static struct clk_regmap g12a_cpu_clk_trace_div = {
1286 .data = &(struct clk_regmap_div_data){
1287 .offset = HHI_SYS_CPU_CLK_CNTL1,
1288 .shift = 20,
1289 .width = 3,
1290 .flags = CLK_DIVIDER_POWER_OF_TWO,
1291 },
1292 .hw.init = &(struct clk_init_data){
1293 .name = "cpu_clk_trace_div",
1294 .ops = &clk_regmap_divider_ro_ops,
1295 .parent_data = &(const struct clk_parent_data) {
1296
1297
1298
1299
1300
1301
1302
1303 .name = "cpu_clk",
1304 .index = -1,
1305 },
1306 .num_parents = 1,
1307 },
1308 };
1309
1310 static struct clk_regmap g12a_cpu_clk_trace = {
1311 .data = &(struct clk_regmap_gate_data){
1312 .offset = HHI_SYS_CPU_CLK_CNTL1,
1313 .bit_idx = 23,
1314 },
1315 .hw.init = &(struct clk_init_data) {
1316 .name = "cpu_clk_trace",
1317 .ops = &clk_regmap_gate_ro_ops,
1318 .parent_hws = (const struct clk_hw *[]) {
1319 &g12a_cpu_clk_trace_div.hw
1320 },
1321 .num_parents = 1,
1322
1323
1324
1325
1326 },
1327 };
1328
1329 static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1330 .mult = 1,
1331 .div = 2,
1332 .hw.init = &(struct clk_init_data){
1333 .name = "cpub_clk_div2",
1334 .ops = &clk_fixed_factor_ops,
1335 .parent_hws = (const struct clk_hw *[]) {
1336 &g12b_cpub_clk.hw
1337 },
1338 .num_parents = 1,
1339 },
1340 };
1341
1342 static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1343 .mult = 1,
1344 .div = 3,
1345 .hw.init = &(struct clk_init_data){
1346 .name = "cpub_clk_div3",
1347 .ops = &clk_fixed_factor_ops,
1348 .parent_hws = (const struct clk_hw *[]) {
1349 &g12b_cpub_clk.hw
1350 },
1351 .num_parents = 1,
1352 },
1353 };
1354
1355 static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1356 .mult = 1,
1357 .div = 4,
1358 .hw.init = &(struct clk_init_data){
1359 .name = "cpub_clk_div4",
1360 .ops = &clk_fixed_factor_ops,
1361 .parent_hws = (const struct clk_hw *[]) {
1362 &g12b_cpub_clk.hw
1363 },
1364 .num_parents = 1,
1365 },
1366 };
1367
1368 static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1369 .mult = 1,
1370 .div = 5,
1371 .hw.init = &(struct clk_init_data){
1372 .name = "cpub_clk_div5",
1373 .ops = &clk_fixed_factor_ops,
1374 .parent_hws = (const struct clk_hw *[]) {
1375 &g12b_cpub_clk.hw
1376 },
1377 .num_parents = 1,
1378 },
1379 };
1380
1381 static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1382 .mult = 1,
1383 .div = 6,
1384 .hw.init = &(struct clk_init_data){
1385 .name = "cpub_clk_div6",
1386 .ops = &clk_fixed_factor_ops,
1387 .parent_hws = (const struct clk_hw *[]) {
1388 &g12b_cpub_clk.hw
1389 },
1390 .num_parents = 1,
1391 },
1392 };
1393
1394 static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1395 .mult = 1,
1396 .div = 7,
1397 .hw.init = &(struct clk_init_data){
1398 .name = "cpub_clk_div7",
1399 .ops = &clk_fixed_factor_ops,
1400 .parent_hws = (const struct clk_hw *[]) {
1401 &g12b_cpub_clk.hw
1402 },
1403 .num_parents = 1,
1404 },
1405 };
1406
1407 static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1408 .mult = 1,
1409 .div = 8,
1410 .hw.init = &(struct clk_init_data){
1411 .name = "cpub_clk_div8",
1412 .ops = &clk_fixed_factor_ops,
1413 .parent_hws = (const struct clk_hw *[]) {
1414 &g12b_cpub_clk.hw
1415 },
1416 .num_parents = 1,
1417 },
1418 };
1419
1420 static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1421 static struct clk_regmap g12b_cpub_clk_apb_sel = {
1422 .data = &(struct clk_regmap_mux_data){
1423 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1424 .mask = 7,
1425 .shift = 3,
1426 .table = mux_table_cpub,
1427 },
1428 .hw.init = &(struct clk_init_data){
1429 .name = "cpub_clk_apb_sel",
1430 .ops = &clk_regmap_mux_ro_ops,
1431 .parent_hws = (const struct clk_hw *[]) {
1432 &g12b_cpub_clk_div2.hw,
1433 &g12b_cpub_clk_div3.hw,
1434 &g12b_cpub_clk_div4.hw,
1435 &g12b_cpub_clk_div5.hw,
1436 &g12b_cpub_clk_div6.hw,
1437 &g12b_cpub_clk_div7.hw,
1438 &g12b_cpub_clk_div8.hw
1439 },
1440 .num_parents = 7,
1441 },
1442 };
1443
1444 static struct clk_regmap g12b_cpub_clk_apb = {
1445 .data = &(struct clk_regmap_gate_data){
1446 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1447 .bit_idx = 16,
1448 .flags = CLK_GATE_SET_TO_DISABLE,
1449 },
1450 .hw.init = &(struct clk_init_data) {
1451 .name = "cpub_clk_apb",
1452 .ops = &clk_regmap_gate_ro_ops,
1453 .parent_hws = (const struct clk_hw *[]) {
1454 &g12b_cpub_clk_apb_sel.hw
1455 },
1456 .num_parents = 1,
1457
1458
1459
1460
1461 },
1462 };
1463
1464 static struct clk_regmap g12b_cpub_clk_atb_sel = {
1465 .data = &(struct clk_regmap_mux_data){
1466 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1467 .mask = 7,
1468 .shift = 6,
1469 .table = mux_table_cpub,
1470 },
1471 .hw.init = &(struct clk_init_data){
1472 .name = "cpub_clk_atb_sel",
1473 .ops = &clk_regmap_mux_ro_ops,
1474 .parent_hws = (const struct clk_hw *[]) {
1475 &g12b_cpub_clk_div2.hw,
1476 &g12b_cpub_clk_div3.hw,
1477 &g12b_cpub_clk_div4.hw,
1478 &g12b_cpub_clk_div5.hw,
1479 &g12b_cpub_clk_div6.hw,
1480 &g12b_cpub_clk_div7.hw,
1481 &g12b_cpub_clk_div8.hw
1482 },
1483 .num_parents = 7,
1484 },
1485 };
1486
1487 static struct clk_regmap g12b_cpub_clk_atb = {
1488 .data = &(struct clk_regmap_gate_data){
1489 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1490 .bit_idx = 17,
1491 .flags = CLK_GATE_SET_TO_DISABLE,
1492 },
1493 .hw.init = &(struct clk_init_data) {
1494 .name = "cpub_clk_atb",
1495 .ops = &clk_regmap_gate_ro_ops,
1496 .parent_hws = (const struct clk_hw *[]) {
1497 &g12b_cpub_clk_atb_sel.hw
1498 },
1499 .num_parents = 1,
1500
1501
1502
1503
1504 },
1505 };
1506
1507 static struct clk_regmap g12b_cpub_clk_axi_sel = {
1508 .data = &(struct clk_regmap_mux_data){
1509 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1510 .mask = 7,
1511 .shift = 9,
1512 .table = mux_table_cpub,
1513 },
1514 .hw.init = &(struct clk_init_data){
1515 .name = "cpub_clk_axi_sel",
1516 .ops = &clk_regmap_mux_ro_ops,
1517 .parent_hws = (const struct clk_hw *[]) {
1518 &g12b_cpub_clk_div2.hw,
1519 &g12b_cpub_clk_div3.hw,
1520 &g12b_cpub_clk_div4.hw,
1521 &g12b_cpub_clk_div5.hw,
1522 &g12b_cpub_clk_div6.hw,
1523 &g12b_cpub_clk_div7.hw,
1524 &g12b_cpub_clk_div8.hw
1525 },
1526 .num_parents = 7,
1527 },
1528 };
1529
1530 static struct clk_regmap g12b_cpub_clk_axi = {
1531 .data = &(struct clk_regmap_gate_data){
1532 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1533 .bit_idx = 18,
1534 .flags = CLK_GATE_SET_TO_DISABLE,
1535 },
1536 .hw.init = &(struct clk_init_data) {
1537 .name = "cpub_clk_axi",
1538 .ops = &clk_regmap_gate_ro_ops,
1539 .parent_hws = (const struct clk_hw *[]) {
1540 &g12b_cpub_clk_axi_sel.hw
1541 },
1542 .num_parents = 1,
1543
1544
1545
1546
1547 },
1548 };
1549
1550 static struct clk_regmap g12b_cpub_clk_trace_sel = {
1551 .data = &(struct clk_regmap_mux_data){
1552 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1553 .mask = 7,
1554 .shift = 20,
1555 .table = mux_table_cpub,
1556 },
1557 .hw.init = &(struct clk_init_data){
1558 .name = "cpub_clk_trace_sel",
1559 .ops = &clk_regmap_mux_ro_ops,
1560 .parent_hws = (const struct clk_hw *[]) {
1561 &g12b_cpub_clk_div2.hw,
1562 &g12b_cpub_clk_div3.hw,
1563 &g12b_cpub_clk_div4.hw,
1564 &g12b_cpub_clk_div5.hw,
1565 &g12b_cpub_clk_div6.hw,
1566 &g12b_cpub_clk_div7.hw,
1567 &g12b_cpub_clk_div8.hw
1568 },
1569 .num_parents = 7,
1570 },
1571 };
1572
1573 static struct clk_regmap g12b_cpub_clk_trace = {
1574 .data = &(struct clk_regmap_gate_data){
1575 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1576 .bit_idx = 23,
1577 .flags = CLK_GATE_SET_TO_DISABLE,
1578 },
1579 .hw.init = &(struct clk_init_data) {
1580 .name = "cpub_clk_trace",
1581 .ops = &clk_regmap_gate_ro_ops,
1582 .parent_hws = (const struct clk_hw *[]) {
1583 &g12b_cpub_clk_trace_sel.hw
1584 },
1585 .num_parents = 1,
1586
1587
1588
1589
1590 },
1591 };
1592
1593 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1594 .min = 55,
1595 .max = 255,
1596 };
1597
1598
1599
1600
1601 static const struct reg_sequence g12a_gp0_init_regs[] = {
1602 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
1603 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
1604 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
1605 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
1606 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
1607 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
1608 };
1609
1610 static struct clk_regmap g12a_gp0_pll_dco = {
1611 .data = &(struct meson_clk_pll_data){
1612 .en = {
1613 .reg_off = HHI_GP0_PLL_CNTL0,
1614 .shift = 28,
1615 .width = 1,
1616 },
1617 .m = {
1618 .reg_off = HHI_GP0_PLL_CNTL0,
1619 .shift = 0,
1620 .width = 8,
1621 },
1622 .n = {
1623 .reg_off = HHI_GP0_PLL_CNTL0,
1624 .shift = 10,
1625 .width = 5,
1626 },
1627 .frac = {
1628 .reg_off = HHI_GP0_PLL_CNTL1,
1629 .shift = 0,
1630 .width = 17,
1631 },
1632 .l = {
1633 .reg_off = HHI_GP0_PLL_CNTL0,
1634 .shift = 31,
1635 .width = 1,
1636 },
1637 .rst = {
1638 .reg_off = HHI_GP0_PLL_CNTL0,
1639 .shift = 29,
1640 .width = 1,
1641 },
1642 .range = &g12a_gp0_pll_mult_range,
1643 .init_regs = g12a_gp0_init_regs,
1644 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1645 },
1646 .hw.init = &(struct clk_init_data){
1647 .name = "gp0_pll_dco",
1648 .ops = &meson_clk_pll_ops,
1649 .parent_data = &(const struct clk_parent_data) {
1650 .fw_name = "xtal",
1651 },
1652 .num_parents = 1,
1653 },
1654 };
1655
1656 static struct clk_regmap g12a_gp0_pll = {
1657 .data = &(struct clk_regmap_div_data){
1658 .offset = HHI_GP0_PLL_CNTL0,
1659 .shift = 16,
1660 .width = 3,
1661 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1662 CLK_DIVIDER_ROUND_CLOSEST),
1663 },
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gp0_pll",
1666 .ops = &clk_regmap_divider_ops,
1667 .parent_hws = (const struct clk_hw *[]) {
1668 &g12a_gp0_pll_dco.hw
1669 },
1670 .num_parents = 1,
1671 .flags = CLK_SET_RATE_PARENT,
1672 },
1673 };
1674
1675 static struct clk_regmap sm1_gp1_pll_dco = {
1676 .data = &(struct meson_clk_pll_data){
1677 .en = {
1678 .reg_off = HHI_GP1_PLL_CNTL0,
1679 .shift = 28,
1680 .width = 1,
1681 },
1682 .m = {
1683 .reg_off = HHI_GP1_PLL_CNTL0,
1684 .shift = 0,
1685 .width = 8,
1686 },
1687 .n = {
1688 .reg_off = HHI_GP1_PLL_CNTL0,
1689 .shift = 10,
1690 .width = 5,
1691 },
1692 .frac = {
1693 .reg_off = HHI_GP1_PLL_CNTL1,
1694 .shift = 0,
1695 .width = 17,
1696 },
1697 .l = {
1698 .reg_off = HHI_GP1_PLL_CNTL0,
1699 .shift = 31,
1700 .width = 1,
1701 },
1702 .rst = {
1703 .reg_off = HHI_GP1_PLL_CNTL0,
1704 .shift = 29,
1705 .width = 1,
1706 },
1707 },
1708 .hw.init = &(struct clk_init_data){
1709 .name = "gp1_pll_dco",
1710 .ops = &meson_clk_pll_ro_ops,
1711 .parent_data = &(const struct clk_parent_data) {
1712 .fw_name = "xtal",
1713 },
1714 .num_parents = 1,
1715
1716 .flags = CLK_IS_CRITICAL,
1717 },
1718 };
1719
1720 static struct clk_regmap sm1_gp1_pll = {
1721 .data = &(struct clk_regmap_div_data){
1722 .offset = HHI_GP1_PLL_CNTL0,
1723 .shift = 16,
1724 .width = 3,
1725 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1726 CLK_DIVIDER_ROUND_CLOSEST),
1727 },
1728 .hw.init = &(struct clk_init_data){
1729 .name = "gp1_pll",
1730 .ops = &clk_regmap_divider_ro_ops,
1731 .parent_hws = (const struct clk_hw *[]) {
1732 &sm1_gp1_pll_dco.hw
1733 },
1734 .num_parents = 1,
1735 },
1736 };
1737
1738
1739
1740
1741 static const struct reg_sequence g12a_hifi_init_regs[] = {
1742 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
1743 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
1744 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
1745 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
1746 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
1747 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
1748 };
1749
1750 static struct clk_regmap g12a_hifi_pll_dco = {
1751 .data = &(struct meson_clk_pll_data){
1752 .en = {
1753 .reg_off = HHI_HIFI_PLL_CNTL0,
1754 .shift = 28,
1755 .width = 1,
1756 },
1757 .m = {
1758 .reg_off = HHI_HIFI_PLL_CNTL0,
1759 .shift = 0,
1760 .width = 8,
1761 },
1762 .n = {
1763 .reg_off = HHI_HIFI_PLL_CNTL0,
1764 .shift = 10,
1765 .width = 5,
1766 },
1767 .frac = {
1768 .reg_off = HHI_HIFI_PLL_CNTL1,
1769 .shift = 0,
1770 .width = 17,
1771 },
1772 .l = {
1773 .reg_off = HHI_HIFI_PLL_CNTL0,
1774 .shift = 31,
1775 .width = 1,
1776 },
1777 .rst = {
1778 .reg_off = HHI_HIFI_PLL_CNTL0,
1779 .shift = 29,
1780 .width = 1,
1781 },
1782 .range = &g12a_gp0_pll_mult_range,
1783 .init_regs = g12a_hifi_init_regs,
1784 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1785 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
1786 },
1787 .hw.init = &(struct clk_init_data){
1788 .name = "hifi_pll_dco",
1789 .ops = &meson_clk_pll_ops,
1790 .parent_data = &(const struct clk_parent_data) {
1791 .fw_name = "xtal",
1792 },
1793 .num_parents = 1,
1794 },
1795 };
1796
1797 static struct clk_regmap g12a_hifi_pll = {
1798 .data = &(struct clk_regmap_div_data){
1799 .offset = HHI_HIFI_PLL_CNTL0,
1800 .shift = 16,
1801 .width = 2,
1802 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1803 CLK_DIVIDER_ROUND_CLOSEST),
1804 },
1805 .hw.init = &(struct clk_init_data){
1806 .name = "hifi_pll",
1807 .ops = &clk_regmap_divider_ops,
1808 .parent_hws = (const struct clk_hw *[]) {
1809 &g12a_hifi_pll_dco.hw
1810 },
1811 .num_parents = 1,
1812 .flags = CLK_SET_RATE_PARENT,
1813 },
1814 };
1815
1816
1817
1818
1819
1820
1821 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1822 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
1823 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
1824 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
1825 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
1826 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
1827 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
1828 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
1829 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
1830 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
1831 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
1832 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
1833 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
1834 };
1835
1836
1837 static const struct pll_params_table g12a_pcie_pll_table[] = {
1838 PLL_PARAMS(150, 1),
1839 {0, 0},
1840 };
1841
1842 static struct clk_regmap g12a_pcie_pll_dco = {
1843 .data = &(struct meson_clk_pll_data){
1844 .en = {
1845 .reg_off = HHI_PCIE_PLL_CNTL0,
1846 .shift = 28,
1847 .width = 1,
1848 },
1849 .m = {
1850 .reg_off = HHI_PCIE_PLL_CNTL0,
1851 .shift = 0,
1852 .width = 8,
1853 },
1854 .n = {
1855 .reg_off = HHI_PCIE_PLL_CNTL0,
1856 .shift = 10,
1857 .width = 5,
1858 },
1859 .frac = {
1860 .reg_off = HHI_PCIE_PLL_CNTL1,
1861 .shift = 0,
1862 .width = 12,
1863 },
1864 .l = {
1865 .reg_off = HHI_PCIE_PLL_CNTL0,
1866 .shift = 31,
1867 .width = 1,
1868 },
1869 .rst = {
1870 .reg_off = HHI_PCIE_PLL_CNTL0,
1871 .shift = 29,
1872 .width = 1,
1873 },
1874 .table = g12a_pcie_pll_table,
1875 .init_regs = g12a_pcie_pll_init_regs,
1876 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1877 },
1878 .hw.init = &(struct clk_init_data){
1879 .name = "pcie_pll_dco",
1880 .ops = &meson_clk_pcie_pll_ops,
1881 .parent_data = &(const struct clk_parent_data) {
1882 .fw_name = "xtal",
1883 },
1884 .num_parents = 1,
1885 },
1886 };
1887
1888 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1889 .mult = 1,
1890 .div = 2,
1891 .hw.init = &(struct clk_init_data){
1892 .name = "pcie_pll_dco_div2",
1893 .ops = &clk_fixed_factor_ops,
1894 .parent_hws = (const struct clk_hw *[]) {
1895 &g12a_pcie_pll_dco.hw
1896 },
1897 .num_parents = 1,
1898 .flags = CLK_SET_RATE_PARENT,
1899 },
1900 };
1901
1902 static struct clk_regmap g12a_pcie_pll_od = {
1903 .data = &(struct clk_regmap_div_data){
1904 .offset = HHI_PCIE_PLL_CNTL0,
1905 .shift = 16,
1906 .width = 5,
1907 .flags = CLK_DIVIDER_ROUND_CLOSEST |
1908 CLK_DIVIDER_ONE_BASED |
1909 CLK_DIVIDER_ALLOW_ZERO,
1910 },
1911 .hw.init = &(struct clk_init_data){
1912 .name = "pcie_pll_od",
1913 .ops = &clk_regmap_divider_ops,
1914 .parent_hws = (const struct clk_hw *[]) {
1915 &g12a_pcie_pll_dco_div2.hw
1916 },
1917 .num_parents = 1,
1918 .flags = CLK_SET_RATE_PARENT,
1919 },
1920 };
1921
1922 static struct clk_fixed_factor g12a_pcie_pll = {
1923 .mult = 1,
1924 .div = 2,
1925 .hw.init = &(struct clk_init_data){
1926 .name = "pcie_pll_pll",
1927 .ops = &clk_fixed_factor_ops,
1928 .parent_hws = (const struct clk_hw *[]) {
1929 &g12a_pcie_pll_od.hw
1930 },
1931 .num_parents = 1,
1932 .flags = CLK_SET_RATE_PARENT,
1933 },
1934 };
1935
1936 static struct clk_regmap g12a_hdmi_pll_dco = {
1937 .data = &(struct meson_clk_pll_data){
1938 .en = {
1939 .reg_off = HHI_HDMI_PLL_CNTL0,
1940 .shift = 28,
1941 .width = 1,
1942 },
1943 .m = {
1944 .reg_off = HHI_HDMI_PLL_CNTL0,
1945 .shift = 0,
1946 .width = 8,
1947 },
1948 .n = {
1949 .reg_off = HHI_HDMI_PLL_CNTL0,
1950 .shift = 10,
1951 .width = 5,
1952 },
1953 .frac = {
1954 .reg_off = HHI_HDMI_PLL_CNTL1,
1955 .shift = 0,
1956 .width = 16,
1957 },
1958 .l = {
1959 .reg_off = HHI_HDMI_PLL_CNTL0,
1960 .shift = 30,
1961 .width = 1,
1962 },
1963 .rst = {
1964 .reg_off = HHI_HDMI_PLL_CNTL0,
1965 .shift = 29,
1966 .width = 1,
1967 },
1968 },
1969 .hw.init = &(struct clk_init_data){
1970 .name = "hdmi_pll_dco",
1971 .ops = &meson_clk_pll_ro_ops,
1972 .parent_data = &(const struct clk_parent_data) {
1973 .fw_name = "xtal",
1974 },
1975 .num_parents = 1,
1976
1977
1978
1979
1980 .flags = CLK_GET_RATE_NOCACHE,
1981 },
1982 };
1983
1984 static struct clk_regmap g12a_hdmi_pll_od = {
1985 .data = &(struct clk_regmap_div_data){
1986 .offset = HHI_HDMI_PLL_CNTL0,
1987 .shift = 16,
1988 .width = 2,
1989 .flags = CLK_DIVIDER_POWER_OF_TWO,
1990 },
1991 .hw.init = &(struct clk_init_data){
1992 .name = "hdmi_pll_od",
1993 .ops = &clk_regmap_divider_ro_ops,
1994 .parent_hws = (const struct clk_hw *[]) {
1995 &g12a_hdmi_pll_dco.hw
1996 },
1997 .num_parents = 1,
1998 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1999 },
2000 };
2001
2002 static struct clk_regmap g12a_hdmi_pll_od2 = {
2003 .data = &(struct clk_regmap_div_data){
2004 .offset = HHI_HDMI_PLL_CNTL0,
2005 .shift = 18,
2006 .width = 2,
2007 .flags = CLK_DIVIDER_POWER_OF_TWO,
2008 },
2009 .hw.init = &(struct clk_init_data){
2010 .name = "hdmi_pll_od2",
2011 .ops = &clk_regmap_divider_ro_ops,
2012 .parent_hws = (const struct clk_hw *[]) {
2013 &g12a_hdmi_pll_od.hw
2014 },
2015 .num_parents = 1,
2016 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2017 },
2018 };
2019
2020 static struct clk_regmap g12a_hdmi_pll = {
2021 .data = &(struct clk_regmap_div_data){
2022 .offset = HHI_HDMI_PLL_CNTL0,
2023 .shift = 20,
2024 .width = 2,
2025 .flags = CLK_DIVIDER_POWER_OF_TWO,
2026 },
2027 .hw.init = &(struct clk_init_data){
2028 .name = "hdmi_pll",
2029 .ops = &clk_regmap_divider_ro_ops,
2030 .parent_hws = (const struct clk_hw *[]) {
2031 &g12a_hdmi_pll_od2.hw
2032 },
2033 .num_parents = 1,
2034 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2035 },
2036 };
2037
2038 static struct clk_fixed_factor g12a_fclk_div4_div = {
2039 .mult = 1,
2040 .div = 4,
2041 .hw.init = &(struct clk_init_data){
2042 .name = "fclk_div4_div",
2043 .ops = &clk_fixed_factor_ops,
2044 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2045 .num_parents = 1,
2046 },
2047 };
2048
2049 static struct clk_regmap g12a_fclk_div4 = {
2050 .data = &(struct clk_regmap_gate_data){
2051 .offset = HHI_FIX_PLL_CNTL1,
2052 .bit_idx = 21,
2053 },
2054 .hw.init = &(struct clk_init_data){
2055 .name = "fclk_div4",
2056 .ops = &clk_regmap_gate_ops,
2057 .parent_hws = (const struct clk_hw *[]) {
2058 &g12a_fclk_div4_div.hw
2059 },
2060 .num_parents = 1,
2061 },
2062 };
2063
2064 static struct clk_fixed_factor g12a_fclk_div5_div = {
2065 .mult = 1,
2066 .div = 5,
2067 .hw.init = &(struct clk_init_data){
2068 .name = "fclk_div5_div",
2069 .ops = &clk_fixed_factor_ops,
2070 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2071 .num_parents = 1,
2072 },
2073 };
2074
2075 static struct clk_regmap g12a_fclk_div5 = {
2076 .data = &(struct clk_regmap_gate_data){
2077 .offset = HHI_FIX_PLL_CNTL1,
2078 .bit_idx = 22,
2079 },
2080 .hw.init = &(struct clk_init_data){
2081 .name = "fclk_div5",
2082 .ops = &clk_regmap_gate_ops,
2083 .parent_hws = (const struct clk_hw *[]) {
2084 &g12a_fclk_div5_div.hw
2085 },
2086 .num_parents = 1,
2087 },
2088 };
2089
2090 static struct clk_fixed_factor g12a_fclk_div7_div = {
2091 .mult = 1,
2092 .div = 7,
2093 .hw.init = &(struct clk_init_data){
2094 .name = "fclk_div7_div",
2095 .ops = &clk_fixed_factor_ops,
2096 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2097 .num_parents = 1,
2098 },
2099 };
2100
2101 static struct clk_regmap g12a_fclk_div7 = {
2102 .data = &(struct clk_regmap_gate_data){
2103 .offset = HHI_FIX_PLL_CNTL1,
2104 .bit_idx = 23,
2105 },
2106 .hw.init = &(struct clk_init_data){
2107 .name = "fclk_div7",
2108 .ops = &clk_regmap_gate_ops,
2109 .parent_hws = (const struct clk_hw *[]) {
2110 &g12a_fclk_div7_div.hw
2111 },
2112 .num_parents = 1,
2113 },
2114 };
2115
2116 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2117 .mult = 1,
2118 .div = 5,
2119 .hw.init = &(struct clk_init_data){
2120 .name = "fclk_div2p5_div",
2121 .ops = &clk_fixed_factor_ops,
2122 .parent_hws = (const struct clk_hw *[]) {
2123 &g12a_fixed_pll_dco.hw
2124 },
2125 .num_parents = 1,
2126 },
2127 };
2128
2129 static struct clk_regmap g12a_fclk_div2p5 = {
2130 .data = &(struct clk_regmap_gate_data){
2131 .offset = HHI_FIX_PLL_CNTL1,
2132 .bit_idx = 25,
2133 },
2134 .hw.init = &(struct clk_init_data){
2135 .name = "fclk_div2p5",
2136 .ops = &clk_regmap_gate_ops,
2137 .parent_hws = (const struct clk_hw *[]) {
2138 &g12a_fclk_div2p5_div.hw
2139 },
2140 .num_parents = 1,
2141 },
2142 };
2143
2144 static struct clk_fixed_factor g12a_mpll_50m_div = {
2145 .mult = 1,
2146 .div = 80,
2147 .hw.init = &(struct clk_init_data){
2148 .name = "mpll_50m_div",
2149 .ops = &clk_fixed_factor_ops,
2150 .parent_hws = (const struct clk_hw *[]) {
2151 &g12a_fixed_pll_dco.hw
2152 },
2153 .num_parents = 1,
2154 },
2155 };
2156
2157 static struct clk_regmap g12a_mpll_50m = {
2158 .data = &(struct clk_regmap_mux_data){
2159 .offset = HHI_FIX_PLL_CNTL3,
2160 .mask = 0x1,
2161 .shift = 5,
2162 },
2163 .hw.init = &(struct clk_init_data){
2164 .name = "mpll_50m",
2165 .ops = &clk_regmap_mux_ro_ops,
2166 .parent_data = (const struct clk_parent_data []) {
2167 { .fw_name = "xtal", },
2168 { .hw = &g12a_mpll_50m_div.hw },
2169 },
2170 .num_parents = 2,
2171 },
2172 };
2173
2174 static struct clk_fixed_factor g12a_mpll_prediv = {
2175 .mult = 1,
2176 .div = 2,
2177 .hw.init = &(struct clk_init_data){
2178 .name = "mpll_prediv",
2179 .ops = &clk_fixed_factor_ops,
2180 .parent_hws = (const struct clk_hw *[]) {
2181 &g12a_fixed_pll_dco.hw
2182 },
2183 .num_parents = 1,
2184 },
2185 };
2186
2187 static const struct reg_sequence g12a_mpll0_init_regs[] = {
2188 { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
2189 };
2190
2191 static struct clk_regmap g12a_mpll0_div = {
2192 .data = &(struct meson_clk_mpll_data){
2193 .sdm = {
2194 .reg_off = HHI_MPLL_CNTL1,
2195 .shift = 0,
2196 .width = 14,
2197 },
2198 .sdm_en = {
2199 .reg_off = HHI_MPLL_CNTL1,
2200 .shift = 30,
2201 .width = 1,
2202 },
2203 .n2 = {
2204 .reg_off = HHI_MPLL_CNTL1,
2205 .shift = 20,
2206 .width = 9,
2207 },
2208 .ssen = {
2209 .reg_off = HHI_MPLL_CNTL1,
2210 .shift = 29,
2211 .width = 1,
2212 },
2213 .lock = &meson_clk_lock,
2214 .init_regs = g12a_mpll0_init_regs,
2215 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2216 },
2217 .hw.init = &(struct clk_init_data){
2218 .name = "mpll0_div",
2219 .ops = &meson_clk_mpll_ops,
2220 .parent_hws = (const struct clk_hw *[]) {
2221 &g12a_mpll_prediv.hw
2222 },
2223 .num_parents = 1,
2224 },
2225 };
2226
2227 static struct clk_regmap g12a_mpll0 = {
2228 .data = &(struct clk_regmap_gate_data){
2229 .offset = HHI_MPLL_CNTL1,
2230 .bit_idx = 31,
2231 },
2232 .hw.init = &(struct clk_init_data){
2233 .name = "mpll0",
2234 .ops = &clk_regmap_gate_ops,
2235 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2236 .num_parents = 1,
2237 .flags = CLK_SET_RATE_PARENT,
2238 },
2239 };
2240
2241 static const struct reg_sequence g12a_mpll1_init_regs[] = {
2242 { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
2243 };
2244
2245 static struct clk_regmap g12a_mpll1_div = {
2246 .data = &(struct meson_clk_mpll_data){
2247 .sdm = {
2248 .reg_off = HHI_MPLL_CNTL3,
2249 .shift = 0,
2250 .width = 14,
2251 },
2252 .sdm_en = {
2253 .reg_off = HHI_MPLL_CNTL3,
2254 .shift = 30,
2255 .width = 1,
2256 },
2257 .n2 = {
2258 .reg_off = HHI_MPLL_CNTL3,
2259 .shift = 20,
2260 .width = 9,
2261 },
2262 .ssen = {
2263 .reg_off = HHI_MPLL_CNTL3,
2264 .shift = 29,
2265 .width = 1,
2266 },
2267 .lock = &meson_clk_lock,
2268 .init_regs = g12a_mpll1_init_regs,
2269 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2270 },
2271 .hw.init = &(struct clk_init_data){
2272 .name = "mpll1_div",
2273 .ops = &meson_clk_mpll_ops,
2274 .parent_hws = (const struct clk_hw *[]) {
2275 &g12a_mpll_prediv.hw
2276 },
2277 .num_parents = 1,
2278 },
2279 };
2280
2281 static struct clk_regmap g12a_mpll1 = {
2282 .data = &(struct clk_regmap_gate_data){
2283 .offset = HHI_MPLL_CNTL3,
2284 .bit_idx = 31,
2285 },
2286 .hw.init = &(struct clk_init_data){
2287 .name = "mpll1",
2288 .ops = &clk_regmap_gate_ops,
2289 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2290 .num_parents = 1,
2291 .flags = CLK_SET_RATE_PARENT,
2292 },
2293 };
2294
2295 static const struct reg_sequence g12a_mpll2_init_regs[] = {
2296 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
2297 };
2298
2299 static struct clk_regmap g12a_mpll2_div = {
2300 .data = &(struct meson_clk_mpll_data){
2301 .sdm = {
2302 .reg_off = HHI_MPLL_CNTL5,
2303 .shift = 0,
2304 .width = 14,
2305 },
2306 .sdm_en = {
2307 .reg_off = HHI_MPLL_CNTL5,
2308 .shift = 30,
2309 .width = 1,
2310 },
2311 .n2 = {
2312 .reg_off = HHI_MPLL_CNTL5,
2313 .shift = 20,
2314 .width = 9,
2315 },
2316 .ssen = {
2317 .reg_off = HHI_MPLL_CNTL5,
2318 .shift = 29,
2319 .width = 1,
2320 },
2321 .lock = &meson_clk_lock,
2322 .init_regs = g12a_mpll2_init_regs,
2323 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2324 },
2325 .hw.init = &(struct clk_init_data){
2326 .name = "mpll2_div",
2327 .ops = &meson_clk_mpll_ops,
2328 .parent_hws = (const struct clk_hw *[]) {
2329 &g12a_mpll_prediv.hw
2330 },
2331 .num_parents = 1,
2332 },
2333 };
2334
2335 static struct clk_regmap g12a_mpll2 = {
2336 .data = &(struct clk_regmap_gate_data){
2337 .offset = HHI_MPLL_CNTL5,
2338 .bit_idx = 31,
2339 },
2340 .hw.init = &(struct clk_init_data){
2341 .name = "mpll2",
2342 .ops = &clk_regmap_gate_ops,
2343 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2344 .num_parents = 1,
2345 .flags = CLK_SET_RATE_PARENT,
2346 },
2347 };
2348
2349 static const struct reg_sequence g12a_mpll3_init_regs[] = {
2350 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
2351 };
2352
2353 static struct clk_regmap g12a_mpll3_div = {
2354 .data = &(struct meson_clk_mpll_data){
2355 .sdm = {
2356 .reg_off = HHI_MPLL_CNTL7,
2357 .shift = 0,
2358 .width = 14,
2359 },
2360 .sdm_en = {
2361 .reg_off = HHI_MPLL_CNTL7,
2362 .shift = 30,
2363 .width = 1,
2364 },
2365 .n2 = {
2366 .reg_off = HHI_MPLL_CNTL7,
2367 .shift = 20,
2368 .width = 9,
2369 },
2370 .ssen = {
2371 .reg_off = HHI_MPLL_CNTL7,
2372 .shift = 29,
2373 .width = 1,
2374 },
2375 .lock = &meson_clk_lock,
2376 .init_regs = g12a_mpll3_init_regs,
2377 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2378 },
2379 .hw.init = &(struct clk_init_data){
2380 .name = "mpll3_div",
2381 .ops = &meson_clk_mpll_ops,
2382 .parent_hws = (const struct clk_hw *[]) {
2383 &g12a_mpll_prediv.hw
2384 },
2385 .num_parents = 1,
2386 },
2387 };
2388
2389 static struct clk_regmap g12a_mpll3 = {
2390 .data = &(struct clk_regmap_gate_data){
2391 .offset = HHI_MPLL_CNTL7,
2392 .bit_idx = 31,
2393 },
2394 .hw.init = &(struct clk_init_data){
2395 .name = "mpll3",
2396 .ops = &clk_regmap_gate_ops,
2397 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2398 .num_parents = 1,
2399 .flags = CLK_SET_RATE_PARENT,
2400 },
2401 };
2402
2403 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
2404 static const struct clk_parent_data clk81_parent_data[] = {
2405 { .fw_name = "xtal", },
2406 { .hw = &g12a_fclk_div7.hw },
2407 { .hw = &g12a_mpll1.hw },
2408 { .hw = &g12a_mpll2.hw },
2409 { .hw = &g12a_fclk_div4.hw },
2410 { .hw = &g12a_fclk_div3.hw },
2411 { .hw = &g12a_fclk_div5.hw },
2412 };
2413
2414 static struct clk_regmap g12a_mpeg_clk_sel = {
2415 .data = &(struct clk_regmap_mux_data){
2416 .offset = HHI_MPEG_CLK_CNTL,
2417 .mask = 0x7,
2418 .shift = 12,
2419 .table = mux_table_clk81,
2420 },
2421 .hw.init = &(struct clk_init_data){
2422 .name = "mpeg_clk_sel",
2423 .ops = &clk_regmap_mux_ro_ops,
2424 .parent_data = clk81_parent_data,
2425 .num_parents = ARRAY_SIZE(clk81_parent_data),
2426 },
2427 };
2428
2429 static struct clk_regmap g12a_mpeg_clk_div = {
2430 .data = &(struct clk_regmap_div_data){
2431 .offset = HHI_MPEG_CLK_CNTL,
2432 .shift = 0,
2433 .width = 7,
2434 },
2435 .hw.init = &(struct clk_init_data){
2436 .name = "mpeg_clk_div",
2437 .ops = &clk_regmap_divider_ops,
2438 .parent_hws = (const struct clk_hw *[]) {
2439 &g12a_mpeg_clk_sel.hw
2440 },
2441 .num_parents = 1,
2442 .flags = CLK_SET_RATE_PARENT,
2443 },
2444 };
2445
2446 static struct clk_regmap g12a_clk81 = {
2447 .data = &(struct clk_regmap_gate_data){
2448 .offset = HHI_MPEG_CLK_CNTL,
2449 .bit_idx = 7,
2450 },
2451 .hw.init = &(struct clk_init_data){
2452 .name = "clk81",
2453 .ops = &clk_regmap_gate_ops,
2454 .parent_hws = (const struct clk_hw *[]) {
2455 &g12a_mpeg_clk_div.hw
2456 },
2457 .num_parents = 1,
2458 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2459 },
2460 };
2461
2462 static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2463 { .fw_name = "xtal", },
2464 { .hw = &g12a_fclk_div2.hw },
2465 { .hw = &g12a_fclk_div3.hw },
2466 { .hw = &g12a_fclk_div5.hw },
2467 { .hw = &g12a_fclk_div7.hw },
2468
2469
2470
2471
2472
2473
2474 };
2475
2476
2477 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2478 .data = &(struct clk_regmap_mux_data){
2479 .offset = HHI_SD_EMMC_CLK_CNTL,
2480 .mask = 0x7,
2481 .shift = 9,
2482 },
2483 .hw.init = &(struct clk_init_data) {
2484 .name = "sd_emmc_a_clk0_sel",
2485 .ops = &clk_regmap_mux_ops,
2486 .parent_data = g12a_sd_emmc_clk0_parent_data,
2487 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2488 .flags = CLK_SET_RATE_PARENT,
2489 },
2490 };
2491
2492 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2493 .data = &(struct clk_regmap_div_data){
2494 .offset = HHI_SD_EMMC_CLK_CNTL,
2495 .shift = 0,
2496 .width = 7,
2497 },
2498 .hw.init = &(struct clk_init_data) {
2499 .name = "sd_emmc_a_clk0_div",
2500 .ops = &clk_regmap_divider_ops,
2501 .parent_hws = (const struct clk_hw *[]) {
2502 &g12a_sd_emmc_a_clk0_sel.hw
2503 },
2504 .num_parents = 1,
2505 .flags = CLK_SET_RATE_PARENT,
2506 },
2507 };
2508
2509 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2510 .data = &(struct clk_regmap_gate_data){
2511 .offset = HHI_SD_EMMC_CLK_CNTL,
2512 .bit_idx = 7,
2513 },
2514 .hw.init = &(struct clk_init_data){
2515 .name = "sd_emmc_a_clk0",
2516 .ops = &clk_regmap_gate_ops,
2517 .parent_hws = (const struct clk_hw *[]) {
2518 &g12a_sd_emmc_a_clk0_div.hw
2519 },
2520 .num_parents = 1,
2521 .flags = CLK_SET_RATE_PARENT,
2522 },
2523 };
2524
2525
2526 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2527 .data = &(struct clk_regmap_mux_data){
2528 .offset = HHI_SD_EMMC_CLK_CNTL,
2529 .mask = 0x7,
2530 .shift = 25,
2531 },
2532 .hw.init = &(struct clk_init_data) {
2533 .name = "sd_emmc_b_clk0_sel",
2534 .ops = &clk_regmap_mux_ops,
2535 .parent_data = g12a_sd_emmc_clk0_parent_data,
2536 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2537 .flags = CLK_SET_RATE_PARENT,
2538 },
2539 };
2540
2541 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2542 .data = &(struct clk_regmap_div_data){
2543 .offset = HHI_SD_EMMC_CLK_CNTL,
2544 .shift = 16,
2545 .width = 7,
2546 },
2547 .hw.init = &(struct clk_init_data) {
2548 .name = "sd_emmc_b_clk0_div",
2549 .ops = &clk_regmap_divider_ops,
2550 .parent_hws = (const struct clk_hw *[]) {
2551 &g12a_sd_emmc_b_clk0_sel.hw
2552 },
2553 .num_parents = 1,
2554 .flags = CLK_SET_RATE_PARENT,
2555 },
2556 };
2557
2558 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2559 .data = &(struct clk_regmap_gate_data){
2560 .offset = HHI_SD_EMMC_CLK_CNTL,
2561 .bit_idx = 23,
2562 },
2563 .hw.init = &(struct clk_init_data){
2564 .name = "sd_emmc_b_clk0",
2565 .ops = &clk_regmap_gate_ops,
2566 .parent_hws = (const struct clk_hw *[]) {
2567 &g12a_sd_emmc_b_clk0_div.hw
2568 },
2569 .num_parents = 1,
2570 .flags = CLK_SET_RATE_PARENT,
2571 },
2572 };
2573
2574
2575 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2576 .data = &(struct clk_regmap_mux_data){
2577 .offset = HHI_NAND_CLK_CNTL,
2578 .mask = 0x7,
2579 .shift = 9,
2580 },
2581 .hw.init = &(struct clk_init_data) {
2582 .name = "sd_emmc_c_clk0_sel",
2583 .ops = &clk_regmap_mux_ops,
2584 .parent_data = g12a_sd_emmc_clk0_parent_data,
2585 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2586 .flags = CLK_SET_RATE_PARENT,
2587 },
2588 };
2589
2590 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2591 .data = &(struct clk_regmap_div_data){
2592 .offset = HHI_NAND_CLK_CNTL,
2593 .shift = 0,
2594 .width = 7,
2595 },
2596 .hw.init = &(struct clk_init_data) {
2597 .name = "sd_emmc_c_clk0_div",
2598 .ops = &clk_regmap_divider_ops,
2599 .parent_hws = (const struct clk_hw *[]) {
2600 &g12a_sd_emmc_c_clk0_sel.hw
2601 },
2602 .num_parents = 1,
2603 .flags = CLK_SET_RATE_PARENT,
2604 },
2605 };
2606
2607 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2608 .data = &(struct clk_regmap_gate_data){
2609 .offset = HHI_NAND_CLK_CNTL,
2610 .bit_idx = 7,
2611 },
2612 .hw.init = &(struct clk_init_data){
2613 .name = "sd_emmc_c_clk0",
2614 .ops = &clk_regmap_gate_ops,
2615 .parent_hws = (const struct clk_hw *[]) {
2616 &g12a_sd_emmc_c_clk0_div.hw
2617 },
2618 .num_parents = 1,
2619 .flags = CLK_SET_RATE_PARENT,
2620 },
2621 };
2622
2623
2624
2625 static struct clk_regmap g12a_vid_pll_div = {
2626 .data = &(struct meson_vid_pll_div_data){
2627 .val = {
2628 .reg_off = HHI_VID_PLL_CLK_DIV,
2629 .shift = 0,
2630 .width = 15,
2631 },
2632 .sel = {
2633 .reg_off = HHI_VID_PLL_CLK_DIV,
2634 .shift = 16,
2635 .width = 2,
2636 },
2637 },
2638 .hw.init = &(struct clk_init_data) {
2639 .name = "vid_pll_div",
2640 .ops = &meson_vid_pll_div_ro_ops,
2641 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2642 .num_parents = 1,
2643 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2644 },
2645 };
2646
2647 static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2648 &g12a_vid_pll_div.hw,
2649 &g12a_hdmi_pll.hw,
2650 };
2651
2652 static struct clk_regmap g12a_vid_pll_sel = {
2653 .data = &(struct clk_regmap_mux_data){
2654 .offset = HHI_VID_PLL_CLK_DIV,
2655 .mask = 0x1,
2656 .shift = 18,
2657 },
2658 .hw.init = &(struct clk_init_data){
2659 .name = "vid_pll_sel",
2660 .ops = &clk_regmap_mux_ops,
2661
2662
2663
2664
2665 .parent_hws = g12a_vid_pll_parent_hws,
2666 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2667 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2668 },
2669 };
2670
2671 static struct clk_regmap g12a_vid_pll = {
2672 .data = &(struct clk_regmap_gate_data){
2673 .offset = HHI_VID_PLL_CLK_DIV,
2674 .bit_idx = 19,
2675 },
2676 .hw.init = &(struct clk_init_data) {
2677 .name = "vid_pll",
2678 .ops = &clk_regmap_gate_ops,
2679 .parent_hws = (const struct clk_hw *[]) {
2680 &g12a_vid_pll_sel.hw
2681 },
2682 .num_parents = 1,
2683 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2684 },
2685 };
2686
2687
2688
2689 static const struct clk_hw *g12a_vpu_parent_hws[] = {
2690 &g12a_fclk_div3.hw,
2691 &g12a_fclk_div4.hw,
2692 &g12a_fclk_div5.hw,
2693 &g12a_fclk_div7.hw,
2694 &g12a_mpll1.hw,
2695 &g12a_vid_pll.hw,
2696 &g12a_hifi_pll.hw,
2697 &g12a_gp0_pll.hw,
2698 };
2699
2700 static struct clk_regmap g12a_vpu_0_sel = {
2701 .data = &(struct clk_regmap_mux_data){
2702 .offset = HHI_VPU_CLK_CNTL,
2703 .mask = 0x7,
2704 .shift = 9,
2705 },
2706 .hw.init = &(struct clk_init_data){
2707 .name = "vpu_0_sel",
2708 .ops = &clk_regmap_mux_ops,
2709 .parent_hws = g12a_vpu_parent_hws,
2710 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2711 .flags = CLK_SET_RATE_NO_REPARENT,
2712 },
2713 };
2714
2715 static struct clk_regmap g12a_vpu_0_div = {
2716 .data = &(struct clk_regmap_div_data){
2717 .offset = HHI_VPU_CLK_CNTL,
2718 .shift = 0,
2719 .width = 7,
2720 },
2721 .hw.init = &(struct clk_init_data){
2722 .name = "vpu_0_div",
2723 .ops = &clk_regmap_divider_ops,
2724 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2725 .num_parents = 1,
2726 .flags = CLK_SET_RATE_PARENT,
2727 },
2728 };
2729
2730 static struct clk_regmap g12a_vpu_0 = {
2731 .data = &(struct clk_regmap_gate_data){
2732 .offset = HHI_VPU_CLK_CNTL,
2733 .bit_idx = 8,
2734 },
2735 .hw.init = &(struct clk_init_data) {
2736 .name = "vpu_0",
2737 .ops = &clk_regmap_gate_ops,
2738 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2739 .num_parents = 1,
2740 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2741 },
2742 };
2743
2744 static struct clk_regmap g12a_vpu_1_sel = {
2745 .data = &(struct clk_regmap_mux_data){
2746 .offset = HHI_VPU_CLK_CNTL,
2747 .mask = 0x7,
2748 .shift = 25,
2749 },
2750 .hw.init = &(struct clk_init_data){
2751 .name = "vpu_1_sel",
2752 .ops = &clk_regmap_mux_ops,
2753 .parent_hws = g12a_vpu_parent_hws,
2754 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2755 .flags = CLK_SET_RATE_NO_REPARENT,
2756 },
2757 };
2758
2759 static struct clk_regmap g12a_vpu_1_div = {
2760 .data = &(struct clk_regmap_div_data){
2761 .offset = HHI_VPU_CLK_CNTL,
2762 .shift = 16,
2763 .width = 7,
2764 },
2765 .hw.init = &(struct clk_init_data){
2766 .name = "vpu_1_div",
2767 .ops = &clk_regmap_divider_ops,
2768 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2769 .num_parents = 1,
2770 .flags = CLK_SET_RATE_PARENT,
2771 },
2772 };
2773
2774 static struct clk_regmap g12a_vpu_1 = {
2775 .data = &(struct clk_regmap_gate_data){
2776 .offset = HHI_VPU_CLK_CNTL,
2777 .bit_idx = 24,
2778 },
2779 .hw.init = &(struct clk_init_data) {
2780 .name = "vpu_1",
2781 .ops = &clk_regmap_gate_ops,
2782 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2783 .num_parents = 1,
2784 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2785 },
2786 };
2787
2788 static struct clk_regmap g12a_vpu = {
2789 .data = &(struct clk_regmap_mux_data){
2790 .offset = HHI_VPU_CLK_CNTL,
2791 .mask = 1,
2792 .shift = 31,
2793 },
2794 .hw.init = &(struct clk_init_data){
2795 .name = "vpu",
2796 .ops = &clk_regmap_mux_ops,
2797
2798
2799
2800
2801 .parent_hws = (const struct clk_hw *[]) {
2802 &g12a_vpu_0.hw,
2803 &g12a_vpu_1.hw,
2804 },
2805 .num_parents = 2,
2806 .flags = CLK_SET_RATE_NO_REPARENT,
2807 },
2808 };
2809
2810
2811
2812 static const struct clk_hw *g12a_vdec_parent_hws[] = {
2813 &g12a_fclk_div2p5.hw,
2814 &g12a_fclk_div3.hw,
2815 &g12a_fclk_div4.hw,
2816 &g12a_fclk_div5.hw,
2817 &g12a_fclk_div7.hw,
2818 &g12a_hifi_pll.hw,
2819 &g12a_gp0_pll.hw,
2820 };
2821
2822 static struct clk_regmap g12a_vdec_1_sel = {
2823 .data = &(struct clk_regmap_mux_data){
2824 .offset = HHI_VDEC_CLK_CNTL,
2825 .mask = 0x7,
2826 .shift = 9,
2827 .flags = CLK_MUX_ROUND_CLOSEST,
2828 },
2829 .hw.init = &(struct clk_init_data){
2830 .name = "vdec_1_sel",
2831 .ops = &clk_regmap_mux_ops,
2832 .parent_hws = g12a_vdec_parent_hws,
2833 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2834 .flags = CLK_SET_RATE_PARENT,
2835 },
2836 };
2837
2838 static struct clk_regmap g12a_vdec_1_div = {
2839 .data = &(struct clk_regmap_div_data){
2840 .offset = HHI_VDEC_CLK_CNTL,
2841 .shift = 0,
2842 .width = 7,
2843 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2844 },
2845 .hw.init = &(struct clk_init_data){
2846 .name = "vdec_1_div",
2847 .ops = &clk_regmap_divider_ops,
2848 .parent_hws = (const struct clk_hw *[]) {
2849 &g12a_vdec_1_sel.hw
2850 },
2851 .num_parents = 1,
2852 .flags = CLK_SET_RATE_PARENT,
2853 },
2854 };
2855
2856 static struct clk_regmap g12a_vdec_1 = {
2857 .data = &(struct clk_regmap_gate_data){
2858 .offset = HHI_VDEC_CLK_CNTL,
2859 .bit_idx = 8,
2860 },
2861 .hw.init = &(struct clk_init_data) {
2862 .name = "vdec_1",
2863 .ops = &clk_regmap_gate_ops,
2864 .parent_hws = (const struct clk_hw *[]) {
2865 &g12a_vdec_1_div.hw
2866 },
2867 .num_parents = 1,
2868 .flags = CLK_SET_RATE_PARENT,
2869 },
2870 };
2871
2872 static struct clk_regmap g12a_vdec_hevcf_sel = {
2873 .data = &(struct clk_regmap_mux_data){
2874 .offset = HHI_VDEC2_CLK_CNTL,
2875 .mask = 0x7,
2876 .shift = 9,
2877 .flags = CLK_MUX_ROUND_CLOSEST,
2878 },
2879 .hw.init = &(struct clk_init_data){
2880 .name = "vdec_hevcf_sel",
2881 .ops = &clk_regmap_mux_ops,
2882 .parent_hws = g12a_vdec_parent_hws,
2883 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2884 .flags = CLK_SET_RATE_PARENT,
2885 },
2886 };
2887
2888 static struct clk_regmap g12a_vdec_hevcf_div = {
2889 .data = &(struct clk_regmap_div_data){
2890 .offset = HHI_VDEC2_CLK_CNTL,
2891 .shift = 0,
2892 .width = 7,
2893 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2894 },
2895 .hw.init = &(struct clk_init_data){
2896 .name = "vdec_hevcf_div",
2897 .ops = &clk_regmap_divider_ops,
2898 .parent_hws = (const struct clk_hw *[]) {
2899 &g12a_vdec_hevcf_sel.hw
2900 },
2901 .num_parents = 1,
2902 .flags = CLK_SET_RATE_PARENT,
2903 },
2904 };
2905
2906 static struct clk_regmap g12a_vdec_hevcf = {
2907 .data = &(struct clk_regmap_gate_data){
2908 .offset = HHI_VDEC2_CLK_CNTL,
2909 .bit_idx = 8,
2910 },
2911 .hw.init = &(struct clk_init_data) {
2912 .name = "vdec_hevcf",
2913 .ops = &clk_regmap_gate_ops,
2914 .parent_hws = (const struct clk_hw *[]) {
2915 &g12a_vdec_hevcf_div.hw
2916 },
2917 .num_parents = 1,
2918 .flags = CLK_SET_RATE_PARENT,
2919 },
2920 };
2921
2922 static struct clk_regmap g12a_vdec_hevc_sel = {
2923 .data = &(struct clk_regmap_mux_data){
2924 .offset = HHI_VDEC2_CLK_CNTL,
2925 .mask = 0x7,
2926 .shift = 25,
2927 .flags = CLK_MUX_ROUND_CLOSEST,
2928 },
2929 .hw.init = &(struct clk_init_data){
2930 .name = "vdec_hevc_sel",
2931 .ops = &clk_regmap_mux_ops,
2932 .parent_hws = g12a_vdec_parent_hws,
2933 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2934 .flags = CLK_SET_RATE_PARENT,
2935 },
2936 };
2937
2938 static struct clk_regmap g12a_vdec_hevc_div = {
2939 .data = &(struct clk_regmap_div_data){
2940 .offset = HHI_VDEC2_CLK_CNTL,
2941 .shift = 16,
2942 .width = 7,
2943 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2944 },
2945 .hw.init = &(struct clk_init_data){
2946 .name = "vdec_hevc_div",
2947 .ops = &clk_regmap_divider_ops,
2948 .parent_hws = (const struct clk_hw *[]) {
2949 &g12a_vdec_hevc_sel.hw
2950 },
2951 .num_parents = 1,
2952 .flags = CLK_SET_RATE_PARENT,
2953 },
2954 };
2955
2956 static struct clk_regmap g12a_vdec_hevc = {
2957 .data = &(struct clk_regmap_gate_data){
2958 .offset = HHI_VDEC2_CLK_CNTL,
2959 .bit_idx = 24,
2960 },
2961 .hw.init = &(struct clk_init_data) {
2962 .name = "vdec_hevc",
2963 .ops = &clk_regmap_gate_ops,
2964 .parent_hws = (const struct clk_hw *[]) {
2965 &g12a_vdec_hevc_div.hw
2966 },
2967 .num_parents = 1,
2968 .flags = CLK_SET_RATE_PARENT,
2969 },
2970 };
2971
2972
2973
2974 static const struct clk_hw *g12a_vapb_parent_hws[] = {
2975 &g12a_fclk_div4.hw,
2976 &g12a_fclk_div3.hw,
2977 &g12a_fclk_div5.hw,
2978 &g12a_fclk_div7.hw,
2979 &g12a_mpll1.hw,
2980 &g12a_vid_pll.hw,
2981 &g12a_mpll2.hw,
2982 &g12a_fclk_div2p5.hw,
2983 };
2984
2985 static struct clk_regmap g12a_vapb_0_sel = {
2986 .data = &(struct clk_regmap_mux_data){
2987 .offset = HHI_VAPBCLK_CNTL,
2988 .mask = 0x3,
2989 .shift = 9,
2990 },
2991 .hw.init = &(struct clk_init_data){
2992 .name = "vapb_0_sel",
2993 .ops = &clk_regmap_mux_ops,
2994 .parent_hws = g12a_vapb_parent_hws,
2995 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2996 .flags = CLK_SET_RATE_NO_REPARENT,
2997 },
2998 };
2999
3000 static struct clk_regmap g12a_vapb_0_div = {
3001 .data = &(struct clk_regmap_div_data){
3002 .offset = HHI_VAPBCLK_CNTL,
3003 .shift = 0,
3004 .width = 7,
3005 },
3006 .hw.init = &(struct clk_init_data){
3007 .name = "vapb_0_div",
3008 .ops = &clk_regmap_divider_ops,
3009 .parent_hws = (const struct clk_hw *[]) {
3010 &g12a_vapb_0_sel.hw
3011 },
3012 .num_parents = 1,
3013 .flags = CLK_SET_RATE_PARENT,
3014 },
3015 };
3016
3017 static struct clk_regmap g12a_vapb_0 = {
3018 .data = &(struct clk_regmap_gate_data){
3019 .offset = HHI_VAPBCLK_CNTL,
3020 .bit_idx = 8,
3021 },
3022 .hw.init = &(struct clk_init_data) {
3023 .name = "vapb_0",
3024 .ops = &clk_regmap_gate_ops,
3025 .parent_hws = (const struct clk_hw *[]) {
3026 &g12a_vapb_0_div.hw
3027 },
3028 .num_parents = 1,
3029 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3030 },
3031 };
3032
3033 static struct clk_regmap g12a_vapb_1_sel = {
3034 .data = &(struct clk_regmap_mux_data){
3035 .offset = HHI_VAPBCLK_CNTL,
3036 .mask = 0x3,
3037 .shift = 25,
3038 },
3039 .hw.init = &(struct clk_init_data){
3040 .name = "vapb_1_sel",
3041 .ops = &clk_regmap_mux_ops,
3042 .parent_hws = g12a_vapb_parent_hws,
3043 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3044 .flags = CLK_SET_RATE_NO_REPARENT,
3045 },
3046 };
3047
3048 static struct clk_regmap g12a_vapb_1_div = {
3049 .data = &(struct clk_regmap_div_data){
3050 .offset = HHI_VAPBCLK_CNTL,
3051 .shift = 16,
3052 .width = 7,
3053 },
3054 .hw.init = &(struct clk_init_data){
3055 .name = "vapb_1_div",
3056 .ops = &clk_regmap_divider_ops,
3057 .parent_hws = (const struct clk_hw *[]) {
3058 &g12a_vapb_1_sel.hw
3059 },
3060 .num_parents = 1,
3061 .flags = CLK_SET_RATE_PARENT,
3062 },
3063 };
3064
3065 static struct clk_regmap g12a_vapb_1 = {
3066 .data = &(struct clk_regmap_gate_data){
3067 .offset = HHI_VAPBCLK_CNTL,
3068 .bit_idx = 24,
3069 },
3070 .hw.init = &(struct clk_init_data) {
3071 .name = "vapb_1",
3072 .ops = &clk_regmap_gate_ops,
3073 .parent_hws = (const struct clk_hw *[]) {
3074 &g12a_vapb_1_div.hw
3075 },
3076 .num_parents = 1,
3077 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3078 },
3079 };
3080
3081 static struct clk_regmap g12a_vapb_sel = {
3082 .data = &(struct clk_regmap_mux_data){
3083 .offset = HHI_VAPBCLK_CNTL,
3084 .mask = 1,
3085 .shift = 31,
3086 },
3087 .hw.init = &(struct clk_init_data){
3088 .name = "vapb_sel",
3089 .ops = &clk_regmap_mux_ops,
3090
3091
3092
3093
3094 .parent_hws = (const struct clk_hw *[]) {
3095 &g12a_vapb_0.hw,
3096 &g12a_vapb_1.hw,
3097 },
3098 .num_parents = 2,
3099 .flags = CLK_SET_RATE_NO_REPARENT,
3100 },
3101 };
3102
3103 static struct clk_regmap g12a_vapb = {
3104 .data = &(struct clk_regmap_gate_data){
3105 .offset = HHI_VAPBCLK_CNTL,
3106 .bit_idx = 30,
3107 },
3108 .hw.init = &(struct clk_init_data) {
3109 .name = "vapb",
3110 .ops = &clk_regmap_gate_ops,
3111 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3112 .num_parents = 1,
3113 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3114 },
3115 };
3116
3117 static const struct clk_hw *g12a_vclk_parent_hws[] = {
3118 &g12a_vid_pll.hw,
3119 &g12a_gp0_pll.hw,
3120 &g12a_hifi_pll.hw,
3121 &g12a_mpll1.hw,
3122 &g12a_fclk_div3.hw,
3123 &g12a_fclk_div4.hw,
3124 &g12a_fclk_div5.hw,
3125 &g12a_fclk_div7.hw,
3126 };
3127
3128 static struct clk_regmap g12a_vclk_sel = {
3129 .data = &(struct clk_regmap_mux_data){
3130 .offset = HHI_VID_CLK_CNTL,
3131 .mask = 0x7,
3132 .shift = 16,
3133 },
3134 .hw.init = &(struct clk_init_data){
3135 .name = "vclk_sel",
3136 .ops = &clk_regmap_mux_ops,
3137 .parent_hws = g12a_vclk_parent_hws,
3138 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3139 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3140 },
3141 };
3142
3143 static struct clk_regmap g12a_vclk2_sel = {
3144 .data = &(struct clk_regmap_mux_data){
3145 .offset = HHI_VIID_CLK_CNTL,
3146 .mask = 0x7,
3147 .shift = 16,
3148 },
3149 .hw.init = &(struct clk_init_data){
3150 .name = "vclk2_sel",
3151 .ops = &clk_regmap_mux_ops,
3152 .parent_hws = g12a_vclk_parent_hws,
3153 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3154 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3155 },
3156 };
3157
3158 static struct clk_regmap g12a_vclk_input = {
3159 .data = &(struct clk_regmap_gate_data){
3160 .offset = HHI_VID_CLK_DIV,
3161 .bit_idx = 16,
3162 },
3163 .hw.init = &(struct clk_init_data) {
3164 .name = "vclk_input",
3165 .ops = &clk_regmap_gate_ops,
3166 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3167 .num_parents = 1,
3168 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3169 },
3170 };
3171
3172 static struct clk_regmap g12a_vclk2_input = {
3173 .data = &(struct clk_regmap_gate_data){
3174 .offset = HHI_VIID_CLK_DIV,
3175 .bit_idx = 16,
3176 },
3177 .hw.init = &(struct clk_init_data) {
3178 .name = "vclk2_input",
3179 .ops = &clk_regmap_gate_ops,
3180 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3181 .num_parents = 1,
3182 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3183 },
3184 };
3185
3186 static struct clk_regmap g12a_vclk_div = {
3187 .data = &(struct clk_regmap_div_data){
3188 .offset = HHI_VID_CLK_DIV,
3189 .shift = 0,
3190 .width = 8,
3191 },
3192 .hw.init = &(struct clk_init_data){
3193 .name = "vclk_div",
3194 .ops = &clk_regmap_divider_ops,
3195 .parent_hws = (const struct clk_hw *[]) {
3196 &g12a_vclk_input.hw
3197 },
3198 .num_parents = 1,
3199 .flags = CLK_GET_RATE_NOCACHE,
3200 },
3201 };
3202
3203 static struct clk_regmap g12a_vclk2_div = {
3204 .data = &(struct clk_regmap_div_data){
3205 .offset = HHI_VIID_CLK_DIV,
3206 .shift = 0,
3207 .width = 8,
3208 },
3209 .hw.init = &(struct clk_init_data){
3210 .name = "vclk2_div",
3211 .ops = &clk_regmap_divider_ops,
3212 .parent_hws = (const struct clk_hw *[]) {
3213 &g12a_vclk2_input.hw
3214 },
3215 .num_parents = 1,
3216 .flags = CLK_GET_RATE_NOCACHE,
3217 },
3218 };
3219
3220 static struct clk_regmap g12a_vclk = {
3221 .data = &(struct clk_regmap_gate_data){
3222 .offset = HHI_VID_CLK_CNTL,
3223 .bit_idx = 19,
3224 },
3225 .hw.init = &(struct clk_init_data) {
3226 .name = "vclk",
3227 .ops = &clk_regmap_gate_ops,
3228 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3229 .num_parents = 1,
3230 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3231 },
3232 };
3233
3234 static struct clk_regmap g12a_vclk2 = {
3235 .data = &(struct clk_regmap_gate_data){
3236 .offset = HHI_VIID_CLK_CNTL,
3237 .bit_idx = 19,
3238 },
3239 .hw.init = &(struct clk_init_data) {
3240 .name = "vclk2",
3241 .ops = &clk_regmap_gate_ops,
3242 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3243 .num_parents = 1,
3244 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3245 },
3246 };
3247
3248 static struct clk_regmap g12a_vclk_div1 = {
3249 .data = &(struct clk_regmap_gate_data){
3250 .offset = HHI_VID_CLK_CNTL,
3251 .bit_idx = 0,
3252 },
3253 .hw.init = &(struct clk_init_data) {
3254 .name = "vclk_div1",
3255 .ops = &clk_regmap_gate_ops,
3256 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3257 .num_parents = 1,
3258 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3259 },
3260 };
3261
3262 static struct clk_regmap g12a_vclk_div2_en = {
3263 .data = &(struct clk_regmap_gate_data){
3264 .offset = HHI_VID_CLK_CNTL,
3265 .bit_idx = 1,
3266 },
3267 .hw.init = &(struct clk_init_data) {
3268 .name = "vclk_div2_en",
3269 .ops = &clk_regmap_gate_ops,
3270 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3271 .num_parents = 1,
3272 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3273 },
3274 };
3275
3276 static struct clk_regmap g12a_vclk_div4_en = {
3277 .data = &(struct clk_regmap_gate_data){
3278 .offset = HHI_VID_CLK_CNTL,
3279 .bit_idx = 2,
3280 },
3281 .hw.init = &(struct clk_init_data) {
3282 .name = "vclk_div4_en",
3283 .ops = &clk_regmap_gate_ops,
3284 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3285 .num_parents = 1,
3286 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3287 },
3288 };
3289
3290 static struct clk_regmap g12a_vclk_div6_en = {
3291 .data = &(struct clk_regmap_gate_data){
3292 .offset = HHI_VID_CLK_CNTL,
3293 .bit_idx = 3,
3294 },
3295 .hw.init = &(struct clk_init_data) {
3296 .name = "vclk_div6_en",
3297 .ops = &clk_regmap_gate_ops,
3298 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3299 .num_parents = 1,
3300 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3301 },
3302 };
3303
3304 static struct clk_regmap g12a_vclk_div12_en = {
3305 .data = &(struct clk_regmap_gate_data){
3306 .offset = HHI_VID_CLK_CNTL,
3307 .bit_idx = 4,
3308 },
3309 .hw.init = &(struct clk_init_data) {
3310 .name = "vclk_div12_en",
3311 .ops = &clk_regmap_gate_ops,
3312 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3313 .num_parents = 1,
3314 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3315 },
3316 };
3317
3318 static struct clk_regmap g12a_vclk2_div1 = {
3319 .data = &(struct clk_regmap_gate_data){
3320 .offset = HHI_VIID_CLK_CNTL,
3321 .bit_idx = 0,
3322 },
3323 .hw.init = &(struct clk_init_data) {
3324 .name = "vclk2_div1",
3325 .ops = &clk_regmap_gate_ops,
3326 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3327 .num_parents = 1,
3328 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3329 },
3330 };
3331
3332 static struct clk_regmap g12a_vclk2_div2_en = {
3333 .data = &(struct clk_regmap_gate_data){
3334 .offset = HHI_VIID_CLK_CNTL,
3335 .bit_idx = 1,
3336 },
3337 .hw.init = &(struct clk_init_data) {
3338 .name = "vclk2_div2_en",
3339 .ops = &clk_regmap_gate_ops,
3340 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3341 .num_parents = 1,
3342 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3343 },
3344 };
3345
3346 static struct clk_regmap g12a_vclk2_div4_en = {
3347 .data = &(struct clk_regmap_gate_data){
3348 .offset = HHI_VIID_CLK_CNTL,
3349 .bit_idx = 2,
3350 },
3351 .hw.init = &(struct clk_init_data) {
3352 .name = "vclk2_div4_en",
3353 .ops = &clk_regmap_gate_ops,
3354 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3355 .num_parents = 1,
3356 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3357 },
3358 };
3359
3360 static struct clk_regmap g12a_vclk2_div6_en = {
3361 .data = &(struct clk_regmap_gate_data){
3362 .offset = HHI_VIID_CLK_CNTL,
3363 .bit_idx = 3,
3364 },
3365 .hw.init = &(struct clk_init_data) {
3366 .name = "vclk2_div6_en",
3367 .ops = &clk_regmap_gate_ops,
3368 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3369 .num_parents = 1,
3370 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3371 },
3372 };
3373
3374 static struct clk_regmap g12a_vclk2_div12_en = {
3375 .data = &(struct clk_regmap_gate_data){
3376 .offset = HHI_VIID_CLK_CNTL,
3377 .bit_idx = 4,
3378 },
3379 .hw.init = &(struct clk_init_data) {
3380 .name = "vclk2_div12_en",
3381 .ops = &clk_regmap_gate_ops,
3382 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3383 .num_parents = 1,
3384 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3385 },
3386 };
3387
3388 static struct clk_fixed_factor g12a_vclk_div2 = {
3389 .mult = 1,
3390 .div = 2,
3391 .hw.init = &(struct clk_init_data){
3392 .name = "vclk_div2",
3393 .ops = &clk_fixed_factor_ops,
3394 .parent_hws = (const struct clk_hw *[]) {
3395 &g12a_vclk_div2_en.hw
3396 },
3397 .num_parents = 1,
3398 },
3399 };
3400
3401 static struct clk_fixed_factor g12a_vclk_div4 = {
3402 .mult = 1,
3403 .div = 4,
3404 .hw.init = &(struct clk_init_data){
3405 .name = "vclk_div4",
3406 .ops = &clk_fixed_factor_ops,
3407 .parent_hws = (const struct clk_hw *[]) {
3408 &g12a_vclk_div4_en.hw
3409 },
3410 .num_parents = 1,
3411 },
3412 };
3413
3414 static struct clk_fixed_factor g12a_vclk_div6 = {
3415 .mult = 1,
3416 .div = 6,
3417 .hw.init = &(struct clk_init_data){
3418 .name = "vclk_div6",
3419 .ops = &clk_fixed_factor_ops,
3420 .parent_hws = (const struct clk_hw *[]) {
3421 &g12a_vclk_div6_en.hw
3422 },
3423 .num_parents = 1,
3424 },
3425 };
3426
3427 static struct clk_fixed_factor g12a_vclk_div12 = {
3428 .mult = 1,
3429 .div = 12,
3430 .hw.init = &(struct clk_init_data){
3431 .name = "vclk_div12",
3432 .ops = &clk_fixed_factor_ops,
3433 .parent_hws = (const struct clk_hw *[]) {
3434 &g12a_vclk_div12_en.hw
3435 },
3436 .num_parents = 1,
3437 },
3438 };
3439
3440 static struct clk_fixed_factor g12a_vclk2_div2 = {
3441 .mult = 1,
3442 .div = 2,
3443 .hw.init = &(struct clk_init_data){
3444 .name = "vclk2_div2",
3445 .ops = &clk_fixed_factor_ops,
3446 .parent_hws = (const struct clk_hw *[]) {
3447 &g12a_vclk2_div2_en.hw
3448 },
3449 .num_parents = 1,
3450 },
3451 };
3452
3453 static struct clk_fixed_factor g12a_vclk2_div4 = {
3454 .mult = 1,
3455 .div = 4,
3456 .hw.init = &(struct clk_init_data){
3457 .name = "vclk2_div4",
3458 .ops = &clk_fixed_factor_ops,
3459 .parent_hws = (const struct clk_hw *[]) {
3460 &g12a_vclk2_div4_en.hw
3461 },
3462 .num_parents = 1,
3463 },
3464 };
3465
3466 static struct clk_fixed_factor g12a_vclk2_div6 = {
3467 .mult = 1,
3468 .div = 6,
3469 .hw.init = &(struct clk_init_data){
3470 .name = "vclk2_div6",
3471 .ops = &clk_fixed_factor_ops,
3472 .parent_hws = (const struct clk_hw *[]) {
3473 &g12a_vclk2_div6_en.hw
3474 },
3475 .num_parents = 1,
3476 },
3477 };
3478
3479 static struct clk_fixed_factor g12a_vclk2_div12 = {
3480 .mult = 1,
3481 .div = 12,
3482 .hw.init = &(struct clk_init_data){
3483 .name = "vclk2_div12",
3484 .ops = &clk_fixed_factor_ops,
3485 .parent_hws = (const struct clk_hw *[]) {
3486 &g12a_vclk2_div12_en.hw
3487 },
3488 .num_parents = 1,
3489 },
3490 };
3491
3492 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3493 static const struct clk_hw *g12a_cts_parent_hws[] = {
3494 &g12a_vclk_div1.hw,
3495 &g12a_vclk_div2.hw,
3496 &g12a_vclk_div4.hw,
3497 &g12a_vclk_div6.hw,
3498 &g12a_vclk_div12.hw,
3499 &g12a_vclk2_div1.hw,
3500 &g12a_vclk2_div2.hw,
3501 &g12a_vclk2_div4.hw,
3502 &g12a_vclk2_div6.hw,
3503 &g12a_vclk2_div12.hw,
3504 };
3505
3506 static struct clk_regmap g12a_cts_enci_sel = {
3507 .data = &(struct clk_regmap_mux_data){
3508 .offset = HHI_VID_CLK_DIV,
3509 .mask = 0xf,
3510 .shift = 28,
3511 .table = mux_table_cts_sel,
3512 },
3513 .hw.init = &(struct clk_init_data){
3514 .name = "cts_enci_sel",
3515 .ops = &clk_regmap_mux_ops,
3516 .parent_hws = g12a_cts_parent_hws,
3517 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3518 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3519 },
3520 };
3521
3522 static struct clk_regmap g12a_cts_encp_sel = {
3523 .data = &(struct clk_regmap_mux_data){
3524 .offset = HHI_VID_CLK_DIV,
3525 .mask = 0xf,
3526 .shift = 20,
3527 .table = mux_table_cts_sel,
3528 },
3529 .hw.init = &(struct clk_init_data){
3530 .name = "cts_encp_sel",
3531 .ops = &clk_regmap_mux_ops,
3532 .parent_hws = g12a_cts_parent_hws,
3533 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3534 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3535 },
3536 };
3537
3538 static struct clk_regmap g12a_cts_vdac_sel = {
3539 .data = &(struct clk_regmap_mux_data){
3540 .offset = HHI_VIID_CLK_DIV,
3541 .mask = 0xf,
3542 .shift = 28,
3543 .table = mux_table_cts_sel,
3544 },
3545 .hw.init = &(struct clk_init_data){
3546 .name = "cts_vdac_sel",
3547 .ops = &clk_regmap_mux_ops,
3548 .parent_hws = g12a_cts_parent_hws,
3549 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3550 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3551 },
3552 };
3553
3554
3555 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3556 static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3557 &g12a_vclk_div1.hw,
3558 &g12a_vclk_div2.hw,
3559 &g12a_vclk_div4.hw,
3560 &g12a_vclk_div6.hw,
3561 &g12a_vclk_div12.hw,
3562 &g12a_vclk2_div1.hw,
3563 &g12a_vclk2_div2.hw,
3564 &g12a_vclk2_div4.hw,
3565 &g12a_vclk2_div6.hw,
3566 &g12a_vclk2_div12.hw,
3567 };
3568
3569 static struct clk_regmap g12a_hdmi_tx_sel = {
3570 .data = &(struct clk_regmap_mux_data){
3571 .offset = HHI_HDMI_CLK_CNTL,
3572 .mask = 0xf,
3573 .shift = 16,
3574 .table = mux_table_hdmi_tx_sel,
3575 },
3576 .hw.init = &(struct clk_init_data){
3577 .name = "hdmi_tx_sel",
3578 .ops = &clk_regmap_mux_ops,
3579 .parent_hws = g12a_cts_hdmi_tx_parent_hws,
3580 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3581 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3582 },
3583 };
3584
3585 static struct clk_regmap g12a_cts_enci = {
3586 .data = &(struct clk_regmap_gate_data){
3587 .offset = HHI_VID_CLK_CNTL2,
3588 .bit_idx = 0,
3589 },
3590 .hw.init = &(struct clk_init_data) {
3591 .name = "cts_enci",
3592 .ops = &clk_regmap_gate_ops,
3593 .parent_hws = (const struct clk_hw *[]) {
3594 &g12a_cts_enci_sel.hw
3595 },
3596 .num_parents = 1,
3597 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3598 },
3599 };
3600
3601 static struct clk_regmap g12a_cts_encp = {
3602 .data = &(struct clk_regmap_gate_data){
3603 .offset = HHI_VID_CLK_CNTL2,
3604 .bit_idx = 2,
3605 },
3606 .hw.init = &(struct clk_init_data) {
3607 .name = "cts_encp",
3608 .ops = &clk_regmap_gate_ops,
3609 .parent_hws = (const struct clk_hw *[]) {
3610 &g12a_cts_encp_sel.hw
3611 },
3612 .num_parents = 1,
3613 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3614 },
3615 };
3616
3617 static struct clk_regmap g12a_cts_vdac = {
3618 .data = &(struct clk_regmap_gate_data){
3619 .offset = HHI_VID_CLK_CNTL2,
3620 .bit_idx = 4,
3621 },
3622 .hw.init = &(struct clk_init_data) {
3623 .name = "cts_vdac",
3624 .ops = &clk_regmap_gate_ops,
3625 .parent_hws = (const struct clk_hw *[]) {
3626 &g12a_cts_vdac_sel.hw
3627 },
3628 .num_parents = 1,
3629 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3630 },
3631 };
3632
3633 static struct clk_regmap g12a_hdmi_tx = {
3634 .data = &(struct clk_regmap_gate_data){
3635 .offset = HHI_VID_CLK_CNTL2,
3636 .bit_idx = 5,
3637 },
3638 .hw.init = &(struct clk_init_data) {
3639 .name = "hdmi_tx",
3640 .ops = &clk_regmap_gate_ops,
3641 .parent_hws = (const struct clk_hw *[]) {
3642 &g12a_hdmi_tx_sel.hw
3643 },
3644 .num_parents = 1,
3645 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3646 },
3647 };
3648
3649
3650
3651 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3652 { .fw_name = "xtal", },
3653 { .hw = &g12a_fclk_div4.hw },
3654 { .hw = &g12a_fclk_div3.hw },
3655 { .hw = &g12a_fclk_div5.hw },
3656 };
3657
3658 static struct clk_regmap g12a_hdmi_sel = {
3659 .data = &(struct clk_regmap_mux_data){
3660 .offset = HHI_HDMI_CLK_CNTL,
3661 .mask = 0x3,
3662 .shift = 9,
3663 .flags = CLK_MUX_ROUND_CLOSEST,
3664 },
3665 .hw.init = &(struct clk_init_data){
3666 .name = "hdmi_sel",
3667 .ops = &clk_regmap_mux_ops,
3668 .parent_data = g12a_hdmi_parent_data,
3669 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3670 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3671 },
3672 };
3673
3674 static struct clk_regmap g12a_hdmi_div = {
3675 .data = &(struct clk_regmap_div_data){
3676 .offset = HHI_HDMI_CLK_CNTL,
3677 .shift = 0,
3678 .width = 7,
3679 },
3680 .hw.init = &(struct clk_init_data){
3681 .name = "hdmi_div",
3682 .ops = &clk_regmap_divider_ops,
3683 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3684 .num_parents = 1,
3685 .flags = CLK_GET_RATE_NOCACHE,
3686 },
3687 };
3688
3689 static struct clk_regmap g12a_hdmi = {
3690 .data = &(struct clk_regmap_gate_data){
3691 .offset = HHI_HDMI_CLK_CNTL,
3692 .bit_idx = 8,
3693 },
3694 .hw.init = &(struct clk_init_data) {
3695 .name = "hdmi",
3696 .ops = &clk_regmap_gate_ops,
3697 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3698 .num_parents = 1,
3699 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3700 },
3701 };
3702
3703
3704
3705
3706
3707 static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3708 { .fw_name = "xtal", },
3709 { .hw = &g12a_gp0_pll.hw },
3710 { .hw = &g12a_hifi_pll.hw },
3711 { .hw = &g12a_fclk_div2p5.hw },
3712 { .hw = &g12a_fclk_div3.hw },
3713 { .hw = &g12a_fclk_div4.hw },
3714 { .hw = &g12a_fclk_div5.hw },
3715 { .hw = &g12a_fclk_div7.hw },
3716 };
3717
3718 static struct clk_regmap g12a_mali_0_sel = {
3719 .data = &(struct clk_regmap_mux_data){
3720 .offset = HHI_MALI_CLK_CNTL,
3721 .mask = 0x7,
3722 .shift = 9,
3723 },
3724 .hw.init = &(struct clk_init_data){
3725 .name = "mali_0_sel",
3726 .ops = &clk_regmap_mux_ops,
3727 .parent_data = g12a_mali_0_1_parent_data,
3728 .num_parents = 8,
3729 .flags = CLK_SET_RATE_NO_REPARENT,
3730 },
3731 };
3732
3733 static struct clk_regmap g12a_mali_0_div = {
3734 .data = &(struct clk_regmap_div_data){
3735 .offset = HHI_MALI_CLK_CNTL,
3736 .shift = 0,
3737 .width = 7,
3738 },
3739 .hw.init = &(struct clk_init_data){
3740 .name = "mali_0_div",
3741 .ops = &clk_regmap_divider_ops,
3742 .parent_hws = (const struct clk_hw *[]) {
3743 &g12a_mali_0_sel.hw
3744 },
3745 .num_parents = 1,
3746 .flags = CLK_SET_RATE_NO_REPARENT,
3747 },
3748 };
3749
3750 static struct clk_regmap g12a_mali_0 = {
3751 .data = &(struct clk_regmap_gate_data){
3752 .offset = HHI_MALI_CLK_CNTL,
3753 .bit_idx = 8,
3754 },
3755 .hw.init = &(struct clk_init_data){
3756 .name = "mali_0",
3757 .ops = &clk_regmap_gate_ops,
3758 .parent_hws = (const struct clk_hw *[]) {
3759 &g12a_mali_0_div.hw
3760 },
3761 .num_parents = 1,
3762 .flags = CLK_SET_RATE_PARENT,
3763 },
3764 };
3765
3766 static struct clk_regmap g12a_mali_1_sel = {
3767 .data = &(struct clk_regmap_mux_data){
3768 .offset = HHI_MALI_CLK_CNTL,
3769 .mask = 0x7,
3770 .shift = 25,
3771 },
3772 .hw.init = &(struct clk_init_data){
3773 .name = "mali_1_sel",
3774 .ops = &clk_regmap_mux_ops,
3775 .parent_data = g12a_mali_0_1_parent_data,
3776 .num_parents = 8,
3777 .flags = CLK_SET_RATE_NO_REPARENT,
3778 },
3779 };
3780
3781 static struct clk_regmap g12a_mali_1_div = {
3782 .data = &(struct clk_regmap_div_data){
3783 .offset = HHI_MALI_CLK_CNTL,
3784 .shift = 16,
3785 .width = 7,
3786 },
3787 .hw.init = &(struct clk_init_data){
3788 .name = "mali_1_div",
3789 .ops = &clk_regmap_divider_ops,
3790 .parent_hws = (const struct clk_hw *[]) {
3791 &g12a_mali_1_sel.hw
3792 },
3793 .num_parents = 1,
3794 .flags = CLK_SET_RATE_NO_REPARENT,
3795 },
3796 };
3797
3798 static struct clk_regmap g12a_mali_1 = {
3799 .data = &(struct clk_regmap_gate_data){
3800 .offset = HHI_MALI_CLK_CNTL,
3801 .bit_idx = 24,
3802 },
3803 .hw.init = &(struct clk_init_data){
3804 .name = "mali_1",
3805 .ops = &clk_regmap_gate_ops,
3806 .parent_hws = (const struct clk_hw *[]) {
3807 &g12a_mali_1_div.hw
3808 },
3809 .num_parents = 1,
3810 .flags = CLK_SET_RATE_PARENT,
3811 },
3812 };
3813
3814 static const struct clk_hw *g12a_mali_parent_hws[] = {
3815 &g12a_mali_0.hw,
3816 &g12a_mali_1.hw,
3817 };
3818
3819 static struct clk_regmap g12a_mali = {
3820 .data = &(struct clk_regmap_mux_data){
3821 .offset = HHI_MALI_CLK_CNTL,
3822 .mask = 1,
3823 .shift = 31,
3824 },
3825 .hw.init = &(struct clk_init_data){
3826 .name = "mali",
3827 .ops = &clk_regmap_mux_ops,
3828 .parent_hws = g12a_mali_parent_hws,
3829 .num_parents = 2,
3830 .flags = CLK_SET_RATE_NO_REPARENT,
3831 },
3832 };
3833
3834 static struct clk_regmap g12a_ts_div = {
3835 .data = &(struct clk_regmap_div_data){
3836 .offset = HHI_TS_CLK_CNTL,
3837 .shift = 0,
3838 .width = 8,
3839 },
3840 .hw.init = &(struct clk_init_data){
3841 .name = "ts_div",
3842 .ops = &clk_regmap_divider_ro_ops,
3843 .parent_data = &(const struct clk_parent_data) {
3844 .fw_name = "xtal",
3845 },
3846 .num_parents = 1,
3847 },
3848 };
3849
3850 static struct clk_regmap g12a_ts = {
3851 .data = &(struct clk_regmap_gate_data){
3852 .offset = HHI_TS_CLK_CNTL,
3853 .bit_idx = 8,
3854 },
3855 .hw.init = &(struct clk_init_data){
3856 .name = "ts",
3857 .ops = &clk_regmap_gate_ops,
3858 .parent_hws = (const struct clk_hw *[]) {
3859 &g12a_ts_div.hw
3860 },
3861 .num_parents = 1,
3862 },
3863 };
3864
3865 #define MESON_GATE(_name, _reg, _bit) \
3866 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
3867
3868 #define MESON_GATE_RO(_name, _reg, _bit) \
3869 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
3870
3871
3872 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
3873 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
3874 static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
3875 static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
3876 static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
3877 static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
3878 static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
3879 static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
3880 static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
3881 static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
3882 static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
3883 static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
3884 static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
3885 static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
3886 static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
3887 static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
3888 static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
3889 static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
3890 static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);
3891 static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
3892 static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
3893 static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
3894
3895 static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
3896 static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
3897 static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
3898 static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
3899 static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
3900 static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
3901 static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
3902 static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
3903 static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
3904 static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
3905 static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
3906 static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
3907 static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
3908
3909 static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
3910 static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
3911 static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
3912 static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
3913 static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
3914 static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
3915 static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
3916 static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
3917 static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
3918 static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
3919
3920 static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
3921 static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
3922 static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
3923 static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
3924 static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
3925 static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
3926 static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
3927 static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
3928 static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
3929 static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
3930 static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
3931 static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
3932 static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
3933 static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
3934 static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
3935 static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
3936 static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
3937 static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
3938 static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
3939
3940 static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
3941 static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
3942 static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
3943 static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
3944 static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
3945
3946
3947 static struct clk_hw_onecell_data g12a_hw_onecell_data = {
3948 .hws = {
3949 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
3950 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
3951 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
3952 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
3953 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
3954 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
3955 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
3956 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
3957 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
3958 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
3959 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
3960 [CLKID_CLK81] = &g12a_clk81.hw,
3961 [CLKID_MPLL0] = &g12a_mpll0.hw,
3962 [CLKID_MPLL1] = &g12a_mpll1.hw,
3963 [CLKID_MPLL2] = &g12a_mpll2.hw,
3964 [CLKID_MPLL3] = &g12a_mpll3.hw,
3965 [CLKID_DDR] = &g12a_ddr.hw,
3966 [CLKID_DOS] = &g12a_dos.hw,
3967 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
3968 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
3969 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
3970 [CLKID_ISA] = &g12a_isa.hw,
3971 [CLKID_PL301] = &g12a_pl301.hw,
3972 [CLKID_PERIPHS] = &g12a_periphs.hw,
3973 [CLKID_SPICC0] = &g12a_spicc_0.hw,
3974 [CLKID_I2C] = &g12a_i2c.hw,
3975 [CLKID_SANA] = &g12a_sana.hw,
3976 [CLKID_SD] = &g12a_sd.hw,
3977 [CLKID_RNG0] = &g12a_rng0.hw,
3978 [CLKID_UART0] = &g12a_uart0.hw,
3979 [CLKID_SPICC1] = &g12a_spicc_1.hw,
3980 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
3981 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
3982 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
3983 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
3984 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
3985 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
3986 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
3987 [CLKID_AUDIO] = &g12a_audio.hw,
3988 [CLKID_ETH] = &g12a_eth_core.hw,
3989 [CLKID_DEMUX] = &g12a_demux.hw,
3990 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
3991 [CLKID_ADC] = &g12a_adc.hw,
3992 [CLKID_UART1] = &g12a_uart1.hw,
3993 [CLKID_G2D] = &g12a_g2d.hw,
3994 [CLKID_RESET] = &g12a_reset.hw,
3995 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
3996 [CLKID_PARSER] = &g12a_parser.hw,
3997 [CLKID_USB] = &g12a_usb_general.hw,
3998 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
3999 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4000 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4001 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4002 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4003 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4004 [CLKID_BT656] = &g12a_bt656.hw,
4005 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4006 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4007 [CLKID_UART2] = &g12a_uart2.hw,
4008 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4009 [CLKID_GIC] = &g12a_gic.hw,
4010 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4011 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4012 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4013 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4014 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4015 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4016 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4017 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4018 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4019 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4020 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4021 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4022 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4023 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4024 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4025 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4026 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4027 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4028 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4029 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4030 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4031 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4032 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4033 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4034 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4035 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4036 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4037 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4038 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4039 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4040 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4041 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4042 [CLKID_ENC480P] = &g12a_enc480p.hw,
4043 [CLKID_RNG1] = &g12a_rng1.hw,
4044 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4045 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4046 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4047 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4048 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4049 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4050 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4051 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4052 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4053 [CLKID_DMA] = &g12a_dma.hw,
4054 [CLKID_EFUSE] = &g12a_efuse.hw,
4055 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4056 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4057 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4058 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4059 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4060 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4061 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4062 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4063 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4064 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4065 [CLKID_VPU] = &g12a_vpu.hw,
4066 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4067 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4068 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4069 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4070 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4071 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4072 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4073 [CLKID_VAPB] = &g12a_vapb.hw,
4074 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4075 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4076 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4077 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4078 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4079 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4080 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4081 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4082 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4083 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4084 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4085 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4086 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4087 [CLKID_VCLK] = &g12a_vclk.hw,
4088 [CLKID_VCLK2] = &g12a_vclk2.hw,
4089 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4090 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4091 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4092 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4093 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4094 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4095 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4096 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4097 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4098 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4099 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4100 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4101 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4102 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4103 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4104 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4105 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4106 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4107 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4108 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4109 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4110 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4111 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4112 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4113 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4114 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4115 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4116 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4117 [CLKID_HDMI] = &g12a_hdmi.hw,
4118 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4119 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4120 [CLKID_MALI_0] = &g12a_mali_0.hw,
4121 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4122 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4123 [CLKID_MALI_1] = &g12a_mali_1.hw,
4124 [CLKID_MALI] = &g12a_mali.hw,
4125 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4126 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4127 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4128 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4129 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4130 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4131 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4132 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4133 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4134 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4135 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4136 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4137 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4138 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4139 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4140 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4141 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4142 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4143 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4144 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4145 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4146 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4147 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4148 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4149 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4150 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4151 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4152 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4153 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4154 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4155 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4156 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4157 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4158 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4159 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4160 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4161 [CLKID_TS] = &g12a_ts.hw,
4162 [NR_CLKS] = NULL,
4163 },
4164 .num = NR_CLKS,
4165 };
4166
4167 static struct clk_hw_onecell_data g12b_hw_onecell_data = {
4168 .hws = {
4169 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4170 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4171 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4172 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4173 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4174 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4175 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4176 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4177 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4178 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4179 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4180 [CLKID_CLK81] = &g12a_clk81.hw,
4181 [CLKID_MPLL0] = &g12a_mpll0.hw,
4182 [CLKID_MPLL1] = &g12a_mpll1.hw,
4183 [CLKID_MPLL2] = &g12a_mpll2.hw,
4184 [CLKID_MPLL3] = &g12a_mpll3.hw,
4185 [CLKID_DDR] = &g12a_ddr.hw,
4186 [CLKID_DOS] = &g12a_dos.hw,
4187 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4188 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4189 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4190 [CLKID_ISA] = &g12a_isa.hw,
4191 [CLKID_PL301] = &g12a_pl301.hw,
4192 [CLKID_PERIPHS] = &g12a_periphs.hw,
4193 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4194 [CLKID_I2C] = &g12a_i2c.hw,
4195 [CLKID_SANA] = &g12a_sana.hw,
4196 [CLKID_SD] = &g12a_sd.hw,
4197 [CLKID_RNG0] = &g12a_rng0.hw,
4198 [CLKID_UART0] = &g12a_uart0.hw,
4199 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4200 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4201 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4202 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4203 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4204 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4205 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4206 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4207 [CLKID_AUDIO] = &g12a_audio.hw,
4208 [CLKID_ETH] = &g12a_eth_core.hw,
4209 [CLKID_DEMUX] = &g12a_demux.hw,
4210 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4211 [CLKID_ADC] = &g12a_adc.hw,
4212 [CLKID_UART1] = &g12a_uart1.hw,
4213 [CLKID_G2D] = &g12a_g2d.hw,
4214 [CLKID_RESET] = &g12a_reset.hw,
4215 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4216 [CLKID_PARSER] = &g12a_parser.hw,
4217 [CLKID_USB] = &g12a_usb_general.hw,
4218 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4219 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4220 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4221 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4222 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4223 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4224 [CLKID_BT656] = &g12a_bt656.hw,
4225 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4226 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4227 [CLKID_UART2] = &g12a_uart2.hw,
4228 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4229 [CLKID_GIC] = &g12a_gic.hw,
4230 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4231 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4232 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4233 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4234 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4235 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4236 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4237 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4238 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4239 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4240 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4241 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4242 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4243 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4244 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4245 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4246 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4247 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4248 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4249 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4250 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4251 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4252 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4253 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4254 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4255 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4256 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4257 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4258 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4259 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4260 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4261 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4262 [CLKID_ENC480P] = &g12a_enc480p.hw,
4263 [CLKID_RNG1] = &g12a_rng1.hw,
4264 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4265 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4266 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4267 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4268 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4269 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4270 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4271 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4272 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4273 [CLKID_DMA] = &g12a_dma.hw,
4274 [CLKID_EFUSE] = &g12a_efuse.hw,
4275 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4276 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4277 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4278 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4279 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4280 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4281 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4282 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4283 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4284 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4285 [CLKID_VPU] = &g12a_vpu.hw,
4286 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4287 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4288 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4289 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4290 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4291 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4292 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4293 [CLKID_VAPB] = &g12a_vapb.hw,
4294 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4295 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4296 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4297 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4298 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4299 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4300 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4301 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4302 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4303 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4304 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4305 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4306 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4307 [CLKID_VCLK] = &g12a_vclk.hw,
4308 [CLKID_VCLK2] = &g12a_vclk2.hw,
4309 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4310 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4311 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4312 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4313 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4314 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4315 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4316 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4317 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4318 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4319 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4320 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4321 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4322 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4323 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4324 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4325 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4326 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4327 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4328 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4329 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4330 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4331 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4332 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4333 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4334 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4335 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4336 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4337 [CLKID_HDMI] = &g12a_hdmi.hw,
4338 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4339 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4340 [CLKID_MALI_0] = &g12a_mali_0.hw,
4341 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4342 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4343 [CLKID_MALI_1] = &g12a_mali_1.hw,
4344 [CLKID_MALI] = &g12a_mali.hw,
4345 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4346 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4347 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4348 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4349 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4350 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4351 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4352 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4353 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4354 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4355 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4356 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4357 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4358 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4359 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4360 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4361 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4362 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4363 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4364 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4365 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4366 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4367 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4368 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4369 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4370 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4371 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4372 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4373 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4374 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4375 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4376 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4377 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4378 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4379 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4380 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4381 [CLKID_TS] = &g12a_ts.hw,
4382 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4383 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4384 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4385 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4386 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4387 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4388 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4389 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4390 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4391 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4392 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4393 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4394 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4395 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4396 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4397 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4398 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4399 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4400 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4401 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4402 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4403 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4404 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4405 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4406 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4407 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4408 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4409 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4410 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4411 [NR_CLKS] = NULL,
4412 },
4413 .num = NR_CLKS,
4414 };
4415
4416 static struct clk_hw_onecell_data sm1_hw_onecell_data = {
4417 .hws = {
4418 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4419 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4420 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4421 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4422 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4423 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4424 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4425 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4426 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4427 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4428 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4429 [CLKID_CLK81] = &g12a_clk81.hw,
4430 [CLKID_MPLL0] = &g12a_mpll0.hw,
4431 [CLKID_MPLL1] = &g12a_mpll1.hw,
4432 [CLKID_MPLL2] = &g12a_mpll2.hw,
4433 [CLKID_MPLL3] = &g12a_mpll3.hw,
4434 [CLKID_DDR] = &g12a_ddr.hw,
4435 [CLKID_DOS] = &g12a_dos.hw,
4436 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4437 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4438 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4439 [CLKID_ISA] = &g12a_isa.hw,
4440 [CLKID_PL301] = &g12a_pl301.hw,
4441 [CLKID_PERIPHS] = &g12a_periphs.hw,
4442 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4443 [CLKID_I2C] = &g12a_i2c.hw,
4444 [CLKID_SANA] = &g12a_sana.hw,
4445 [CLKID_SD] = &g12a_sd.hw,
4446 [CLKID_RNG0] = &g12a_rng0.hw,
4447 [CLKID_UART0] = &g12a_uart0.hw,
4448 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4449 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4450 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4451 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4452 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4453 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4454 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4455 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4456 [CLKID_AUDIO] = &g12a_audio.hw,
4457 [CLKID_ETH] = &g12a_eth_core.hw,
4458 [CLKID_DEMUX] = &g12a_demux.hw,
4459 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4460 [CLKID_ADC] = &g12a_adc.hw,
4461 [CLKID_UART1] = &g12a_uart1.hw,
4462 [CLKID_G2D] = &g12a_g2d.hw,
4463 [CLKID_RESET] = &g12a_reset.hw,
4464 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4465 [CLKID_PARSER] = &g12a_parser.hw,
4466 [CLKID_USB] = &g12a_usb_general.hw,
4467 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4468 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4469 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4470 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4471 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4472 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4473 [CLKID_BT656] = &g12a_bt656.hw,
4474 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4475 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4476 [CLKID_UART2] = &g12a_uart2.hw,
4477 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4478 [CLKID_GIC] = &g12a_gic.hw,
4479 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4480 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4481 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4482 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4483 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4484 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4485 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4486 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4487 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4488 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4489 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4490 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4491 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4492 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4493 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4494 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4495 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4496 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4497 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4498 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4499 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4500 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4501 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4502 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4503 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4504 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4505 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4506 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4507 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4508 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4509 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4510 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4511 [CLKID_ENC480P] = &g12a_enc480p.hw,
4512 [CLKID_RNG1] = &g12a_rng1.hw,
4513 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4514 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4515 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4516 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4517 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4518 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4519 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4520 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4521 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4522 [CLKID_DMA] = &g12a_dma.hw,
4523 [CLKID_EFUSE] = &g12a_efuse.hw,
4524 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4525 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4526 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4527 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4528 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4529 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4530 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4531 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4532 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4533 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4534 [CLKID_VPU] = &g12a_vpu.hw,
4535 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4536 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4537 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4538 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4539 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4540 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4541 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4542 [CLKID_VAPB] = &g12a_vapb.hw,
4543 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4544 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4545 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4546 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4547 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4548 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4549 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4550 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4551 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4552 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4553 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4554 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4555 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4556 [CLKID_VCLK] = &g12a_vclk.hw,
4557 [CLKID_VCLK2] = &g12a_vclk2.hw,
4558 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4559 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4560 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4561 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4562 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4563 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4564 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4565 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4566 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4567 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4568 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4569 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4570 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4571 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4572 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4573 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4574 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4575 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4576 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4577 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4578 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4579 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4580 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4581 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4582 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4583 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4584 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4585 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4586 [CLKID_HDMI] = &g12a_hdmi.hw,
4587 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4588 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4589 [CLKID_MALI_0] = &g12a_mali_0.hw,
4590 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4591 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4592 [CLKID_MALI_1] = &g12a_mali_1.hw,
4593 [CLKID_MALI] = &g12a_mali.hw,
4594 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4595 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4596 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4597 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4598 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4599 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4600 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4601 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4602 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4603 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4604 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4605 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4606 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4607 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4608 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4609 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4610 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4611 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4612 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4613 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4614 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4615 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4616 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4617 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4618 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4619 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4620 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4621 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4622 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4623 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4624 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4625 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4626 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4627 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4628 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4629 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4630 [CLKID_TS] = &g12a_ts.hw,
4631 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4632 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4633 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4634 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4635 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4636 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4637 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4638 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4639 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4640 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4641 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4642 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4643 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4644 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4645 [NR_CLKS] = NULL,
4646 },
4647 .num = NR_CLKS,
4648 };
4649
4650
4651 static struct clk_regmap *const g12a_clk_regmaps[] = {
4652 &g12a_clk81,
4653 &g12a_dos,
4654 &g12a_ddr,
4655 &g12a_audio_locker,
4656 &g12a_mipi_dsi_host,
4657 &g12a_eth_phy,
4658 &g12a_isa,
4659 &g12a_pl301,
4660 &g12a_periphs,
4661 &g12a_spicc_0,
4662 &g12a_i2c,
4663 &g12a_sana,
4664 &g12a_sd,
4665 &g12a_rng0,
4666 &g12a_uart0,
4667 &g12a_spicc_1,
4668 &g12a_hiu_reg,
4669 &g12a_mipi_dsi_phy,
4670 &g12a_assist_misc,
4671 &g12a_emmc_a,
4672 &g12a_emmc_b,
4673 &g12a_emmc_c,
4674 &g12a_audio_codec,
4675 &g12a_audio,
4676 &g12a_eth_core,
4677 &g12a_demux,
4678 &g12a_audio_ififo,
4679 &g12a_adc,
4680 &g12a_uart1,
4681 &g12a_g2d,
4682 &g12a_reset,
4683 &g12a_pcie_comb,
4684 &g12a_parser,
4685 &g12a_usb_general,
4686 &g12a_pcie_phy,
4687 &g12a_ahb_arb0,
4688 &g12a_ahb_data_bus,
4689 &g12a_ahb_ctrl_bus,
4690 &g12a_htx_hdcp22,
4691 &g12a_htx_pclk,
4692 &g12a_bt656,
4693 &g12a_usb1_to_ddr,
4694 &g12a_mmc_pclk,
4695 &g12a_uart2,
4696 &g12a_vpu_intr,
4697 &g12a_gic,
4698 &g12a_sd_emmc_a_clk0,
4699 &g12a_sd_emmc_b_clk0,
4700 &g12a_sd_emmc_c_clk0,
4701 &g12a_mpeg_clk_div,
4702 &g12a_sd_emmc_a_clk0_div,
4703 &g12a_sd_emmc_b_clk0_div,
4704 &g12a_sd_emmc_c_clk0_div,
4705 &g12a_mpeg_clk_sel,
4706 &g12a_sd_emmc_a_clk0_sel,
4707 &g12a_sd_emmc_b_clk0_sel,
4708 &g12a_sd_emmc_c_clk0_sel,
4709 &g12a_mpll0,
4710 &g12a_mpll1,
4711 &g12a_mpll2,
4712 &g12a_mpll3,
4713 &g12a_mpll0_div,
4714 &g12a_mpll1_div,
4715 &g12a_mpll2_div,
4716 &g12a_mpll3_div,
4717 &g12a_fixed_pll,
4718 &g12a_sys_pll,
4719 &g12a_gp0_pll,
4720 &g12a_hifi_pll,
4721 &g12a_vclk2_venci0,
4722 &g12a_vclk2_venci1,
4723 &g12a_vclk2_vencp0,
4724 &g12a_vclk2_vencp1,
4725 &g12a_vclk2_venct0,
4726 &g12a_vclk2_venct1,
4727 &g12a_vclk2_other,
4728 &g12a_vclk2_enci,
4729 &g12a_vclk2_encp,
4730 &g12a_dac_clk,
4731 &g12a_aoclk_gate,
4732 &g12a_iec958_gate,
4733 &g12a_enc480p,
4734 &g12a_rng1,
4735 &g12a_vclk2_enct,
4736 &g12a_vclk2_encl,
4737 &g12a_vclk2_venclmmc,
4738 &g12a_vclk2_vencl,
4739 &g12a_vclk2_other1,
4740 &g12a_fixed_pll_dco,
4741 &g12a_sys_pll_dco,
4742 &g12a_gp0_pll_dco,
4743 &g12a_hifi_pll_dco,
4744 &g12a_fclk_div2,
4745 &g12a_fclk_div3,
4746 &g12a_fclk_div4,
4747 &g12a_fclk_div5,
4748 &g12a_fclk_div7,
4749 &g12a_fclk_div2p5,
4750 &g12a_dma,
4751 &g12a_efuse,
4752 &g12a_rom_boot,
4753 &g12a_reset_sec,
4754 &g12a_sec_ahb_apb3,
4755 &g12a_vpu_0_sel,
4756 &g12a_vpu_0_div,
4757 &g12a_vpu_0,
4758 &g12a_vpu_1_sel,
4759 &g12a_vpu_1_div,
4760 &g12a_vpu_1,
4761 &g12a_vpu,
4762 &g12a_vapb_0_sel,
4763 &g12a_vapb_0_div,
4764 &g12a_vapb_0,
4765 &g12a_vapb_1_sel,
4766 &g12a_vapb_1_div,
4767 &g12a_vapb_1,
4768 &g12a_vapb_sel,
4769 &g12a_vapb,
4770 &g12a_hdmi_pll_dco,
4771 &g12a_hdmi_pll_od,
4772 &g12a_hdmi_pll_od2,
4773 &g12a_hdmi_pll,
4774 &g12a_vid_pll_div,
4775 &g12a_vid_pll_sel,
4776 &g12a_vid_pll,
4777 &g12a_vclk_sel,
4778 &g12a_vclk2_sel,
4779 &g12a_vclk_input,
4780 &g12a_vclk2_input,
4781 &g12a_vclk_div,
4782 &g12a_vclk2_div,
4783 &g12a_vclk,
4784 &g12a_vclk2,
4785 &g12a_vclk_div1,
4786 &g12a_vclk_div2_en,
4787 &g12a_vclk_div4_en,
4788 &g12a_vclk_div6_en,
4789 &g12a_vclk_div12_en,
4790 &g12a_vclk2_div1,
4791 &g12a_vclk2_div2_en,
4792 &g12a_vclk2_div4_en,
4793 &g12a_vclk2_div6_en,
4794 &g12a_vclk2_div12_en,
4795 &g12a_cts_enci_sel,
4796 &g12a_cts_encp_sel,
4797 &g12a_cts_vdac_sel,
4798 &g12a_hdmi_tx_sel,
4799 &g12a_cts_enci,
4800 &g12a_cts_encp,
4801 &g12a_cts_vdac,
4802 &g12a_hdmi_tx,
4803 &g12a_hdmi_sel,
4804 &g12a_hdmi_div,
4805 &g12a_hdmi,
4806 &g12a_mali_0_sel,
4807 &g12a_mali_0_div,
4808 &g12a_mali_0,
4809 &g12a_mali_1_sel,
4810 &g12a_mali_1_div,
4811 &g12a_mali_1,
4812 &g12a_mali,
4813 &g12a_mpll_50m,
4814 &g12a_sys_pll_div16_en,
4815 &g12a_cpu_clk_premux0,
4816 &g12a_cpu_clk_mux0_div,
4817 &g12a_cpu_clk_postmux0,
4818 &g12a_cpu_clk_premux1,
4819 &g12a_cpu_clk_mux1_div,
4820 &g12a_cpu_clk_postmux1,
4821 &g12a_cpu_clk_dyn,
4822 &g12a_cpu_clk,
4823 &g12a_cpu_clk_div16_en,
4824 &g12a_cpu_clk_apb_div,
4825 &g12a_cpu_clk_apb,
4826 &g12a_cpu_clk_atb_div,
4827 &g12a_cpu_clk_atb,
4828 &g12a_cpu_clk_axi_div,
4829 &g12a_cpu_clk_axi,
4830 &g12a_cpu_clk_trace_div,
4831 &g12a_cpu_clk_trace,
4832 &g12a_pcie_pll_od,
4833 &g12a_pcie_pll_dco,
4834 &g12a_vdec_1_sel,
4835 &g12a_vdec_1_div,
4836 &g12a_vdec_1,
4837 &g12a_vdec_hevc_sel,
4838 &g12a_vdec_hevc_div,
4839 &g12a_vdec_hevc,
4840 &g12a_vdec_hevcf_sel,
4841 &g12a_vdec_hevcf_div,
4842 &g12a_vdec_hevcf,
4843 &g12a_ts_div,
4844 &g12a_ts,
4845 &g12b_cpu_clk,
4846 &g12b_sys1_pll_dco,
4847 &g12b_sys1_pll,
4848 &g12b_sys1_pll_div16_en,
4849 &g12b_cpub_clk_premux0,
4850 &g12b_cpub_clk_mux0_div,
4851 &g12b_cpub_clk_postmux0,
4852 &g12b_cpub_clk_premux1,
4853 &g12b_cpub_clk_mux1_div,
4854 &g12b_cpub_clk_postmux1,
4855 &g12b_cpub_clk_dyn,
4856 &g12b_cpub_clk,
4857 &g12b_cpub_clk_div16_en,
4858 &g12b_cpub_clk_apb_sel,
4859 &g12b_cpub_clk_apb,
4860 &g12b_cpub_clk_atb_sel,
4861 &g12b_cpub_clk_atb,
4862 &g12b_cpub_clk_axi_sel,
4863 &g12b_cpub_clk_axi,
4864 &g12b_cpub_clk_trace_sel,
4865 &g12b_cpub_clk_trace,
4866 &sm1_gp1_pll_dco,
4867 &sm1_gp1_pll,
4868 &sm1_dsu_clk_premux0,
4869 &sm1_dsu_clk_premux1,
4870 &sm1_dsu_clk_mux0_div,
4871 &sm1_dsu_clk_postmux0,
4872 &sm1_dsu_clk_mux1_div,
4873 &sm1_dsu_clk_postmux1,
4874 &sm1_dsu_clk_dyn,
4875 &sm1_dsu_final_clk,
4876 &sm1_dsu_clk,
4877 &sm1_cpu1_clk,
4878 &sm1_cpu2_clk,
4879 &sm1_cpu3_clk,
4880 };
4881
4882 static const struct reg_sequence g12a_init_regs[] = {
4883 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
4884 };
4885
4886 static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
4887 struct clk_hw **hws)
4888 {
4889 const char *notifier_clk_name;
4890 struct clk *notifier_clk;
4891 struct clk_hw *xtal;
4892 int ret;
4893
4894 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
4895
4896
4897 g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
4898 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
4899 notifier_clk = __clk_lookup(notifier_clk_name);
4900 ret = clk_notifier_register(notifier_clk,
4901 &g12a_cpu_clk_postmux0_nb_data.nb);
4902 if (ret) {
4903 dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
4904 return ret;
4905 }
4906
4907
4908 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
4909 notifier_clk = __clk_lookup(notifier_clk_name);
4910 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4911 if (ret) {
4912 dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
4913 return ret;
4914 }
4915
4916 return 0;
4917 }
4918
4919 static int meson_g12b_dvfs_setup(struct platform_device *pdev)
4920 {
4921 struct clk_hw **hws = g12b_hw_onecell_data.hws;
4922 const char *notifier_clk_name;
4923 struct clk *notifier_clk;
4924 struct clk_hw *xtal;
4925 int ret;
4926
4927 ret = meson_g12a_dvfs_setup_common(pdev, hws);
4928 if (ret)
4929 return ret;
4930
4931 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
4932
4933
4934 notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
4935 notifier_clk = __clk_lookup(notifier_clk_name);
4936 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4937 if (ret) {
4938 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
4939 return ret;
4940 }
4941
4942
4943 notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
4944 notifier_clk = __clk_lookup(notifier_clk_name);
4945 ret = clk_notifier_register(notifier_clk,
4946 &g12b_cpu_clk_sys1_pll_nb_data.nb);
4947 if (ret) {
4948 dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
4949 return ret;
4950 }
4951
4952
4953
4954
4955 g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
4956 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
4957 notifier_clk = __clk_lookup(notifier_clk_name);
4958 ret = clk_notifier_register(notifier_clk,
4959 &g12b_cpub_clk_postmux0_nb_data.nb);
4960 if (ret) {
4961 dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
4962 return ret;
4963 }
4964
4965
4966 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
4967 notifier_clk = __clk_lookup(notifier_clk_name);
4968 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4969 if (ret) {
4970 dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
4971 return ret;
4972 }
4973
4974
4975 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
4976 notifier_clk = __clk_lookup(notifier_clk_name);
4977 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4978 if (ret) {
4979 dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
4980 return ret;
4981 }
4982
4983
4984 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
4985 notifier_clk = __clk_lookup(notifier_clk_name);
4986 ret = clk_notifier_register(notifier_clk,
4987 &g12b_cpub_clk_sys_pll_nb_data.nb);
4988 if (ret) {
4989 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
4990 return ret;
4991 }
4992
4993 return 0;
4994 }
4995
4996 static int meson_g12a_dvfs_setup(struct platform_device *pdev)
4997 {
4998 struct clk_hw **hws = g12a_hw_onecell_data.hws;
4999 const char *notifier_clk_name;
5000 struct clk *notifier_clk;
5001 int ret;
5002
5003 ret = meson_g12a_dvfs_setup_common(pdev, hws);
5004 if (ret)
5005 return ret;
5006
5007
5008 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
5009 notifier_clk = __clk_lookup(notifier_clk_name);
5010 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5011 if (ret) {
5012 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
5013 return ret;
5014 }
5015
5016
5017 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
5018 notifier_clk = __clk_lookup(notifier_clk_name);
5019 ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
5020 if (ret) {
5021 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
5022 return ret;
5023 }
5024
5025 return 0;
5026 }
5027
5028 struct meson_g12a_data {
5029 const struct meson_eeclkc_data eeclkc_data;
5030 int (*dvfs_setup)(struct platform_device *pdev);
5031 };
5032
5033 static int meson_g12a_probe(struct platform_device *pdev)
5034 {
5035 const struct meson_eeclkc_data *eeclkc_data;
5036 const struct meson_g12a_data *g12a_data;
5037 int ret;
5038
5039 eeclkc_data = of_device_get_match_data(&pdev->dev);
5040 if (!eeclkc_data)
5041 return -EINVAL;
5042
5043 ret = meson_eeclkc_probe(pdev);
5044 if (ret)
5045 return ret;
5046
5047 g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5048 eeclkc_data);
5049
5050 if (g12a_data->dvfs_setup)
5051 return g12a_data->dvfs_setup(pdev);
5052
5053 return 0;
5054 }
5055
5056 static const struct meson_g12a_data g12a_clkc_data = {
5057 .eeclkc_data = {
5058 .regmap_clks = g12a_clk_regmaps,
5059 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5060 .hw_onecell_data = &g12a_hw_onecell_data,
5061 .init_regs = g12a_init_regs,
5062 .init_count = ARRAY_SIZE(g12a_init_regs),
5063 },
5064 .dvfs_setup = meson_g12a_dvfs_setup,
5065 };
5066
5067 static const struct meson_g12a_data g12b_clkc_data = {
5068 .eeclkc_data = {
5069 .regmap_clks = g12a_clk_regmaps,
5070 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5071 .hw_onecell_data = &g12b_hw_onecell_data,
5072 },
5073 .dvfs_setup = meson_g12b_dvfs_setup,
5074 };
5075
5076 static const struct meson_g12a_data sm1_clkc_data = {
5077 .eeclkc_data = {
5078 .regmap_clks = g12a_clk_regmaps,
5079 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5080 .hw_onecell_data = &sm1_hw_onecell_data,
5081 },
5082 .dvfs_setup = meson_g12a_dvfs_setup,
5083 };
5084
5085 static const struct of_device_id clkc_match_table[] = {
5086 {
5087 .compatible = "amlogic,g12a-clkc",
5088 .data = &g12a_clkc_data.eeclkc_data
5089 },
5090 {
5091 .compatible = "amlogic,g12b-clkc",
5092 .data = &g12b_clkc_data.eeclkc_data
5093 },
5094 {
5095 .compatible = "amlogic,sm1-clkc",
5096 .data = &sm1_clkc_data.eeclkc_data
5097 },
5098 {}
5099 };
5100
5101 static struct platform_driver g12a_driver = {
5102 .probe = meson_g12a_probe,
5103 .driver = {
5104 .name = "g12a-clkc",
5105 .of_match_table = clkc_match_table,
5106 },
5107 };
5108
5109 builtin_platform_driver(g12a_driver);