This source file includes following definitions.
- atl_write
- atl_read
- atl_clk_enable
- atl_clk_disable
- atl_clk_is_enabled
- atl_clk_recalc_rate
- atl_clk_round_rate
- atl_clk_set_rate
- of_dra7_atl_clock_setup
- of_dra7_atl_clk_probe
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18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/slab.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/clk/ti.h>
28
29 #include "clock.h"
30
31 #define DRA7_ATL_INSTANCES 4
32
33 #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
34 #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
35 #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
36 #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
37 #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
38 #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
39 #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
40
41 #define DRA7_ATL_SWEN BIT(0)
42 #define DRA7_ATL_DIVIDER_MASK (0x1f)
43 #define DRA7_ATL_PCLKMUX BIT(0)
44 struct dra7_atl_clock_info;
45
46 struct dra7_atl_desc {
47 struct clk *clk;
48 struct clk_hw hw;
49 struct dra7_atl_clock_info *cinfo;
50 int id;
51
52 bool probed;
53 bool valid;
54 bool enabled;
55 u32 bws;
56 u32 aws;
57 u32 divider;
58 };
59
60 struct dra7_atl_clock_info {
61 struct device *dev;
62 void __iomem *iobase;
63
64 struct dra7_atl_desc *cdesc;
65 };
66
67 #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
68
69 static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
70 u32 val)
71 {
72 __raw_writel(val, cinfo->iobase + reg);
73 }
74
75 static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
76 {
77 return __raw_readl(cinfo->iobase + reg);
78 }
79
80 static int atl_clk_enable(struct clk_hw *hw)
81 {
82 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
83
84 if (!cdesc->probed)
85 goto out;
86
87 if (unlikely(!cdesc->valid))
88 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
89 cdesc->id);
90 pm_runtime_get_sync(cdesc->cinfo->dev);
91
92 atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
93 cdesc->divider - 1);
94 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
95
96 out:
97 cdesc->enabled = true;
98
99 return 0;
100 }
101
102 static void atl_clk_disable(struct clk_hw *hw)
103 {
104 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
105
106 if (!cdesc->probed)
107 goto out;
108
109 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
110 pm_runtime_put_sync(cdesc->cinfo->dev);
111
112 out:
113 cdesc->enabled = false;
114 }
115
116 static int atl_clk_is_enabled(struct clk_hw *hw)
117 {
118 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
119
120 return cdesc->enabled;
121 }
122
123 static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
125 {
126 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
127
128 return parent_rate / cdesc->divider;
129 }
130
131 static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long *parent_rate)
133 {
134 unsigned divider;
135
136 divider = (*parent_rate + rate / 2) / rate;
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
138 divider = DRA7_ATL_DIVIDER_MASK + 1;
139
140 return *parent_rate / divider;
141 }
142
143 static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long parent_rate)
145 {
146 struct dra7_atl_desc *cdesc;
147 u32 divider;
148
149 if (!hw || !rate)
150 return -EINVAL;
151
152 cdesc = to_atl_desc(hw);
153 divider = ((parent_rate + rate / 2) / rate) - 1;
154 if (divider > DRA7_ATL_DIVIDER_MASK)
155 divider = DRA7_ATL_DIVIDER_MASK;
156
157 cdesc->divider = divider + 1;
158
159 return 0;
160 }
161
162 static const struct clk_ops atl_clk_ops = {
163 .enable = atl_clk_enable,
164 .disable = atl_clk_disable,
165 .is_enabled = atl_clk_is_enabled,
166 .recalc_rate = atl_clk_recalc_rate,
167 .round_rate = atl_clk_round_rate,
168 .set_rate = atl_clk_set_rate,
169 };
170
171 static void __init of_dra7_atl_clock_setup(struct device_node *node)
172 {
173 struct dra7_atl_desc *clk_hw = NULL;
174 struct clk_init_data init = { NULL };
175 const char **parent_names = NULL;
176 struct clk *clk;
177
178 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
179 if (!clk_hw) {
180 pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
181 return;
182 }
183
184 clk_hw->hw.init = &init;
185 clk_hw->divider = 1;
186 init.name = node->name;
187 init.ops = &atl_clk_ops;
188 init.flags = CLK_IGNORE_UNUSED;
189 init.num_parents = of_clk_get_parent_count(node);
190
191 if (init.num_parents != 1) {
192 pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
193 node);
194 goto cleanup;
195 }
196
197 parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
198
199 if (!parent_names)
200 goto cleanup;
201
202 parent_names[0] = of_clk_get_parent_name(node, 0);
203
204 init.parent_names = parent_names;
205
206 clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
207
208 if (!IS_ERR(clk)) {
209 of_clk_add_provider(node, of_clk_src_simple_get, clk);
210 kfree(parent_names);
211 return;
212 }
213 cleanup:
214 kfree(parent_names);
215 kfree(clk_hw);
216 }
217 CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
218
219 static int of_dra7_atl_clk_probe(struct platform_device *pdev)
220 {
221 struct device_node *node = pdev->dev.of_node;
222 struct dra7_atl_clock_info *cinfo;
223 int i;
224 int ret = 0;
225
226 if (!node)
227 return -ENODEV;
228
229 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
230 if (!cinfo)
231 return -ENOMEM;
232
233 cinfo->iobase = of_iomap(node, 0);
234 cinfo->dev = &pdev->dev;
235 pm_runtime_enable(cinfo->dev);
236 pm_runtime_irq_safe(cinfo->dev);
237
238 pm_runtime_get_sync(cinfo->dev);
239 atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
240
241 for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
242 struct device_node *cfg_node;
243 char prop[5];
244 struct dra7_atl_desc *cdesc;
245 struct of_phandle_args clkspec;
246 struct clk *clk;
247 int rc;
248
249 rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
250 NULL, i, &clkspec);
251
252 if (rc) {
253 pr_err("%s: failed to lookup atl clock %d\n", __func__,
254 i);
255 return -EINVAL;
256 }
257
258 clk = of_clk_get_from_provider(&clkspec);
259 if (IS_ERR(clk)) {
260 pr_err("%s: failed to get atl clock %d from provider\n",
261 __func__, i);
262 return PTR_ERR(clk);
263 }
264
265 cdesc = to_atl_desc(__clk_get_hw(clk));
266 cdesc->cinfo = cinfo;
267 cdesc->id = i;
268
269
270 snprintf(prop, sizeof(prop), "atl%u", i);
271 cfg_node = of_get_child_by_name(node, prop);
272 if (cfg_node) {
273 ret = of_property_read_u32(cfg_node, "bws",
274 &cdesc->bws);
275 ret |= of_property_read_u32(cfg_node, "aws",
276 &cdesc->aws);
277 if (!ret) {
278 cdesc->valid = true;
279 atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
280 cdesc->bws);
281 atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
282 cdesc->aws);
283 }
284 of_node_put(cfg_node);
285 }
286
287 cdesc->probed = true;
288
289
290
291
292 if (cdesc->enabled)
293 atl_clk_enable(__clk_get_hw(clk));
294 }
295 pm_runtime_put_sync(cinfo->dev);
296
297 return ret;
298 }
299
300 static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
301 { .compatible = "ti,dra7-atl", },
302 {},
303 };
304
305 static struct platform_driver dra7_atl_clk_driver = {
306 .driver = {
307 .name = "dra7-atl",
308 .suppress_bind_attrs = true,
309 .of_match_table = of_dra7_atl_clk_match_tbl,
310 },
311 .probe = of_dra7_atl_clk_probe,
312 };
313 builtin_platform_driver(dra7_atl_clk_driver);