This source file includes following definitions.
- ddr_perf_cpumask_show
- ddr_pmu_event_show
- ddr_perf_is_filtered
- ddr_perf_filter_val
- ddr_perf_filters_compatible
- ddr_perf_is_enhanced_filtered
- ddr_perf_alloc_counter
- ddr_perf_free_counter
- ddr_perf_read_counter
- ddr_perf_event_init
- ddr_perf_event_update
- ddr_perf_counter_enable
- ddr_perf_event_start
- ddr_perf_event_add
- ddr_perf_event_stop
- ddr_perf_event_del
- ddr_perf_pmu_enable
- ddr_perf_pmu_disable
- ddr_perf_init
- ddr_perf_irq_handler
- ddr_perf_offline_cpu
- ddr_perf_probe
- ddr_perf_remove
1
2
3
4
5
6
7 #include <linux/bitfield.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/perf_event.h>
17 #include <linux/slab.h>
18
19 #define COUNTER_CNTL 0x0
20 #define COUNTER_READ 0x20
21
22 #define COUNTER_DPCR1 0x30
23
24 #define CNTL_OVER 0x1
25 #define CNTL_CLEAR 0x2
26 #define CNTL_EN 0x4
27 #define CNTL_EN_MASK 0xFFFFFFFB
28 #define CNTL_CLEAR_MASK 0xFFFFFFFD
29 #define CNTL_OVER_MASK 0xFFFFFFFE
30
31 #define CNTL_CSV_SHIFT 24
32 #define CNTL_CSV_MASK (0xFF << CNTL_CSV_SHIFT)
33
34 #define EVENT_CYCLES_ID 0
35 #define EVENT_CYCLES_COUNTER 0
36 #define NUM_COUNTERS 4
37
38 #define AXI_MASKING_REVERT 0xffff0000
39
40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
41
42 #define DDR_PERF_DEV_NAME "imx8_ddr"
43 #define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
44
45 static DEFINE_IDA(ddr_ida);
46
47
48 #define DDR_CAP_AXI_ID_FILTER 0x1
49 #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3
50
51 struct fsl_ddr_devtype_data {
52 unsigned int quirks;
53 };
54
55 static const struct fsl_ddr_devtype_data imx8_devtype_data;
56
57 static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
58 .quirks = DDR_CAP_AXI_ID_FILTER,
59 };
60
61 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
62 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
63 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
64 { }
65 };
66 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
67
68 struct ddr_pmu {
69 struct pmu pmu;
70 void __iomem *base;
71 unsigned int cpu;
72 struct hlist_node node;
73 struct device *dev;
74 struct perf_event *events[NUM_COUNTERS];
75 int active_events;
76 enum cpuhp_state cpuhp_state;
77 const struct fsl_ddr_devtype_data *devtype_data;
78 int irq;
79 int id;
80 };
81
82 static ssize_t ddr_perf_cpumask_show(struct device *dev,
83 struct device_attribute *attr, char *buf)
84 {
85 struct ddr_pmu *pmu = dev_get_drvdata(dev);
86
87 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
88 }
89
90 static struct device_attribute ddr_perf_cpumask_attr =
91 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
92
93 static struct attribute *ddr_perf_cpumask_attrs[] = {
94 &ddr_perf_cpumask_attr.attr,
95 NULL,
96 };
97
98 static struct attribute_group ddr_perf_cpumask_attr_group = {
99 .attrs = ddr_perf_cpumask_attrs,
100 };
101
102 static ssize_t
103 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr,
104 char *page)
105 {
106 struct perf_pmu_events_attr *pmu_attr;
107
108 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
109 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
110 }
111
112 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \
113 (&((struct perf_pmu_events_attr[]) { \
114 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
115 .id = _id, } \
116 })[0].attr.attr)
117
118 static struct attribute *ddr_perf_events_attrs[] = {
119 IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID),
120 IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01),
121 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
122 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
123 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
124 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
125 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
126 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
127 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
128 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
129 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
130 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
131 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
132 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
133 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
134 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
135 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
136 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
137 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
138 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
139 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
140 IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31),
141 IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32),
142 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
143 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
144 IMX8_DDR_PMU_EVENT_ATTR(read, 0x35),
145 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
146 IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37),
147 IMX8_DDR_PMU_EVENT_ATTR(write, 0x38),
148 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
149 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
150 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
151 NULL,
152 };
153
154 static struct attribute_group ddr_perf_events_attr_group = {
155 .name = "events",
156 .attrs = ddr_perf_events_attrs,
157 };
158
159 PMU_FORMAT_ATTR(event, "config:0-7");
160 PMU_FORMAT_ATTR(axi_id, "config1:0-15");
161 PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
162
163 static struct attribute *ddr_perf_format_attrs[] = {
164 &format_attr_event.attr,
165 &format_attr_axi_id.attr,
166 &format_attr_axi_mask.attr,
167 NULL,
168 };
169
170 static struct attribute_group ddr_perf_format_attr_group = {
171 .name = "format",
172 .attrs = ddr_perf_format_attrs,
173 };
174
175 static const struct attribute_group *attr_groups[] = {
176 &ddr_perf_events_attr_group,
177 &ddr_perf_format_attr_group,
178 &ddr_perf_cpumask_attr_group,
179 NULL,
180 };
181
182 static bool ddr_perf_is_filtered(struct perf_event *event)
183 {
184 return event->attr.config == 0x41 || event->attr.config == 0x42;
185 }
186
187 static u32 ddr_perf_filter_val(struct perf_event *event)
188 {
189 return event->attr.config1;
190 }
191
192 static bool ddr_perf_filters_compatible(struct perf_event *a,
193 struct perf_event *b)
194 {
195 if (!ddr_perf_is_filtered(a))
196 return true;
197 if (!ddr_perf_is_filtered(b))
198 return true;
199 return ddr_perf_filter_val(a) == ddr_perf_filter_val(b);
200 }
201
202 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event)
203 {
204 unsigned int filt;
205 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
206
207 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED;
208 return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) &&
209 ddr_perf_is_filtered(event);
210 }
211
212 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
213 {
214 int i;
215
216
217
218
219
220
221 if (event == EVENT_CYCLES_ID) {
222 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
223 return EVENT_CYCLES_COUNTER;
224 else
225 return -ENOENT;
226 }
227
228 for (i = 1; i < NUM_COUNTERS; i++) {
229 if (pmu->events[i] == NULL)
230 return i;
231 }
232
233 return -ENOENT;
234 }
235
236 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
237 {
238 pmu->events[counter] = NULL;
239 }
240
241 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
242 {
243 struct perf_event *event = pmu->events[counter];
244 void __iomem *base = pmu->base;
245
246
247
248
249
250
251 base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 :
252 COUNTER_READ;
253 return readl_relaxed(base + counter * 4);
254 }
255
256 static int ddr_perf_event_init(struct perf_event *event)
257 {
258 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
259 struct hw_perf_event *hwc = &event->hw;
260 struct perf_event *sibling;
261
262 if (event->attr.type != event->pmu->type)
263 return -ENOENT;
264
265 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
266 return -EOPNOTSUPP;
267
268 if (event->cpu < 0) {
269 dev_warn(pmu->dev, "Can't provide per-task data!\n");
270 return -EOPNOTSUPP;
271 }
272
273
274
275
276
277
278 if (event->group_leader->pmu != event->pmu &&
279 !is_software_event(event->group_leader))
280 return -EINVAL;
281
282 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
283 if (!ddr_perf_filters_compatible(event, event->group_leader))
284 return -EINVAL;
285 for_each_sibling_event(sibling, event->group_leader) {
286 if (!ddr_perf_filters_compatible(event, sibling))
287 return -EINVAL;
288 }
289 }
290
291 for_each_sibling_event(sibling, event->group_leader) {
292 if (sibling->pmu != event->pmu &&
293 !is_software_event(sibling))
294 return -EINVAL;
295 }
296
297 event->cpu = pmu->cpu;
298 hwc->idx = -1;
299
300 return 0;
301 }
302
303
304 static void ddr_perf_event_update(struct perf_event *event)
305 {
306 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
307 struct hw_perf_event *hwc = &event->hw;
308 u64 delta, prev_raw_count, new_raw_count;
309 int counter = hwc->idx;
310
311 do {
312 prev_raw_count = local64_read(&hwc->prev_count);
313 new_raw_count = ddr_perf_read_counter(pmu, counter);
314 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
315 new_raw_count) != prev_raw_count);
316
317 delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
318
319 local64_add(delta, &event->count);
320 }
321
322 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
323 int counter, bool enable)
324 {
325 u8 reg = counter * 4 + COUNTER_CNTL;
326 int val;
327
328 if (enable) {
329
330
331
332
333
334
335 writel(0, pmu->base + reg);
336 val = CNTL_EN | CNTL_CLEAR;
337 val |= FIELD_PREP(CNTL_CSV_MASK, config);
338 writel(val, pmu->base + reg);
339 } else {
340
341 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
342 writel(val, pmu->base + reg);
343 }
344 }
345
346 static void ddr_perf_event_start(struct perf_event *event, int flags)
347 {
348 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
349 struct hw_perf_event *hwc = &event->hw;
350 int counter = hwc->idx;
351
352 local64_set(&hwc->prev_count, 0);
353
354 ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
355
356 hwc->state = 0;
357 }
358
359 static int ddr_perf_event_add(struct perf_event *event, int flags)
360 {
361 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
362 struct hw_perf_event *hwc = &event->hw;
363 int counter;
364 int cfg = event->attr.config;
365 int cfg1 = event->attr.config1;
366
367 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
368 int i;
369
370 for (i = 1; i < NUM_COUNTERS; i++) {
371 if (pmu->events[i] &&
372 !ddr_perf_filters_compatible(event, pmu->events[i]))
373 return -EINVAL;
374 }
375
376 if (ddr_perf_is_filtered(event)) {
377
378 cfg1 ^= AXI_MASKING_REVERT;
379 writel(cfg1, pmu->base + COUNTER_DPCR1);
380 }
381 }
382
383 counter = ddr_perf_alloc_counter(pmu, cfg);
384 if (counter < 0) {
385 dev_dbg(pmu->dev, "There are not enough counters\n");
386 return -EOPNOTSUPP;
387 }
388
389 pmu->events[counter] = event;
390 pmu->active_events++;
391 hwc->idx = counter;
392
393 hwc->state |= PERF_HES_STOPPED;
394
395 if (flags & PERF_EF_START)
396 ddr_perf_event_start(event, flags);
397
398 return 0;
399 }
400
401 static void ddr_perf_event_stop(struct perf_event *event, int flags)
402 {
403 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
404 struct hw_perf_event *hwc = &event->hw;
405 int counter = hwc->idx;
406
407 ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
408 ddr_perf_event_update(event);
409
410 hwc->state |= PERF_HES_STOPPED;
411 }
412
413 static void ddr_perf_event_del(struct perf_event *event, int flags)
414 {
415 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
416 struct hw_perf_event *hwc = &event->hw;
417 int counter = hwc->idx;
418
419 ddr_perf_event_stop(event, PERF_EF_UPDATE);
420
421 ddr_perf_free_counter(pmu, counter);
422 pmu->active_events--;
423 hwc->idx = -1;
424 }
425
426 static void ddr_perf_pmu_enable(struct pmu *pmu)
427 {
428 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
429
430
431 if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
432 ddr_perf_counter_enable(ddr_pmu,
433 EVENT_CYCLES_ID,
434 EVENT_CYCLES_COUNTER,
435 true);
436 }
437
438 static void ddr_perf_pmu_disable(struct pmu *pmu)
439 {
440 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
441
442 if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
443 ddr_perf_counter_enable(ddr_pmu,
444 EVENT_CYCLES_ID,
445 EVENT_CYCLES_COUNTER,
446 false);
447 }
448
449 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
450 struct device *dev)
451 {
452 *pmu = (struct ddr_pmu) {
453 .pmu = (struct pmu) {
454 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
455 .task_ctx_nr = perf_invalid_context,
456 .attr_groups = attr_groups,
457 .event_init = ddr_perf_event_init,
458 .add = ddr_perf_event_add,
459 .del = ddr_perf_event_del,
460 .start = ddr_perf_event_start,
461 .stop = ddr_perf_event_stop,
462 .read = ddr_perf_event_update,
463 .pmu_enable = ddr_perf_pmu_enable,
464 .pmu_disable = ddr_perf_pmu_disable,
465 },
466 .base = base,
467 .dev = dev,
468 };
469
470 pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
471 return pmu->id;
472 }
473
474 static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
475 {
476 int i;
477 struct ddr_pmu *pmu = (struct ddr_pmu *) p;
478 struct perf_event *event, *cycle_event = NULL;
479
480
481 ddr_perf_counter_enable(pmu,
482 EVENT_CYCLES_ID,
483 EVENT_CYCLES_COUNTER,
484 false);
485
486
487
488
489
490
491
492
493
494
495 for (i = 0; i < NUM_COUNTERS; i++) {
496
497 if (!pmu->events[i])
498 continue;
499
500 event = pmu->events[i];
501
502 ddr_perf_event_update(event);
503
504 if (event->hw.idx == EVENT_CYCLES_COUNTER)
505 cycle_event = event;
506 }
507
508 ddr_perf_counter_enable(pmu,
509 EVENT_CYCLES_ID,
510 EVENT_CYCLES_COUNTER,
511 true);
512 if (cycle_event)
513 ddr_perf_event_update(cycle_event);
514
515 return IRQ_HANDLED;
516 }
517
518 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
519 {
520 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
521 int target;
522
523 if (cpu != pmu->cpu)
524 return 0;
525
526 target = cpumask_any_but(cpu_online_mask, cpu);
527 if (target >= nr_cpu_ids)
528 return 0;
529
530 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
531 pmu->cpu = target;
532
533 WARN_ON(irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu)));
534
535 return 0;
536 }
537
538 static int ddr_perf_probe(struct platform_device *pdev)
539 {
540 struct ddr_pmu *pmu;
541 struct device_node *np;
542 void __iomem *base;
543 char *name;
544 int num;
545 int ret;
546 int irq;
547
548 base = devm_platform_ioremap_resource(pdev, 0);
549 if (IS_ERR(base))
550 return PTR_ERR(base);
551
552 np = pdev->dev.of_node;
553
554 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
555 if (!pmu)
556 return -ENOMEM;
557
558 num = ddr_perf_init(pmu, base, &pdev->dev);
559
560 platform_set_drvdata(pdev, pmu);
561
562 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
563 num);
564 if (!name)
565 return -ENOMEM;
566
567 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
568
569 pmu->cpu = raw_smp_processor_id();
570 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
571 DDR_CPUHP_CB_NAME,
572 NULL,
573 ddr_perf_offline_cpu);
574
575 if (ret < 0) {
576 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n");
577 goto cpuhp_state_err;
578 }
579
580 pmu->cpuhp_state = ret;
581
582
583 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
584 if (ret) {
585 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
586 goto cpuhp_instance_err;
587 }
588
589
590 irq = of_irq_get(np, 0);
591 if (irq < 0) {
592 dev_err(&pdev->dev, "Failed to get irq: %d", irq);
593 ret = irq;
594 goto ddr_perf_err;
595 }
596
597 ret = devm_request_irq(&pdev->dev, irq,
598 ddr_perf_irq_handler,
599 IRQF_NOBALANCING | IRQF_NO_THREAD,
600 DDR_CPUHP_CB_NAME,
601 pmu);
602 if (ret < 0) {
603 dev_err(&pdev->dev, "Request irq failed: %d", ret);
604 goto ddr_perf_err;
605 }
606
607 pmu->irq = irq;
608 ret = irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu));
609 if (ret) {
610 dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
611 goto ddr_perf_err;
612 }
613
614 ret = perf_pmu_register(&pmu->pmu, name, -1);
615 if (ret)
616 goto ddr_perf_err;
617
618 return 0;
619
620 ddr_perf_err:
621 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
622 cpuhp_instance_err:
623 cpuhp_remove_multi_state(pmu->cpuhp_state);
624 cpuhp_state_err:
625 ida_simple_remove(&ddr_ida, pmu->id);
626 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
627 return ret;
628 }
629
630 static int ddr_perf_remove(struct platform_device *pdev)
631 {
632 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
633
634 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
635 cpuhp_remove_multi_state(pmu->cpuhp_state);
636 irq_set_affinity_hint(pmu->irq, NULL);
637
638 perf_pmu_unregister(&pmu->pmu);
639
640 ida_simple_remove(&ddr_ida, pmu->id);
641 return 0;
642 }
643
644 static struct platform_driver imx_ddr_pmu_driver = {
645 .driver = {
646 .name = "imx-ddr-pmu",
647 .of_match_table = imx_ddr_pmu_dt_ids,
648 },
649 .probe = ddr_perf_probe,
650 .remove = ddr_perf_remove,
651 };
652
653 module_platform_driver(imx_ddr_pmu_driver);
654 MODULE_LICENSE("GPL v2");