drivers/tty/serial/8250/8250

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This source file includes following definitions.
omap_8250_rx_dma_flush
uart_read
omap8250_set_mctrl
omap_8250_mdr1_errataset
omap_8250_get_divisor
omap8250_update_scr
omap8250_update_mdr1
omap8250_restore_regs
omap_8250_set_termios
omap_8250_pm
omap_serial_fill_features_erratas
omap8250_uart_qos_work
omap8250_irq
omap_8250_startup
omap_8250_shutdown
omap_8250_throttle
omap_8250_rs485_config
omap_8250_unthrottle
__dma_rx_do_complete
__dma_rx_complete
omap_8250_rx_dma_flush
omap_8250_rx_dma
omap_8250_dma_tx_complete
omap_8250_tx_dma
handle_rx_dma
omap_8250_dma_handle_irq
the_no_dma_filter_fn
omap_8250_rx_dma
omap8250_no_handle_irq
omap8250_probe
omap8250_remove
omap8250_prepare
omap8250_complete
omap8250_suspend
omap8250_resume
omap8250_lost_context
omap8250_soft_reset
omap8250_runtime_suspend
omap8250_runtime_resume
omap8250_console_fixup
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * 8250-core based driver for the OMAP internal UART
   4  *
   5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Copyright (C) 2014 Sebastian Andrzej Siewior
   8  *
   9  */
  10 
  11 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14 
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/tty_flip.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/delay.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/console.h>
  31 #include <linux/pm_qos.h>
  32 #include <linux/pm_wakeirq.h>
  33 #include <linux/dma-mapping.h>
  34 
  35 #include "8250.h"
  36 
  37 #define DEFAULT_CLK_SPEED       48000000
  38 
  39 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  40 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  41 #define OMAP_DMA_TX_KICK                (1 << 2)
  42 /*
  43  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  44  * The same errata is applicable to AM335x and DRA7x processors too.
  45  */
  46 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  47 
  48 #define OMAP_UART_FCR_RX_TRIG           6
  49 #define OMAP_UART_FCR_TX_TRIG           4
  50 
  51 /* SCR register bitmasks */
  52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  54 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  55 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  56 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  57 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  58 
  59 /* MVR register bitmasks */
  60 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  63 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  64 #define OMAP_UART_MVR_MAJ_MASK          0x700
  65 #define OMAP_UART_MVR_MAJ_SHIFT         8
  66 #define OMAP_UART_MVR_MIN_MASK          0x3f
  67 
  68 /* SYSC register bitmasks */
  69 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  70 
  71 /* SYSS register bitmasks */
  72 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  73 
  74 #define UART_TI752_TLR_TX       0
  75 #define UART_TI752_TLR_RX       4
  76 
  77 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  78 #define TRIGGER_FCR_MASK(x)     (x & 3)
  79 
  80 /* Enable XON/XOFF flow control on output */
  81 #define OMAP_UART_SW_TX         0x08
  82 /* Enable XON/XOFF flow control on input */
  83 #define OMAP_UART_SW_RX         0x02
  84 
  85 #define OMAP_UART_WER_MOD_WKUP  0x7f
  86 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  87 
  88 #define TX_TRIGGER      1
  89 #define RX_TRIGGER      48
  90 
  91 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  92 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  93 
  94 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  95 
  96 #define OMAP_UART_REV_46 0x0406
  97 #define OMAP_UART_REV_52 0x0502
  98 #define OMAP_UART_REV_63 0x0603
  99 
 100 struct omap8250_priv {
 101         int line;
 102         u8 habit;
 103         u8 mdr1;
 104         u8 efr;
 105         u8 scr;
 106         u8 wer;
 107         u8 xon;
 108         u8 xoff;
 109         u8 delayed_restore;
 110         u16 quot;
 111 
 112         bool is_suspending;
 113         int wakeirq;
 114         int wakeups_enabled;
 115         u32 latency;
 116         u32 calc_latency;
 117         struct pm_qos_request pm_qos_request;
 118         struct work_struct qos_work;
 119         struct uart_8250_dma omap8250_dma;
 120         spinlock_t rx_dma_lock;
 121         bool rx_dma_broken;
 122         bool throttled;
 123 };
 124 
 125 #ifdef CONFIG_SERIAL_8250_DMA
 126 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 127 #else
 128 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 129 #endif
 130 
 131 static u32 uart_read(struct uart_8250_port *up, u32 reg)
 132 {
 133         return readl(up->port.membase + (reg << up->port.regshift));
 134 }
 135 
 136 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 137 {
 138         struct uart_8250_port *up = up_to_u8250p(port);
 139         struct omap8250_priv *priv = up->port.private_data;
 140         u8 lcr;
 141 
 142         serial8250_do_set_mctrl(port, mctrl);
 143 
 144         if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
 145                 /*
 146                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 147                  * setting if RTS is raised
 148                  */
 149                 lcr = serial_in(up, UART_LCR);
 150                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 151                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 152                         priv->efr |= UART_EFR_RTS;
 153                 else
 154                         priv->efr &= ~UART_EFR_RTS;
 155                 serial_out(up, UART_EFR, priv->efr);
 156                 serial_out(up, UART_LCR, lcr);
 157         }
 158 }
 159 
 160 /*
 161  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 162  * The access to uart register after MDR1 Access
 163  * causes UART to corrupt data.
 164  *
 165  * Need a delay =
 166  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 167  * give 10 times as much
 168  */
 169 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 170                                      struct omap8250_priv *priv)
 171 {
 172         u8 timeout = 255;
 173         u8 old_mdr1;
 174 
 175         old_mdr1 = serial_in(up, UART_OMAP_MDR1);
 176         if (old_mdr1 == priv->mdr1)
 177                 return;
 178 
 179         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 180         udelay(2);
 181         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 182                         UART_FCR_CLEAR_RCVR);
 183         /*
 184          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 185          * TX_FIFO_E bit is 1.
 186          */
 187         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
 188                                 (UART_LSR_THRE | UART_LSR_DR))) {
 189                 timeout--;
 190                 if (!timeout) {
 191                         /* Should *never* happen. we warn and carry on */
 192                         dev_crit(up->port.dev, "Errata i202: timedout %x\n",
 193                                  serial_in(up, UART_LSR));
 194                         break;
 195                 }
 196                 udelay(1);
 197         }
 198 }
 199 
 200 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 201                                   struct omap8250_priv *priv)
 202 {
 203         unsigned int uartclk = port->uartclk;
 204         unsigned int div_13, div_16;
 205         unsigned int abs_d13, abs_d16;
 206 
 207         /*
 208          * Old custom speed handling.
 209          */
 210         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 211                 priv->quot = port->custom_divisor & UART_DIV_MAX;
 212                 /*
 213                  * I assume that nobody is using this. But hey, if somebody
 214                  * would like to specify the divisor _and_ the mode then the
 215                  * driver is ready and waiting for it.
 216                  */
 217                 if (port->custom_divisor & (1 << 16))
 218                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 219                 else
 220                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 221                 return;
 222         }
 223         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 224         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 225 
 226         if (!div_13)
 227                 div_13 = 1;
 228         if (!div_16)
 229                 div_16 = 1;
 230 
 231         abs_d13 = abs(baud - uartclk / 13 / div_13);
 232         abs_d16 = abs(baud - uartclk / 16 / div_16);
 233 
 234         if (abs_d13 >= abs_d16) {
 235                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 236                 priv->quot = div_16;
 237         } else {
 238                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 239                 priv->quot = div_13;
 240         }
 241 }
 242 
 243 static void omap8250_update_scr(struct uart_8250_port *up,
 244                                 struct omap8250_priv *priv)
 245 {
 246         u8 old_scr;
 247 
 248         old_scr = serial_in(up, UART_OMAP_SCR);
 249         if (old_scr == priv->scr)
 250                 return;
 251 
 252         /*
 253          * The manual recommends not to enable the DMA mode selector in the SCR
 254          * (instead of the FCR) register _and_ selecting the DMA mode as one
 255          * register write because this may lead to malfunction.
 256          */
 257         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 258                 serial_out(up, UART_OMAP_SCR,
 259                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 260         serial_out(up, UART_OMAP_SCR, priv->scr);
 261 }
 262 
 263 static void omap8250_update_mdr1(struct uart_8250_port *up,
 264                                  struct omap8250_priv *priv)
 265 {
 266         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 267                 omap_8250_mdr1_errataset(up, priv);
 268         else
 269                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 270 }
 271 
 272 static void omap8250_restore_regs(struct uart_8250_port *up)
 273 {
 274         struct omap8250_priv *priv = up->port.private_data;
 275         struct uart_8250_dma    *dma = up->dma;
 276 
 277         if (dma && dma->tx_running) {
 278                 /*
 279                  * TCSANOW requests the change to occur immediately however if
 280                  * we have a TX-DMA operation in progress then it has been
 281                  * observed that it might stall and never complete. Therefore we
 282                  * delay DMA completes to prevent this hang from happen.
 283                  */
 284                 priv->delayed_restore = 1;
 285                 return;
 286         }
 287 
 288         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 289         serial_out(up, UART_EFR, UART_EFR_ECB);
 290 
 291         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 292         serial8250_out_MCR(up, UART_MCR_TCRTLR);
 293         serial_out(up, UART_FCR, up->fcr);
 294 
 295         omap8250_update_scr(up, priv);
 296 
 297         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 298 
 299         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 300                         OMAP_UART_TCR_HALT(52));
 301         serial_out(up, UART_TI752_TLR,
 302                    TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
 303                    TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
 304 
 305         serial_out(up, UART_LCR, 0);
 306 
 307         /* drop TCR + TLR access, we setup XON/XOFF later */
 308         serial8250_out_MCR(up, up->mcr);
 309         serial_out(up, UART_IER, up->ier);
 310 
 311         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 312         serial_dl_write(up, priv->quot);
 313 
 314         serial_out(up, UART_EFR, priv->efr);
 315 
 316         /* Configure flow control */
 317         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 318         serial_out(up, UART_XON1, priv->xon);
 319         serial_out(up, UART_XOFF1, priv->xoff);
 320 
 321         serial_out(up, UART_LCR, up->lcr);
 322 
 323         omap8250_update_mdr1(up, priv);
 324 
 325         up->port.ops->set_mctrl(&up->port, up->port.mctrl);
 326 }
 327 
 328 /*
 329  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 330  * some differences in how we want to handle flow control.
 331  */
 332 static void omap_8250_set_termios(struct uart_port *port,
 333                                   struct ktermios *termios,
 334                                   struct ktermios *old)
 335 {
 336         struct uart_8250_port *up = up_to_u8250p(port);
 337         struct omap8250_priv *priv = up->port.private_data;
 338         unsigned char cval = 0;
 339         unsigned int baud;
 340 
 341         switch (termios->c_cflag & CSIZE) {
 342         case CS5:
 343                 cval = UART_LCR_WLEN5;
 344                 break;
 345         case CS6:
 346                 cval = UART_LCR_WLEN6;
 347                 break;
 348         case CS7:
 349                 cval = UART_LCR_WLEN7;
 350                 break;
 351         default:
 352         case CS8:
 353                 cval = UART_LCR_WLEN8;
 354                 break;
 355         }
 356 
 357         if (termios->c_cflag & CSTOPB)
 358                 cval |= UART_LCR_STOP;
 359         if (termios->c_cflag & PARENB)
 360                 cval |= UART_LCR_PARITY;
 361         if (!(termios->c_cflag & PARODD))
 362                 cval |= UART_LCR_EPAR;
 363         if (termios->c_cflag & CMSPAR)
 364                 cval |= UART_LCR_SPAR;
 365 
 366         /*
 367          * Ask the core to calculate the divisor for us.
 368          */
 369         baud = uart_get_baud_rate(port, termios, old,
 370                                   port->uartclk / 16 / UART_DIV_MAX,
 371                                   port->uartclk / 13);
 372         omap_8250_get_divisor(port, baud, priv);
 373 
 374         /*
 375          * Ok, we're now changing the port state. Do it with
 376          * interrupts disabled.
 377          */
 378         pm_runtime_get_sync(port->dev);
 379         spin_lock_irq(&port->lock);
 380 
 381         /*
 382          * Update the per-port timeout.
 383          */
 384         uart_update_timeout(port, termios->c_cflag, baud);
 385 
 386         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 387         if (termios->c_iflag & INPCK)
 388                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 389         if (termios->c_iflag & (IGNBRK | PARMRK))
 390                 up->port.read_status_mask |= UART_LSR_BI;
 391 
 392         /*
 393          * Characters to ignore
 394          */
 395         up->port.ignore_status_mask = 0;
 396         if (termios->c_iflag & IGNPAR)
 397                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 398         if (termios->c_iflag & IGNBRK) {
 399                 up->port.ignore_status_mask |= UART_LSR_BI;
 400                 /*
 401                  * If we're ignoring parity and break indicators,
 402                  * ignore overruns too (for real raw support).
 403                  */
 404                 if (termios->c_iflag & IGNPAR)
 405                         up->port.ignore_status_mask |= UART_LSR_OE;
 406         }
 407 
 408         /*
 409          * ignore all characters if CREAD is not set
 410          */
 411         if ((termios->c_cflag & CREAD) == 0)
 412                 up->port.ignore_status_mask |= UART_LSR_DR;
 413 
 414         /*
 415          * Modem status interrupts
 416          */
 417         up->ier &= ~UART_IER_MSI;
 418         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 419                 up->ier |= UART_IER_MSI;
 420 
 421         up->lcr = cval;
 422         /* Up to here it was mostly serial8250_do_set_termios() */
 423 
 424         /*
 425          * We enable TRIG_GRANU for RX and TX and additionally we set
 426          * SCR_TX_EMPTY bit. The result is the following:
 427          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 428          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 429          *   once the UART decides that there no new bytes arriving.
 430          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 431          *   empty - the trigger level is ignored here.
 432          *
 433          * Once DMA is enabled:
 434          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 435          *   bytes in the TX FIFO. On each assert the DMA engine will move
 436          *   TX_TRIGGER bytes into the FIFO.
 437          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 438          *   the FIFO and move RX_TRIGGER bytes.
 439          * This is because threshold and trigger values are the same.
 440          */
 441         up->fcr = UART_FCR_ENABLE_FIFO;
 442         up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
 443         up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
 444 
 445         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 446                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 447 
 448         if (up->dma)
 449                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 450                         OMAP_UART_SCR_DMAMODE_CTL;
 451 
 452         priv->xon = termios->c_cc[VSTART];
 453         priv->xoff = termios->c_cc[VSTOP];
 454 
 455         priv->efr = 0;
 456         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 457 
 458         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
 459             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
 460             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
 461                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 462                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 463                 priv->efr |= UART_EFR_CTS;
 464         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 465                 /*
 466                  * OMAP rx s/w flow control is borked; the transmitter remains
 467                  * stuck off even if rx flow control is subsequently disabled
 468                  */
 469 
 470                 /*
 471                  * IXOFF Flag:
 472                  * Enable XON/XOFF flow control on output.
 473                  * Transmit XON1, XOFF1
 474                  */
 475                 if (termios->c_iflag & IXOFF) {
 476                         up->port.status |= UPSTAT_AUTOXOFF;
 477                         priv->efr |= OMAP_UART_SW_TX;
 478                 }
 479         }
 480         omap8250_restore_regs(up);
 481 
 482         spin_unlock_irq(&up->port.lock);
 483         pm_runtime_mark_last_busy(port->dev);
 484         pm_runtime_put_autosuspend(port->dev);
 485 
 486         /* calculate wakeup latency constraint */
 487         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 488         priv->latency = priv->calc_latency;
 489 
 490         schedule_work(&priv->qos_work);
 491 
 492         /* Don't rewrite B0 */
 493         if (tty_termios_baud_rate(termios))
 494                 tty_termios_encode_baud_rate(termios, baud, baud);
 495 }
 496 
 497 /* same as 8250 except that we may have extra flow bits set in EFR */
 498 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 499                          unsigned int oldstate)
 500 {
 501         struct uart_8250_port *up = up_to_u8250p(port);
 502         u8 efr;
 503 
 504         pm_runtime_get_sync(port->dev);
 505         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 506         efr = serial_in(up, UART_EFR);
 507         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 508         serial_out(up, UART_LCR, 0);
 509 
 510         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 511         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 512         serial_out(up, UART_EFR, efr);
 513         serial_out(up, UART_LCR, 0);
 514 
 515         pm_runtime_mark_last_busy(port->dev);
 516         pm_runtime_put_autosuspend(port->dev);
 517 }
 518 
 519 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 520                                               struct omap8250_priv *priv)
 521 {
 522         u32 mvr, scheme;
 523         u16 revision, major, minor;
 524 
 525         mvr = uart_read(up, UART_OMAP_MVER);
 526 
 527         /* Check revision register scheme */
 528         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 529 
 530         switch (scheme) {
 531         case 0: /* Legacy Scheme: OMAP2/3 */
 532                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 533                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 534                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 535                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 536                 break;
 537         case 1:
 538                 /* New Scheme: OMAP4+ */
 539                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 540                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 541                         OMAP_UART_MVR_MAJ_SHIFT;
 542                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 543                 break;
 544         default:
 545                 dev_warn(up->port.dev,
 546                          "Unknown revision, defaulting to highest\n");
 547                 /* highest possible revision */
 548                 major = 0xff;
 549                 minor = 0xff;
 550         }
 551         /* normalize revision for the driver */
 552         revision = UART_BUILD_REVISION(major, minor);
 553 
 554         switch (revision) {
 555         case OMAP_UART_REV_46:
 556                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 557                 break;
 558         case OMAP_UART_REV_52:
 559                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 560                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 561                 break;
 562         case OMAP_UART_REV_63:
 563                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 564                         OMAP_UART_WER_HAS_TX_WAKEUP;
 565                 break;
 566         default:
 567                 break;
 568         }
 569 }
 570 
 571 static void omap8250_uart_qos_work(struct work_struct *work)
 572 {
 573         struct omap8250_priv *priv;
 574 
 575         priv = container_of(work, struct omap8250_priv, qos_work);
 576         pm_qos_update_request(&priv->pm_qos_request, priv->latency);
 577 }
 578 
 579 #ifdef CONFIG_SERIAL_8250_DMA
 580 static int omap_8250_dma_handle_irq(struct uart_port *port);
 581 #endif
 582 
 583 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 584 {
 585         struct uart_port *port = dev_id;
 586         struct uart_8250_port *up = up_to_u8250p(port);
 587         unsigned int iir;
 588         int ret;
 589 
 590 #ifdef CONFIG_SERIAL_8250_DMA
 591         if (up->dma) {
 592                 ret = omap_8250_dma_handle_irq(port);
 593                 return IRQ_RETVAL(ret);
 594         }
 595 #endif
 596 
 597         serial8250_rpm_get(up);
 598         iir = serial_port_in(port, UART_IIR);
 599         ret = serial8250_handle_irq(port, iir);
 600         serial8250_rpm_put(up);
 601 
 602         return IRQ_RETVAL(ret);
 603 }
 604 
 605 static int omap_8250_startup(struct uart_port *port)
 606 {
 607         struct uart_8250_port *up = up_to_u8250p(port);
 608         struct omap8250_priv *priv = port->private_data;
 609         int ret;
 610 
 611         if (priv->wakeirq) {
 612                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 613                 if (ret)
 614                         return ret;
 615         }
 616 
 617         pm_runtime_get_sync(port->dev);
 618 
 619         up->mcr = 0;
 620         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 621 
 622         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 623 
 624         up->lsr_saved_flags = 0;
 625         up->msr_saved_flags = 0;
 626 
 627         /* Disable DMA for console UART */
 628         if (uart_console(port))
 629                 up->dma = NULL;
 630 
 631         if (up->dma) {
 632                 ret = serial8250_request_dma(up);
 633                 if (ret) {
 634                         dev_warn_ratelimited(port->dev,
 635                                              "failed to request DMA\n");
 636                         up->dma = NULL;
 637                 }
 638         }
 639 
 640         ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
 641                           dev_name(port->dev), port);
 642         if (ret < 0)
 643                 goto err;
 644 
 645         up->ier = UART_IER_RLSI | UART_IER_RDI;
 646         serial_out(up, UART_IER, up->ier);
 647 
 648 #ifdef CONFIG_PM
 649         up->capabilities |= UART_CAP_RPM;
 650 #endif
 651 
 652         /* Enable module level wake up */
 653         priv->wer = OMAP_UART_WER_MOD_WKUP;
 654         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 655                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 656         serial_out(up, UART_OMAP_WER, priv->wer);
 657 
 658         if (up->dma)
 659                 up->dma->rx_dma(up);
 660 
 661         pm_runtime_mark_last_busy(port->dev);
 662         pm_runtime_put_autosuspend(port->dev);
 663         return 0;
 664 err:
 665         pm_runtime_mark_last_busy(port->dev);
 666         pm_runtime_put_autosuspend(port->dev);
 667         dev_pm_clear_wake_irq(port->dev);
 668         return ret;
 669 }
 670 
 671 static void omap_8250_shutdown(struct uart_port *port)
 672 {
 673         struct uart_8250_port *up = up_to_u8250p(port);
 674         struct omap8250_priv *priv = port->private_data;
 675 
 676         flush_work(&priv->qos_work);
 677         if (up->dma)
 678                 omap_8250_rx_dma_flush(up);
 679 
 680         pm_runtime_get_sync(port->dev);
 681 
 682         serial_out(up, UART_OMAP_WER, 0);
 683 
 684         up->ier = 0;
 685         serial_out(up, UART_IER, 0);
 686 
 687         if (up->dma)
 688                 serial8250_release_dma(up);
 689 
 690         /*
 691          * Disable break condition and FIFOs
 692          */
 693         if (up->lcr & UART_LCR_SBC)
 694                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 695         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 696 
 697         pm_runtime_mark_last_busy(port->dev);
 698         pm_runtime_put_autosuspend(port->dev);
 699         free_irq(port->irq, port);
 700         dev_pm_clear_wake_irq(port->dev);
 701 }
 702 
 703 static void omap_8250_throttle(struct uart_port *port)
 704 {
 705         struct omap8250_priv *priv = port->private_data;
 706         struct uart_8250_port *up = up_to_u8250p(port);
 707         unsigned long flags;
 708 
 709         pm_runtime_get_sync(port->dev);
 710 
 711         spin_lock_irqsave(&port->lock, flags);
 712         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 713         serial_out(up, UART_IER, up->ier);
 714         priv->throttled = true;
 715         spin_unlock_irqrestore(&port->lock, flags);
 716 
 717         pm_runtime_mark_last_busy(port->dev);
 718         pm_runtime_put_autosuspend(port->dev);
 719 }
 720 
 721 static int omap_8250_rs485_config(struct uart_port *port,
 722                                   struct serial_rs485 *rs485)
 723 {
 724         struct uart_8250_port *up = up_to_u8250p(port);
 725 
 726         /* Clamp the delays to [0, 100ms] */
 727         rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
 728         rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
 729 
 730         port->rs485 = *rs485;
 731 
 732         /*
 733          * Both serial8250_em485_init and serial8250_em485_destroy
 734          * are idempotent
 735          */
 736         if (rs485->flags & SER_RS485_ENABLED) {
 737                 int ret = serial8250_em485_init(up);
 738 
 739                 if (ret) {
 740                         rs485->flags &= ~SER_RS485_ENABLED;
 741                         port->rs485.flags &= ~SER_RS485_ENABLED;
 742                 }
 743                 return ret;
 744         }
 745 
 746         serial8250_em485_destroy(up);
 747 
 748         return 0;
 749 }
 750 
 751 static void omap_8250_unthrottle(struct uart_port *port)
 752 {
 753         struct omap8250_priv *priv = port->private_data;
 754         struct uart_8250_port *up = up_to_u8250p(port);
 755         unsigned long flags;
 756 
 757         pm_runtime_get_sync(port->dev);
 758 
 759         spin_lock_irqsave(&port->lock, flags);
 760         priv->throttled = false;
 761         if (up->dma)
 762                 up->dma->rx_dma(up);
 763         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 764         serial_out(up, UART_IER, up->ier);
 765         spin_unlock_irqrestore(&port->lock, flags);
 766 
 767         pm_runtime_mark_last_busy(port->dev);
 768         pm_runtime_put_autosuspend(port->dev);
 769 }
 770 
 771 #ifdef CONFIG_SERIAL_8250_DMA
 772 static int omap_8250_rx_dma(struct uart_8250_port *p);
 773 
 774 static void __dma_rx_do_complete(struct uart_8250_port *p)
 775 {
 776         struct omap8250_priv    *priv = p->port.private_data;
 777         struct uart_8250_dma    *dma = p->dma;
 778         struct tty_port         *tty_port = &p->port.state->port;
 779         struct dma_tx_state     state;
 780         int                     count;
 781         unsigned long           flags;
 782         int                     ret;
 783 
 784         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 785 
 786         if (!dma->rx_running)
 787                 goto unlock;
 788 
 789         dma->rx_running = 0;
 790         dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 791 
 792         count = dma->rx_size - state.residue;
 793 
 794         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 795 
 796         p->port.icount.rx += ret;
 797         p->port.icount.buf_overrun += count - ret;
 798 unlock:
 799         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 800 
 801         tty_flip_buffer_push(tty_port);
 802 }
 803 
 804 static void __dma_rx_complete(void *param)
 805 {
 806         struct uart_8250_port *p = param;
 807         struct omap8250_priv *priv = p->port.private_data;
 808         struct uart_8250_dma *dma = p->dma;
 809         struct dma_tx_state     state;
 810         unsigned long flags;
 811 
 812         spin_lock_irqsave(&p->port.lock, flags);
 813 
 814         /*
 815          * If the tx status is not DMA_COMPLETE, then this is a delayed
 816          * completion callback. A previous RX timeout flush would have
 817          * already pushed the data, so exit.
 818          */
 819         if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
 820                         DMA_COMPLETE) {
 821                 spin_unlock_irqrestore(&p->port.lock, flags);
 822                 return;
 823         }
 824         __dma_rx_do_complete(p);
 825         if (!priv->throttled)
 826                 omap_8250_rx_dma(p);
 827 
 828         spin_unlock_irqrestore(&p->port.lock, flags);
 829 }
 830 
 831 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
 832 {
 833         struct omap8250_priv    *priv = p->port.private_data;
 834         struct uart_8250_dma    *dma = p->dma;
 835         struct dma_tx_state     state;
 836         unsigned long           flags;
 837         int ret;
 838 
 839         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 840 
 841         if (!dma->rx_running) {
 842                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 843                 return;
 844         }
 845 
 846         ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 847         if (ret == DMA_IN_PROGRESS) {
 848                 ret = dmaengine_pause(dma->rxchan);
 849                 if (WARN_ON_ONCE(ret))
 850                         priv->rx_dma_broken = true;
 851         }
 852         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 853 
 854         __dma_rx_do_complete(p);
 855         dmaengine_terminate_all(dma->rxchan);
 856 }
 857 
 858 static int omap_8250_rx_dma(struct uart_8250_port *p)
 859 {
 860         struct omap8250_priv            *priv = p->port.private_data;
 861         struct uart_8250_dma            *dma = p->dma;
 862         int                             err = 0;
 863         struct dma_async_tx_descriptor  *desc;
 864         unsigned long                   flags;
 865 
 866         if (priv->rx_dma_broken)
 867                 return -EINVAL;
 868 
 869         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 870 
 871         if (dma->rx_running)
 872                 goto out;
 873 
 874         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 875                                            dma->rx_size, DMA_DEV_TO_MEM,
 876                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 877         if (!desc) {
 878                 err = -EBUSY;
 879                 goto out;
 880         }
 881 
 882         dma->rx_running = 1;
 883         desc->callback = __dma_rx_complete;
 884         desc->callback_param = p;
 885 
 886         dma->rx_cookie = dmaengine_submit(desc);
 887 
 888         dma_async_issue_pending(dma->rxchan);
 889 out:
 890         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 891         return err;
 892 }
 893 
 894 static int omap_8250_tx_dma(struct uart_8250_port *p);
 895 
 896 static void omap_8250_dma_tx_complete(void *param)
 897 {
 898         struct uart_8250_port   *p = param;
 899         struct uart_8250_dma    *dma = p->dma;
 900         struct circ_buf         *xmit = &p->port.state->xmit;
 901         unsigned long           flags;
 902         bool                    en_thri = false;
 903         struct omap8250_priv    *priv = p->port.private_data;
 904 
 905         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
 906                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 907 
 908         spin_lock_irqsave(&p->port.lock, flags);
 909 
 910         dma->tx_running = 0;
 911 
 912         xmit->tail += dma->tx_size;
 913         xmit->tail &= UART_XMIT_SIZE - 1;
 914         p->port.icount.tx += dma->tx_size;
 915 
 916         if (priv->delayed_restore) {
 917                 priv->delayed_restore = 0;
 918                 omap8250_restore_regs(p);
 919         }
 920 
 921         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 922                 uart_write_wakeup(&p->port);
 923 
 924         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
 925                 int ret;
 926 
 927                 ret = omap_8250_tx_dma(p);
 928                 if (ret)
 929                         en_thri = true;
 930         } else if (p->capabilities & UART_CAP_RPM) {
 931                 en_thri = true;
 932         }
 933 
 934         if (en_thri) {
 935                 dma->tx_err = 1;
 936                 serial8250_set_THRI(p);
 937         }
 938 
 939         spin_unlock_irqrestore(&p->port.lock, flags);
 940 }
 941 
 942 static int omap_8250_tx_dma(struct uart_8250_port *p)
 943 {
 944         struct uart_8250_dma            *dma = p->dma;
 945         struct omap8250_priv            *priv = p->port.private_data;
 946         struct circ_buf                 *xmit = &p->port.state->xmit;
 947         struct dma_async_tx_descriptor  *desc;
 948         unsigned int    skip_byte = 0;
 949         int ret;
 950 
 951         if (dma->tx_running)
 952                 return 0;
 953         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
 954 
 955                 /*
 956                  * Even if no data, we need to return an error for the two cases
 957                  * below so serial8250_tx_chars() is invoked and properly clears
 958                  * THRI and/or runtime suspend.
 959                  */
 960                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
 961                         ret = -EBUSY;
 962                         goto err;
 963                 }
 964                 serial8250_clear_THRI(p);
 965                 return 0;
 966         }
 967 
 968         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 969         if (priv->habit & OMAP_DMA_TX_KICK) {
 970                 u8 tx_lvl;
 971 
 972                 /*
 973                  * We need to put the first byte into the FIFO in order to start
 974                  * the DMA transfer. For transfers smaller than four bytes we
 975                  * don't bother doing DMA at all. It seem not matter if there
 976                  * are still bytes in the FIFO from the last transfer (in case
 977                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
 978                  * leaving the FIFO seem not to trigger the DMA transfer. It is
 979                  * really the byte that we put into the FIFO.
 980                  * If the FIFO is already full then we most likely got here from
 981                  * omap_8250_dma_tx_complete(). And this means the DMA engine
 982                  * just completed its work. We don't have to wait the complete
 983                  * 86us at 115200,8n1 but around 60us (not to mention lower
 984                  * baudrates). So in that case we take the interrupt and try
 985                  * again with an empty FIFO.
 986                  */
 987                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
 988                 if (tx_lvl == p->tx_loadsz) {
 989                         ret = -EBUSY;
 990                         goto err;
 991                 }
 992                 if (dma->tx_size < 4) {
 993                         ret = -EINVAL;
 994                         goto err;
 995                 }
 996                 skip_byte = 1;
 997         }
 998 
 999         desc = dmaengine_prep_slave_single(dma->txchan,
1000                         dma->tx_addr + xmit->tail + skip_byte,
1001                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1002                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1003         if (!desc) {
1004                 ret = -EBUSY;
1005                 goto err;
1006         }
1007 
1008         dma->tx_running = 1;
1009 
1010         desc->callback = omap_8250_dma_tx_complete;
1011         desc->callback_param = p;
1012 
1013         dma->tx_cookie = dmaengine_submit(desc);
1014 
1015         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1016                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1017 
1018         dma_async_issue_pending(dma->txchan);
1019         if (dma->tx_err)
1020                 dma->tx_err = 0;
1021 
1022         serial8250_clear_THRI(p);
1023         if (skip_byte)
1024                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1025         return 0;
1026 err:
1027         dma->tx_err = 1;
1028         return ret;
1029 }
1030 
1031 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1032 {
1033         switch (iir & 0x3f) {
1034         case UART_IIR_RLSI:
1035         case UART_IIR_RX_TIMEOUT:
1036         case UART_IIR_RDI:
1037                 omap_8250_rx_dma_flush(up);
1038                 return true;
1039         }
1040         return omap_8250_rx_dma(up);
1041 }
1042 
1043 /*
1044  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1045  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1046  * use the default routine in the non-DMA case and this one for with DMA.
1047  */
1048 static int omap_8250_dma_handle_irq(struct uart_port *port)
1049 {
1050         struct uart_8250_port *up = up_to_u8250p(port);
1051         unsigned char status;
1052         unsigned long flags;
1053         u8 iir;
1054 
1055         serial8250_rpm_get(up);
1056 
1057         iir = serial_port_in(port, UART_IIR);
1058         if (iir & UART_IIR_NO_INT) {
1059                 serial8250_rpm_put(up);
1060                 return 0;
1061         }
1062 
1063         spin_lock_irqsave(&port->lock, flags);
1064 
1065         status = serial_port_in(port, UART_LSR);
1066 
1067         if (status & (UART_LSR_DR | UART_LSR_BI)) {
1068                 if (handle_rx_dma(up, iir)) {
1069                         status = serial8250_rx_chars(up, status);
1070                         omap_8250_rx_dma(up);
1071                 }
1072         }
1073         serial8250_modem_status(up);
1074         if (status & UART_LSR_THRE && up->dma->tx_err) {
1075                 if (uart_tx_stopped(&up->port) ||
1076                     uart_circ_empty(&up->port.state->xmit)) {
1077                         up->dma->tx_err = 0;
1078                         serial8250_tx_chars(up);
1079                 } else  {
1080                         /*
1081                          * try again due to an earlier failer which
1082                          * might have been resolved by now.
1083                          */
1084                         if (omap_8250_tx_dma(up))
1085                                 serial8250_tx_chars(up);
1086                 }
1087         }
1088 
1089         uart_unlock_and_check_sysrq(port, flags);
1090         serial8250_rpm_put(up);
1091         return 1;
1092 }
1093 
1094 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1095 {
1096         return false;
1097 }
1098 
1099 #else
1100 
1101 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1102 {
1103         return -EINVAL;
1104 }
1105 #endif
1106 
1107 static int omap8250_no_handle_irq(struct uart_port *port)
1108 {
1109         /* IRQ has not been requested but handling irq? */
1110         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1111         return 0;
1112 }
1113 
1114 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1115 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1116 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1117 
1118 static const struct of_device_id omap8250_dt_ids[] = {
1119         { .compatible = "ti,am654-uart" },
1120         { .compatible = "ti,omap2-uart" },
1121         { .compatible = "ti,omap3-uart" },
1122         { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1123         { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1124         { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1125         { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1126         {},
1127 };
1128 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1129 
1130 static int omap8250_probe(struct platform_device *pdev)
1131 {
1132         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1133         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1134         struct device_node *np = pdev->dev.of_node;
1135         struct omap8250_priv *priv;
1136         struct uart_8250_port up;
1137         int ret;
1138         void __iomem *membase;
1139         const struct of_device_id *id;
1140 
1141         if (!regs || !irq) {
1142                 dev_err(&pdev->dev, "missing registers or irq\n");
1143                 return -EINVAL;
1144         }
1145 
1146         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1147         if (!priv)
1148                 return -ENOMEM;
1149 
1150         membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1151                                        resource_size(regs));
1152         if (!membase)
1153                 return -ENODEV;
1154 
1155         memset(&up, 0, sizeof(up));
1156         up.port.dev = &pdev->dev;
1157         up.port.mapbase = regs->start;
1158         up.port.membase = membase;
1159         up.port.irq = irq->start;
1160         /*
1161          * It claims to be 16C750 compatible however it is a little different.
1162          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1163          * have) is enabled via EFR instead of MCR. The type is set here 8250
1164          * just to get things going. UNKNOWN does not work for a few reasons and
1165          * we don't need our own type since we don't use 8250's set_termios()
1166          * or pm callback.
1167          */
1168         up.port.type = PORT_8250;
1169         up.port.iotype = UPIO_MEM;
1170         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1171                 UPF_HARD_FLOW;
1172         up.port.private_data = priv;
1173 
1174         up.port.regshift = 2;
1175         up.port.fifosize = 64;
1176         up.tx_loadsz = 64;
1177         up.capabilities = UART_CAP_FIFO;
1178 #ifdef CONFIG_PM
1179         /*
1180          * Runtime PM is mostly transparent. However to do it right we need to a
1181          * TX empty interrupt before we can put the device to auto idle. So if
1182          * PM is not enabled we don't add that flag and can spare that one extra
1183          * interrupt in the TX path.
1184          */
1185         up.capabilities |= UART_CAP_RPM;
1186 #endif
1187         up.port.set_termios = omap_8250_set_termios;
1188         up.port.set_mctrl = omap8250_set_mctrl;
1189         up.port.pm = omap_8250_pm;
1190         up.port.startup = omap_8250_startup;
1191         up.port.shutdown = omap_8250_shutdown;
1192         up.port.throttle = omap_8250_throttle;
1193         up.port.unthrottle = omap_8250_unthrottle;
1194         up.port.rs485_config = omap_8250_rs485_config;
1195 
1196         ret = of_alias_get_id(np, "serial");
1197         if (ret < 0) {
1198                 dev_err(&pdev->dev, "failed to get alias\n");
1199                 return ret;
1200         }
1201         up.port.line = ret;
1202 
1203         if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1204                 struct clk *clk;
1205 
1206                 clk = devm_clk_get(&pdev->dev, NULL);
1207                 if (IS_ERR(clk)) {
1208                         if (PTR_ERR(clk) == -EPROBE_DEFER)
1209                                 return -EPROBE_DEFER;
1210                 } else {
1211                         up.port.uartclk = clk_get_rate(clk);
1212                 }
1213         }
1214 
1215         priv->wakeirq = irq_of_parse_and_map(np, 1);
1216 
1217         id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1218         if (id && id->data)
1219                 priv->habit |= *(u8 *)id->data;
1220 
1221         if (!up.port.uartclk) {
1222                 up.port.uartclk = DEFAULT_CLK_SPEED;
1223                 dev_warn(&pdev->dev,
1224                          "No clock speed specified: using default: %d\n",
1225                          DEFAULT_CLK_SPEED);
1226         }
1227 
1228         priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1229         priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1230         pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1231                            priv->latency);
1232         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1233 
1234         spin_lock_init(&priv->rx_dma_lock);
1235 
1236         device_init_wakeup(&pdev->dev, true);
1237         pm_runtime_use_autosuspend(&pdev->dev);
1238 
1239         /*
1240          * Disable runtime PM until autosuspend delay unless specifically
1241          * enabled by the user via sysfs. This is the historic way to
1242          * prevent an unsafe default policy with lossy characters on wake-up.
1243          * For serdev devices this is not needed, the policy can be managed by
1244          * the serdev driver.
1245          */
1246         if (!of_get_available_child_count(pdev->dev.of_node))
1247                 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1248 
1249         pm_runtime_irq_safe(&pdev->dev);
1250         pm_runtime_enable(&pdev->dev);
1251 
1252         pm_runtime_get_sync(&pdev->dev);
1253 
1254         omap_serial_fill_features_erratas(&up, priv);
1255         up.port.handle_irq = omap8250_no_handle_irq;
1256 #ifdef CONFIG_SERIAL_8250_DMA
1257         /*
1258          * Oh DMA support. If there are no DMA properties in the DT then
1259          * we will fall back to a generic DMA channel which does not
1260          * really work here. To ensure that we do not get a generic DMA
1261          * channel assigned, we have the the_no_dma_filter_fn() here.
1262          * To avoid "failed to request DMA" messages we check for DMA
1263          * properties in DT.
1264          */
1265         ret = of_property_count_strings(np, "dma-names");
1266         if (ret == 2) {
1267                 up.dma = &priv->omap8250_dma;
1268                 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1269                 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1270                 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1271                 priv->omap8250_dma.rx_size = RX_TRIGGER;
1272                 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1273                 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1274         }
1275 #endif
1276         ret = serial8250_register_8250_port(&up);
1277         if (ret < 0) {
1278                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1279                 goto err;
1280         }
1281         priv->line = ret;
1282         platform_set_drvdata(pdev, priv);
1283         pm_runtime_mark_last_busy(&pdev->dev);
1284         pm_runtime_put_autosuspend(&pdev->dev);
1285         return 0;
1286 err:
1287         pm_runtime_dont_use_autosuspend(&pdev->dev);
1288         pm_runtime_put_sync(&pdev->dev);
1289         pm_runtime_disable(&pdev->dev);
1290         return ret;
1291 }
1292 
1293 static int omap8250_remove(struct platform_device *pdev)
1294 {
1295         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1296 
1297         pm_runtime_dont_use_autosuspend(&pdev->dev);
1298         pm_runtime_put_sync(&pdev->dev);
1299         pm_runtime_disable(&pdev->dev);
1300         serial8250_unregister_port(priv->line);
1301         pm_qos_remove_request(&priv->pm_qos_request);
1302         device_init_wakeup(&pdev->dev, false);
1303         return 0;
1304 }
1305 
1306 #ifdef CONFIG_PM_SLEEP
1307 static int omap8250_prepare(struct device *dev)
1308 {
1309         struct omap8250_priv *priv = dev_get_drvdata(dev);
1310 
1311         if (!priv)
1312                 return 0;
1313         priv->is_suspending = true;
1314         return 0;
1315 }
1316 
1317 static void omap8250_complete(struct device *dev)
1318 {
1319         struct omap8250_priv *priv = dev_get_drvdata(dev);
1320 
1321         if (!priv)
1322                 return;
1323         priv->is_suspending = false;
1324 }
1325 
1326 static int omap8250_suspend(struct device *dev)
1327 {
1328         struct omap8250_priv *priv = dev_get_drvdata(dev);
1329         struct uart_8250_port *up = serial8250_get_port(priv->line);
1330 
1331         serial8250_suspend_port(priv->line);
1332 
1333         pm_runtime_get_sync(dev);
1334         if (!device_may_wakeup(dev))
1335                 priv->wer = 0;
1336         serial_out(up, UART_OMAP_WER, priv->wer);
1337         pm_runtime_mark_last_busy(dev);
1338         pm_runtime_put_autosuspend(dev);
1339 
1340         flush_work(&priv->qos_work);
1341         return 0;
1342 }
1343 
1344 static int omap8250_resume(struct device *dev)
1345 {
1346         struct omap8250_priv *priv = dev_get_drvdata(dev);
1347 
1348         serial8250_resume_port(priv->line);
1349         return 0;
1350 }
1351 #else
1352 #define omap8250_prepare NULL
1353 #define omap8250_complete NULL
1354 #endif
1355 
1356 #ifdef CONFIG_PM
1357 static int omap8250_lost_context(struct uart_8250_port *up)
1358 {
1359         u32 val;
1360 
1361         val = serial_in(up, UART_OMAP_SCR);
1362         /*
1363          * If we lose context, then SCR is set to its reset value of zero.
1364          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1365          * among other bits, to never set the register back to zero again.
1366          */
1367         if (!val)
1368                 return 1;
1369         return 0;
1370 }
1371 
1372 /* TODO: in future, this should happen via API in drivers/reset/ */
1373 static int omap8250_soft_reset(struct device *dev)
1374 {
1375         struct omap8250_priv *priv = dev_get_drvdata(dev);
1376         struct uart_8250_port *up = serial8250_get_port(priv->line);
1377         int timeout = 100;
1378         int sysc;
1379         int syss;
1380 
1381         /*
1382          * At least on omap4, unused uarts may not idle after reset without
1383          * a basic scr dma configuration even with no dma in use. The
1384          * module clkctrl status bits will be 1 instead of 3 blocking idle
1385          * for the whole clockdomain. The softreset below will clear scr,
1386          * and we restore it on resume so this is safe to do on all SoCs
1387          * needing omap8250_soft_reset() quirk. Do it in two writes as
1388          * recommended in the comment for omap8250_update_scr().
1389          */
1390         serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1391         serial_out(up, UART_OMAP_SCR,
1392                    OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1393 
1394         sysc = serial_in(up, UART_OMAP_SYSC);
1395 
1396         /* softreset the UART */
1397         sysc |= OMAP_UART_SYSC_SOFTRESET;
1398         serial_out(up, UART_OMAP_SYSC, sysc);
1399 
1400         /* By experiments, 1us enough for reset complete on AM335x */
1401         do {
1402                 udelay(1);
1403                 syss = serial_in(up, UART_OMAP_SYSS);
1404         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1405 
1406         if (!timeout) {
1407                 dev_err(dev, "timed out waiting for reset done\n");
1408                 return -ETIMEDOUT;
1409         }
1410 
1411         return 0;
1412 }
1413 
1414 static int omap8250_runtime_suspend(struct device *dev)
1415 {
1416         struct omap8250_priv *priv = dev_get_drvdata(dev);
1417         struct uart_8250_port *up;
1418 
1419         /* In case runtime-pm tries this before we are setup */
1420         if (!priv)
1421                 return 0;
1422 
1423         up = serial8250_get_port(priv->line);
1424         /*
1425          * When using 'no_console_suspend', the console UART must not be
1426          * suspended. Since driver suspend is managed by runtime suspend,
1427          * preventing runtime suspend (by returning error) will keep device
1428          * active during suspend.
1429          */
1430         if (priv->is_suspending && !console_suspend_enabled) {
1431                 if (uart_console(&up->port))
1432                         return -EBUSY;
1433         }
1434 
1435         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1436                 int ret;
1437 
1438                 ret = omap8250_soft_reset(dev);
1439                 if (ret)
1440                         return ret;
1441 
1442                 /* Restore to UART mode after reset (for wakeup) */
1443                 omap8250_update_mdr1(up, priv);
1444                 /* Restore wakeup enable register */
1445                 serial_out(up, UART_OMAP_WER, priv->wer);
1446         }
1447 
1448         if (up->dma && up->dma->rxchan)
1449                 omap_8250_rx_dma_flush(up);
1450 
1451         priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1452         schedule_work(&priv->qos_work);
1453 
1454         return 0;
1455 }
1456 
1457 static int omap8250_runtime_resume(struct device *dev)
1458 {
1459         struct omap8250_priv *priv = dev_get_drvdata(dev);
1460         struct uart_8250_port *up;
1461 
1462         /* In case runtime-pm tries this before we are setup */
1463         if (!priv)
1464                 return 0;
1465 
1466         up = serial8250_get_port(priv->line);
1467 
1468         if (omap8250_lost_context(up))
1469                 omap8250_restore_regs(up);
1470 
1471         if (up->dma && up->dma->rxchan)
1472                 omap_8250_rx_dma(up);
1473 
1474         priv->latency = priv->calc_latency;
1475         schedule_work(&priv->qos_work);
1476         return 0;
1477 }
1478 #endif
1479 
1480 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1481 static int __init omap8250_console_fixup(void)
1482 {
1483         char *omap_str;
1484         char *options;
1485         u8 idx;
1486 
1487         if (strstr(boot_command_line, "console=ttyS"))
1488                 /* user set a ttyS based name for the console */
1489                 return 0;
1490 
1491         omap_str = strstr(boot_command_line, "console=ttyO");
1492         if (!omap_str)
1493                 /* user did not set ttyO based console, so we don't care */
1494                 return 0;
1495 
1496         omap_str += 12;
1497         if ('0' <= *omap_str && *omap_str <= '9')
1498                 idx = *omap_str - '0';
1499         else
1500                 return 0;
1501 
1502         omap_str++;
1503         if (omap_str[0] == ',') {
1504                 omap_str++;
1505                 options = omap_str;
1506         } else {
1507                 options = NULL;
1508         }
1509 
1510         add_preferred_console("ttyS", idx, options);
1511         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1512                idx, idx);
1513         pr_err("This ensures that you still see kernel messages. Please\n");
1514         pr_err("update your kernel commandline.\n");
1515         return 0;
1516 }
1517 console_initcall(omap8250_console_fixup);
1518 #endif
1519 
1520 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1521         SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1522         SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1523                            omap8250_runtime_resume, NULL)
1524         .prepare        = omap8250_prepare,
1525         .complete       = omap8250_complete,
1526 };
1527 
1528 static struct platform_driver omap8250_platform_driver = {
1529         .driver = {
1530                 .name           = "omap8250",
1531                 .pm             = &omap8250_dev_pm_ops,
1532                 .of_match_table = omap8250_dt_ids,
1533         },
1534         .probe                  = omap8250_probe,
1535         .remove                 = omap8250_remove,
1536 };
1537 module_platform_driver(omap8250_platform_driver);
1538 
1539 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1540 MODULE_DESCRIPTION("OMAP 8250 Driver");
1541 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/8250/8250_omap.c

DEFINITIONS
