This source file includes following definitions.
- sccnxp_read
- sccnxp_write
- sccnxp_port_read
- sccnxp_port_write
- sccnxp_update_best_err
- sccnxp_set_baud
- sccnxp_enable_irq
- sccnxp_disable_irq
- sccnxp_set_bit
- sccnxp_handle_rx
- sccnxp_handle_tx
- sccnxp_handle_events
- sccnxp_timer
- sccnxp_ist
- sccnxp_start_tx
- sccnxp_stop_tx
- sccnxp_stop_rx
- sccnxp_tx_empty
- sccnxp_set_mctrl
- sccnxp_get_mctrl
- sccnxp_break_ctl
- sccnxp_set_termios
- sccnxp_startup
- sccnxp_shutdown
- sccnxp_type
- sccnxp_release_port
- sccnxp_request_port
- sccnxp_config_port
- sccnxp_verify_port
- sccnxp_console_putchar
- sccnxp_console_write
- sccnxp_console_setup
- sccnxp_probe
- sccnxp_remove
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10 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 #define SUPPORT_SYSRQ
12 #endif
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/device.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/io.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/platform_data/serial-sccnxp.h>
29 #include <linux/regulator/consumer.h>
30
31 #define SCCNXP_NAME "uart-sccnxp"
32 #define SCCNXP_MAJOR 204
33 #define SCCNXP_MINOR 205
34
35 #define SCCNXP_MR_REG (0x00)
36 # define MR0_BAUD_NORMAL (0 << 0)
37 # define MR0_BAUD_EXT1 (1 << 0)
38 # define MR0_BAUD_EXT2 (5 << 0)
39 # define MR0_FIFO (1 << 3)
40 # define MR0_TXLVL (1 << 4)
41 # define MR1_BITS_5 (0 << 0)
42 # define MR1_BITS_6 (1 << 0)
43 # define MR1_BITS_7 (2 << 0)
44 # define MR1_BITS_8 (3 << 0)
45 # define MR1_PAR_EVN (0 << 2)
46 # define MR1_PAR_ODD (1 << 2)
47 # define MR1_PAR_NO (4 << 2)
48 # define MR2_STOP1 (7 << 0)
49 # define MR2_STOP2 (0xf << 0)
50 #define SCCNXP_SR_REG (0x01)
51 # define SR_RXRDY (1 << 0)
52 # define SR_FULL (1 << 1)
53 # define SR_TXRDY (1 << 2)
54 # define SR_TXEMT (1 << 3)
55 # define SR_OVR (1 << 4)
56 # define SR_PE (1 << 5)
57 # define SR_FE (1 << 6)
58 # define SR_BRK (1 << 7)
59 #define SCCNXP_CSR_REG (SCCNXP_SR_REG)
60 # define CSR_TIMER_MODE (0x0d)
61 #define SCCNXP_CR_REG (0x02)
62 # define CR_RX_ENABLE (1 << 0)
63 # define CR_RX_DISABLE (1 << 1)
64 # define CR_TX_ENABLE (1 << 2)
65 # define CR_TX_DISABLE (1 << 3)
66 # define CR_CMD_MRPTR1 (0x01 << 4)
67 # define CR_CMD_RX_RESET (0x02 << 4)
68 # define CR_CMD_TX_RESET (0x03 << 4)
69 # define CR_CMD_STATUS_RESET (0x04 << 4)
70 # define CR_CMD_BREAK_RESET (0x05 << 4)
71 # define CR_CMD_START_BREAK (0x06 << 4)
72 # define CR_CMD_STOP_BREAK (0x07 << 4)
73 # define CR_CMD_MRPTR0 (0x0b << 4)
74 #define SCCNXP_RHR_REG (0x03)
75 #define SCCNXP_THR_REG SCCNXP_RHR_REG
76 #define SCCNXP_IPCR_REG (0x04)
77 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
78 # define ACR_BAUD0 (0 << 7)
79 # define ACR_BAUD1 (1 << 7)
80 # define ACR_TIMER_MODE (6 << 4)
81 #define SCCNXP_ISR_REG (0x05)
82 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
83 # define IMR_TXRDY (1 << 0)
84 # define IMR_RXRDY (1 << 1)
85 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
86 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
87 #define SCCNXP_CTPU_REG (0x06)
88 #define SCCNXP_CTPL_REG (0x07)
89 #define SCCNXP_IPR_REG (0x0d)
90 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
91 #define SCCNXP_SOP_REG (0x0e)
92 #define SCCNXP_START_COUNTER_REG SCCNXP_SOP_REG
93 #define SCCNXP_ROP_REG (0x0f)
94
95
96 #define MCTRL_MASK(sig) (0xf << (sig))
97 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
98 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
99
100 #define SCCNXP_HAVE_IO 0x00000001
101 #define SCCNXP_HAVE_MR0 0x00000002
102
103 struct sccnxp_chip {
104 const char *name;
105 unsigned int nr;
106 unsigned long freq_min;
107 unsigned long freq_std;
108 unsigned long freq_max;
109 unsigned int flags;
110 unsigned int fifosize;
111
112 unsigned int trwd;
113 };
114
115 struct sccnxp_port {
116 struct uart_driver uart;
117 struct uart_port port[SCCNXP_MAX_UARTS];
118 bool opened[SCCNXP_MAX_UARTS];
119
120 int irq;
121 u8 imr;
122
123 struct sccnxp_chip *chip;
124
125 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
126 struct console console;
127 #endif
128
129 spinlock_t lock;
130
131 bool poll;
132 struct timer_list timer;
133
134 struct sccnxp_pdata pdata;
135
136 struct regulator *regulator;
137 };
138
139 static const struct sccnxp_chip sc2681 = {
140 .name = "SC2681",
141 .nr = 2,
142 .freq_min = 1000000,
143 .freq_std = 3686400,
144 .freq_max = 4000000,
145 .flags = SCCNXP_HAVE_IO,
146 .fifosize = 3,
147 .trwd = 200,
148 };
149
150 static const struct sccnxp_chip sc2691 = {
151 .name = "SC2691",
152 .nr = 1,
153 .freq_min = 1000000,
154 .freq_std = 3686400,
155 .freq_max = 4000000,
156 .flags = 0,
157 .fifosize = 3,
158 .trwd = 150,
159 };
160
161 static const struct sccnxp_chip sc2692 = {
162 .name = "SC2692",
163 .nr = 2,
164 .freq_min = 1000000,
165 .freq_std = 3686400,
166 .freq_max = 4000000,
167 .flags = SCCNXP_HAVE_IO,
168 .fifosize = 3,
169 .trwd = 30,
170 };
171
172 static const struct sccnxp_chip sc2891 = {
173 .name = "SC2891",
174 .nr = 1,
175 .freq_min = 100000,
176 .freq_std = 3686400,
177 .freq_max = 8000000,
178 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
179 .fifosize = 16,
180 .trwd = 27,
181 };
182
183 static const struct sccnxp_chip sc2892 = {
184 .name = "SC2892",
185 .nr = 2,
186 .freq_min = 100000,
187 .freq_std = 3686400,
188 .freq_max = 8000000,
189 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
190 .fifosize = 16,
191 .trwd = 17,
192 };
193
194 static const struct sccnxp_chip sc28202 = {
195 .name = "SC28202",
196 .nr = 2,
197 .freq_min = 1000000,
198 .freq_std = 14745600,
199 .freq_max = 50000000,
200 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
201 .fifosize = 256,
202 .trwd = 10,
203 };
204
205 static const struct sccnxp_chip sc68681 = {
206 .name = "SC68681",
207 .nr = 2,
208 .freq_min = 1000000,
209 .freq_std = 3686400,
210 .freq_max = 4000000,
211 .flags = SCCNXP_HAVE_IO,
212 .fifosize = 3,
213 .trwd = 200,
214 };
215
216 static const struct sccnxp_chip sc68692 = {
217 .name = "SC68692",
218 .nr = 2,
219 .freq_min = 1000000,
220 .freq_std = 3686400,
221 .freq_max = 4000000,
222 .flags = SCCNXP_HAVE_IO,
223 .fifosize = 3,
224 .trwd = 200,
225 };
226
227 static u8 sccnxp_read(struct uart_port *port, u8 reg)
228 {
229 struct sccnxp_port *s = dev_get_drvdata(port->dev);
230 u8 ret;
231
232 ret = readb(port->membase + (reg << port->regshift));
233
234 ndelay(s->chip->trwd);
235
236 return ret;
237 }
238
239 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
240 {
241 struct sccnxp_port *s = dev_get_drvdata(port->dev);
242
243 writeb(v, port->membase + (reg << port->regshift));
244
245 ndelay(s->chip->trwd);
246 }
247
248 static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
249 {
250 return sccnxp_read(port, (port->line << 3) + reg);
251 }
252
253 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
254 {
255 sccnxp_write(port, (port->line << 3) + reg, v);
256 }
257
258 static int sccnxp_update_best_err(int a, int b, int *besterr)
259 {
260 int err = abs(a - b);
261
262 if (*besterr > err) {
263 *besterr = err;
264 return 0;
265 }
266
267 return 1;
268 }
269
270 static const struct {
271 u8 csr;
272 u8 acr;
273 u8 mr0;
274 int baud;
275 } baud_std[] = {
276 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
277 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
278 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
279 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
280 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
281 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
282 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
283 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
284 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
285 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
286 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
287 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
288 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
289 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
290 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
291 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
292 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
293 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
294 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
295 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
296 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
297 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
298 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
299 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
300 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
301 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
302 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
303 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
304 { 0, 0, 0, 0 }
305 };
306
307 static int sccnxp_set_baud(struct uart_port *port, int baud)
308 {
309 struct sccnxp_port *s = dev_get_drvdata(port->dev);
310 int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
311 struct sccnxp_chip *chip = s->chip;
312 u8 i, acr = 0, csr = 0, mr0 = 0;
313
314
315 div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
316 if ((div_std >= 2) && (div_std <= 0xffff)) {
317 bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
318 sccnxp_update_best_err(baud, bestbaud, &besterr);
319 csr = CSR_TIMER_MODE;
320 sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
321 sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
322
323 sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
324 }
325
326
327 for (i = 0; baud_std[i].baud && besterr; i++) {
328 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
329 continue;
330 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
331 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
332 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
333 acr = baud_std[i].acr;
334 csr = baud_std[i].csr;
335 mr0 = baud_std[i].mr0;
336 bestbaud = tmp_baud;
337 }
338 }
339
340 if (chip->flags & SCCNXP_HAVE_MR0) {
341
342 mr0 |= MR0_FIFO | MR0_TXLVL;
343
344 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
345 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
346 }
347
348 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
349 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
350
351 if (baud != bestbaud)
352 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
353 baud, bestbaud);
354
355 return bestbaud;
356 }
357
358 static void sccnxp_enable_irq(struct uart_port *port, int mask)
359 {
360 struct sccnxp_port *s = dev_get_drvdata(port->dev);
361
362 s->imr |= mask << (port->line * 4);
363 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
364 }
365
366 static void sccnxp_disable_irq(struct uart_port *port, int mask)
367 {
368 struct sccnxp_port *s = dev_get_drvdata(port->dev);
369
370 s->imr &= ~(mask << (port->line * 4));
371 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
372 }
373
374 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
375 {
376 u8 bitmask;
377 struct sccnxp_port *s = dev_get_drvdata(port->dev);
378
379 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
380 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
381 if (state)
382 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
383 else
384 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
385 }
386 }
387
388 static void sccnxp_handle_rx(struct uart_port *port)
389 {
390 u8 sr;
391 unsigned int ch, flag;
392
393 for (;;) {
394 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
395 if (!(sr & SR_RXRDY))
396 break;
397 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
398
399 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
400
401 port->icount.rx++;
402 flag = TTY_NORMAL;
403
404 if (unlikely(sr)) {
405 if (sr & SR_BRK) {
406 port->icount.brk++;
407 sccnxp_port_write(port, SCCNXP_CR_REG,
408 CR_CMD_BREAK_RESET);
409 if (uart_handle_break(port))
410 continue;
411 } else if (sr & SR_PE)
412 port->icount.parity++;
413 else if (sr & SR_FE)
414 port->icount.frame++;
415 else if (sr & SR_OVR) {
416 port->icount.overrun++;
417 sccnxp_port_write(port, SCCNXP_CR_REG,
418 CR_CMD_STATUS_RESET);
419 }
420
421 sr &= port->read_status_mask;
422 if (sr & SR_BRK)
423 flag = TTY_BREAK;
424 else if (sr & SR_PE)
425 flag = TTY_PARITY;
426 else if (sr & SR_FE)
427 flag = TTY_FRAME;
428 else if (sr & SR_OVR)
429 flag = TTY_OVERRUN;
430 }
431
432 if (uart_handle_sysrq_char(port, ch))
433 continue;
434
435 if (sr & port->ignore_status_mask)
436 continue;
437
438 uart_insert_char(port, sr, SR_OVR, ch, flag);
439 }
440
441 tty_flip_buffer_push(&port->state->port);
442 }
443
444 static void sccnxp_handle_tx(struct uart_port *port)
445 {
446 u8 sr;
447 struct circ_buf *xmit = &port->state->xmit;
448 struct sccnxp_port *s = dev_get_drvdata(port->dev);
449
450 if (unlikely(port->x_char)) {
451 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
452 port->icount.tx++;
453 port->x_char = 0;
454 return;
455 }
456
457 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
458
459 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
460 sccnxp_disable_irq(port, IMR_TXRDY);
461
462
463 if (s->chip->flags & SCCNXP_HAVE_IO)
464 sccnxp_set_bit(port, DIR_OP, 0);
465 }
466 return;
467 }
468
469 while (!uart_circ_empty(xmit)) {
470 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
471 if (!(sr & SR_TXRDY))
472 break;
473
474 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
475 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
476 port->icount.tx++;
477 }
478
479 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
480 uart_write_wakeup(port);
481 }
482
483 static void sccnxp_handle_events(struct sccnxp_port *s)
484 {
485 int i;
486 u8 isr;
487
488 do {
489 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
490 isr &= s->imr;
491 if (!isr)
492 break;
493
494 for (i = 0; i < s->uart.nr; i++) {
495 if (s->opened[i] && (isr & ISR_RXRDY(i)))
496 sccnxp_handle_rx(&s->port[i]);
497 if (s->opened[i] && (isr & ISR_TXRDY(i)))
498 sccnxp_handle_tx(&s->port[i]);
499 }
500 } while (1);
501 }
502
503 static void sccnxp_timer(struct timer_list *t)
504 {
505 struct sccnxp_port *s = from_timer(s, t, timer);
506 unsigned long flags;
507
508 spin_lock_irqsave(&s->lock, flags);
509 sccnxp_handle_events(s);
510 spin_unlock_irqrestore(&s->lock, flags);
511
512 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
513 }
514
515 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
516 {
517 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
518 unsigned long flags;
519
520 spin_lock_irqsave(&s->lock, flags);
521 sccnxp_handle_events(s);
522 spin_unlock_irqrestore(&s->lock, flags);
523
524 return IRQ_HANDLED;
525 }
526
527 static void sccnxp_start_tx(struct uart_port *port)
528 {
529 struct sccnxp_port *s = dev_get_drvdata(port->dev);
530 unsigned long flags;
531
532 spin_lock_irqsave(&s->lock, flags);
533
534
535 if (s->chip->flags & SCCNXP_HAVE_IO)
536 sccnxp_set_bit(port, DIR_OP, 1);
537
538 sccnxp_enable_irq(port, IMR_TXRDY);
539
540 spin_unlock_irqrestore(&s->lock, flags);
541 }
542
543 static void sccnxp_stop_tx(struct uart_port *port)
544 {
545
546 }
547
548 static void sccnxp_stop_rx(struct uart_port *port)
549 {
550 struct sccnxp_port *s = dev_get_drvdata(port->dev);
551 unsigned long flags;
552
553 spin_lock_irqsave(&s->lock, flags);
554 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
555 spin_unlock_irqrestore(&s->lock, flags);
556 }
557
558 static unsigned int sccnxp_tx_empty(struct uart_port *port)
559 {
560 u8 val;
561 unsigned long flags;
562 struct sccnxp_port *s = dev_get_drvdata(port->dev);
563
564 spin_lock_irqsave(&s->lock, flags);
565 val = sccnxp_port_read(port, SCCNXP_SR_REG);
566 spin_unlock_irqrestore(&s->lock, flags);
567
568 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
569 }
570
571 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
572 {
573 struct sccnxp_port *s = dev_get_drvdata(port->dev);
574 unsigned long flags;
575
576 if (!(s->chip->flags & SCCNXP_HAVE_IO))
577 return;
578
579 spin_lock_irqsave(&s->lock, flags);
580
581 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
582 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
583
584 spin_unlock_irqrestore(&s->lock, flags);
585 }
586
587 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
588 {
589 u8 bitmask, ipr;
590 unsigned long flags;
591 struct sccnxp_port *s = dev_get_drvdata(port->dev);
592 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
593
594 if (!(s->chip->flags & SCCNXP_HAVE_IO))
595 return mctrl;
596
597 spin_lock_irqsave(&s->lock, flags);
598
599 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
600
601 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
602 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
603 DSR_IP);
604 mctrl &= ~TIOCM_DSR;
605 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
606 }
607 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
608 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
609 CTS_IP);
610 mctrl &= ~TIOCM_CTS;
611 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
612 }
613 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
614 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
615 DCD_IP);
616 mctrl &= ~TIOCM_CAR;
617 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
618 }
619 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
620 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
621 RNG_IP);
622 mctrl &= ~TIOCM_RNG;
623 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
624 }
625
626 spin_unlock_irqrestore(&s->lock, flags);
627
628 return mctrl;
629 }
630
631 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
632 {
633 struct sccnxp_port *s = dev_get_drvdata(port->dev);
634 unsigned long flags;
635
636 spin_lock_irqsave(&s->lock, flags);
637 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
638 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
639 spin_unlock_irqrestore(&s->lock, flags);
640 }
641
642 static void sccnxp_set_termios(struct uart_port *port,
643 struct ktermios *termios, struct ktermios *old)
644 {
645 struct sccnxp_port *s = dev_get_drvdata(port->dev);
646 unsigned long flags;
647 u8 mr1, mr2;
648 int baud;
649
650 spin_lock_irqsave(&s->lock, flags);
651
652
653 termios->c_cflag &= ~CMSPAR;
654
655
656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
657 CR_RX_DISABLE | CR_TX_DISABLE);
658 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
659 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
660 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
661
662
663 switch (termios->c_cflag & CSIZE) {
664 case CS5:
665 mr1 = MR1_BITS_5;
666 break;
667 case CS6:
668 mr1 = MR1_BITS_6;
669 break;
670 case CS7:
671 mr1 = MR1_BITS_7;
672 break;
673 case CS8:
674 default:
675 mr1 = MR1_BITS_8;
676 break;
677 }
678
679
680 if (termios->c_cflag & PARENB) {
681 if (termios->c_cflag & PARODD)
682 mr1 |= MR1_PAR_ODD;
683 } else
684 mr1 |= MR1_PAR_NO;
685
686
687 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
688
689
690 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
691 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
692 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
693
694
695 port->read_status_mask = SR_OVR;
696 if (termios->c_iflag & INPCK)
697 port->read_status_mask |= SR_PE | SR_FE;
698 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
699 port->read_status_mask |= SR_BRK;
700
701
702 port->ignore_status_mask = 0;
703 if (termios->c_iflag & IGNBRK)
704 port->ignore_status_mask |= SR_BRK;
705 if (termios->c_iflag & IGNPAR)
706 port->ignore_status_mask |= SR_PE;
707 if (!(termios->c_cflag & CREAD))
708 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
709
710
711 baud = uart_get_baud_rate(port, termios, old, 50,
712 (s->chip->flags & SCCNXP_HAVE_MR0) ?
713 230400 : 38400);
714 baud = sccnxp_set_baud(port, baud);
715
716
717 uart_update_timeout(port, termios->c_cflag, baud);
718
719
720 if (tty_termios_baud_rate(termios))
721 tty_termios_encode_baud_rate(termios, baud, baud);
722
723
724 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
725
726 spin_unlock_irqrestore(&s->lock, flags);
727 }
728
729 static int sccnxp_startup(struct uart_port *port)
730 {
731 struct sccnxp_port *s = dev_get_drvdata(port->dev);
732 unsigned long flags;
733
734 spin_lock_irqsave(&s->lock, flags);
735
736 if (s->chip->flags & SCCNXP_HAVE_IO) {
737
738 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
739 }
740
741
742 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
743 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
744 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
745 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
746
747
748 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
749
750
751 sccnxp_enable_irq(port, IMR_RXRDY);
752
753 s->opened[port->line] = 1;
754
755 spin_unlock_irqrestore(&s->lock, flags);
756
757 return 0;
758 }
759
760 static void sccnxp_shutdown(struct uart_port *port)
761 {
762 struct sccnxp_port *s = dev_get_drvdata(port->dev);
763 unsigned long flags;
764
765 spin_lock_irqsave(&s->lock, flags);
766
767 s->opened[port->line] = 0;
768
769
770 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
771
772
773 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
774
775
776 if (s->chip->flags & SCCNXP_HAVE_IO)
777 sccnxp_set_bit(port, DIR_OP, 0);
778
779 spin_unlock_irqrestore(&s->lock, flags);
780 }
781
782 static const char *sccnxp_type(struct uart_port *port)
783 {
784 struct sccnxp_port *s = dev_get_drvdata(port->dev);
785
786 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
787 }
788
789 static void sccnxp_release_port(struct uart_port *port)
790 {
791
792 }
793
794 static int sccnxp_request_port(struct uart_port *port)
795 {
796
797 return 0;
798 }
799
800 static void sccnxp_config_port(struct uart_port *port, int flags)
801 {
802 if (flags & UART_CONFIG_TYPE)
803 port->type = PORT_SC26XX;
804 }
805
806 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
807 {
808 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
809 return 0;
810 if (s->irq == port->irq)
811 return 0;
812
813 return -EINVAL;
814 }
815
816 static const struct uart_ops sccnxp_ops = {
817 .tx_empty = sccnxp_tx_empty,
818 .set_mctrl = sccnxp_set_mctrl,
819 .get_mctrl = sccnxp_get_mctrl,
820 .stop_tx = sccnxp_stop_tx,
821 .start_tx = sccnxp_start_tx,
822 .stop_rx = sccnxp_stop_rx,
823 .break_ctl = sccnxp_break_ctl,
824 .startup = sccnxp_startup,
825 .shutdown = sccnxp_shutdown,
826 .set_termios = sccnxp_set_termios,
827 .type = sccnxp_type,
828 .release_port = sccnxp_release_port,
829 .request_port = sccnxp_request_port,
830 .config_port = sccnxp_config_port,
831 .verify_port = sccnxp_verify_port,
832 };
833
834 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
835 static void sccnxp_console_putchar(struct uart_port *port, int c)
836 {
837 int tryes = 100000;
838
839 while (tryes--) {
840 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
841 sccnxp_port_write(port, SCCNXP_THR_REG, c);
842 break;
843 }
844 barrier();
845 }
846 }
847
848 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
849 {
850 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
851 struct uart_port *port = &s->port[co->index];
852 unsigned long flags;
853
854 spin_lock_irqsave(&s->lock, flags);
855 uart_console_write(port, c, n, sccnxp_console_putchar);
856 spin_unlock_irqrestore(&s->lock, flags);
857 }
858
859 static int sccnxp_console_setup(struct console *co, char *options)
860 {
861 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
862 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
863 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
864
865 if (options)
866 uart_parse_options(options, &baud, &parity, &bits, &flow);
867
868 return uart_set_options(port, co, baud, parity, bits, flow);
869 }
870 #endif
871
872 static const struct platform_device_id sccnxp_id_table[] = {
873 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
874 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
875 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
876 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
877 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
878 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
879 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
880 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
881 { }
882 };
883 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
884
885 static int sccnxp_probe(struct platform_device *pdev)
886 {
887 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
888 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
889 int i, ret, uartclk;
890 struct sccnxp_port *s;
891 void __iomem *membase;
892 struct clk *clk;
893
894 membase = devm_ioremap_resource(&pdev->dev, res);
895 if (IS_ERR(membase))
896 return PTR_ERR(membase);
897
898 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
899 if (!s) {
900 dev_err(&pdev->dev, "Error allocating port structure\n");
901 return -ENOMEM;
902 }
903 platform_set_drvdata(pdev, s);
904
905 spin_lock_init(&s->lock);
906
907 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
908
909 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
910 if (!IS_ERR(s->regulator)) {
911 ret = regulator_enable(s->regulator);
912 if (ret) {
913 dev_err(&pdev->dev,
914 "Failed to enable regulator: %i\n", ret);
915 return ret;
916 }
917 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
918 return -EPROBE_DEFER;
919
920 clk = devm_clk_get(&pdev->dev, NULL);
921 if (IS_ERR(clk)) {
922 ret = PTR_ERR(clk);
923 if (ret == -EPROBE_DEFER)
924 goto err_out;
925 uartclk = 0;
926 } else {
927 ret = clk_prepare_enable(clk);
928 if (ret)
929 goto err_out;
930
931 ret = devm_add_action_or_reset(&pdev->dev,
932 (void(*)(void *))clk_disable_unprepare,
933 clk);
934 if (ret)
935 goto err_out;
936
937 uartclk = clk_get_rate(clk);
938 }
939
940 if (!uartclk) {
941 dev_notice(&pdev->dev, "Using default clock frequency\n");
942 uartclk = s->chip->freq_std;
943 }
944
945
946 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
947 dev_err(&pdev->dev, "Frequency out of bounds\n");
948 ret = -EINVAL;
949 goto err_out;
950 }
951
952 if (pdata)
953 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
954
955 if (s->pdata.poll_time_us) {
956 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
957 s->pdata.poll_time_us);
958 s->poll = 1;
959 }
960
961 if (!s->poll) {
962 s->irq = platform_get_irq(pdev, 0);
963 if (s->irq < 0) {
964 ret = -ENXIO;
965 goto err_out;
966 }
967 }
968
969 s->uart.owner = THIS_MODULE;
970 s->uart.dev_name = "ttySC";
971 s->uart.major = SCCNXP_MAJOR;
972 s->uart.minor = SCCNXP_MINOR;
973 s->uart.nr = s->chip->nr;
974 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
975 s->uart.cons = &s->console;
976 s->uart.cons->device = uart_console_device;
977 s->uart.cons->write = sccnxp_console_write;
978 s->uart.cons->setup = sccnxp_console_setup;
979 s->uart.cons->flags = CON_PRINTBUFFER;
980 s->uart.cons->index = -1;
981 s->uart.cons->data = s;
982 strcpy(s->uart.cons->name, "ttySC");
983 #endif
984 ret = uart_register_driver(&s->uart);
985 if (ret) {
986 dev_err(&pdev->dev, "Registering UART driver failed\n");
987 goto err_out;
988 }
989
990 for (i = 0; i < s->uart.nr; i++) {
991 s->port[i].line = i;
992 s->port[i].dev = &pdev->dev;
993 s->port[i].irq = s->irq;
994 s->port[i].type = PORT_SC26XX;
995 s->port[i].fifosize = s->chip->fifosize;
996 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
997 s->port[i].iotype = UPIO_MEM;
998 s->port[i].mapbase = res->start;
999 s->port[i].membase = membase;
1000 s->port[i].regshift = s->pdata.reg_shift;
1001 s->port[i].uartclk = uartclk;
1002 s->port[i].ops = &sccnxp_ops;
1003 uart_add_one_port(&s->uart, &s->port[i]);
1004
1005 if (s->chip->flags & SCCNXP_HAVE_IO)
1006 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
1007 }
1008
1009
1010 s->imr = 0;
1011 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
1012
1013 if (!s->poll) {
1014 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1015 sccnxp_ist,
1016 IRQF_TRIGGER_FALLING |
1017 IRQF_ONESHOT,
1018 dev_name(&pdev->dev), s);
1019 if (!ret)
1020 return 0;
1021
1022 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1023 } else {
1024 timer_setup(&s->timer, sccnxp_timer, 0);
1025 mod_timer(&s->timer, jiffies +
1026 usecs_to_jiffies(s->pdata.poll_time_us));
1027 return 0;
1028 }
1029
1030 uart_unregister_driver(&s->uart);
1031 err_out:
1032 if (!IS_ERR(s->regulator))
1033 regulator_disable(s->regulator);
1034
1035 return ret;
1036 }
1037
1038 static int sccnxp_remove(struct platform_device *pdev)
1039 {
1040 int i;
1041 struct sccnxp_port *s = platform_get_drvdata(pdev);
1042
1043 if (!s->poll)
1044 devm_free_irq(&pdev->dev, s->irq, s);
1045 else
1046 del_timer_sync(&s->timer);
1047
1048 for (i = 0; i < s->uart.nr; i++)
1049 uart_remove_one_port(&s->uart, &s->port[i]);
1050
1051 uart_unregister_driver(&s->uart);
1052
1053 if (!IS_ERR(s->regulator))
1054 return regulator_disable(s->regulator);
1055
1056 return 0;
1057 }
1058
1059 static struct platform_driver sccnxp_uart_driver = {
1060 .driver = {
1061 .name = SCCNXP_NAME,
1062 },
1063 .probe = sccnxp_probe,
1064 .remove = sccnxp_remove,
1065 .id_table = sccnxp_id_table,
1066 };
1067 module_platform_driver(sccnxp_uart_driver);
1068
1069 MODULE_LICENSE("GPL v2");
1070 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1071 MODULE_DESCRIPTION("SCCNXP serial driver");