drivers/pci/hotplug/pciehp

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This source file includes following definitions.
ctrl_dev
pciehp_request_irq
pciehp_free_irq
pcie_poll_cmd
pcie_wait_cmd
pcie_do_write_cmd
pcie_write_cmd
pcie_write_cmd_nowait
pciehp_check_link_active
pci_bus_check_dev
pciehp_check_link_status
__pciehp_link_set
pciehp_link_enable
pciehp_get_raw_indicator_status
pciehp_get_attention_status
pciehp_get_power_status
pciehp_get_latch_status
pciehp_card_present
pciehp_card_present_or_link_active
pciehp_query_power_fault
pciehp_set_raw_indicator_status
pciehp_set_indicators
pciehp_power_on_slot
pciehp_power_off_slot
pciehp_isr
pciehp_ist
pciehp_poll
pcie_enable_notification
pcie_disable_notification
pcie_clear_hotplug_events
pcie_enable_interrupt
pcie_disable_interrupt
pciehp_reset_slot
pcie_init_notification
pcie_shutdown_notification
dbg_ctrl
pcie_init
pciehp_release_ctrl
quirk_cmd_compl
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI Express PCI Hot Plug Driver
   4  *
   5  * Copyright (C) 1995,2001 Compaq Computer Corporation
   6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   7  * Copyright (C) 2001 IBM Corp.
   8  * Copyright (C) 2003-2004 Intel Corporation
   9  *
  10  * All rights reserved.
  11  *
  12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  13  */
  14 
  15 #define dev_fmt(fmt) "pciehp: " fmt
  16 
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/kthread.h>
  21 #include <linux/pci.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 
  26 #include "../pci.h"
  27 #include "pciehp.h"
  28 
  29 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  30 {
  31         return ctrl->pcie->port;
  32 }
  33 
  34 static irqreturn_t pciehp_isr(int irq, void *dev_id);
  35 static irqreturn_t pciehp_ist(int irq, void *dev_id);
  36 static int pciehp_poll(void *data);
  37 
  38 static inline int pciehp_request_irq(struct controller *ctrl)
  39 {
  40         int retval, irq = ctrl->pcie->irq;
  41 
  42         if (pciehp_poll_mode) {
  43                 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
  44                                                 "pciehp_poll-%s",
  45                                                 slot_name(ctrl));
  46                 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
  47         }
  48 
  49         /* Installs the interrupt handler */
  50         retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
  51                                       IRQF_SHARED, "pciehp", ctrl);
  52         if (retval)
  53                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  54                          irq);
  55         return retval;
  56 }
  57 
  58 static inline void pciehp_free_irq(struct controller *ctrl)
  59 {
  60         if (pciehp_poll_mode)
  61                 kthread_stop(ctrl->poll_thread);
  62         else
  63                 free_irq(ctrl->pcie->irq, ctrl);
  64 }
  65 
  66 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
  67 {
  68         struct pci_dev *pdev = ctrl_dev(ctrl);
  69         u16 slot_status;
  70 
  71         while (true) {
  72                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
  73                 if (slot_status == (u16) ~0) {
  74                         ctrl_info(ctrl, "%s: no response from device\n",
  75                                   __func__);
  76                         return 0;
  77                 }
  78 
  79                 if (slot_status & PCI_EXP_SLTSTA_CC) {
  80                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
  81                                                    PCI_EXP_SLTSTA_CC);
  82                         return 1;
  83                 }
  84                 if (timeout < 0)
  85                         break;
  86                 msleep(10);
  87                 timeout -= 10;
  88         }
  89         return 0;       /* timeout */
  90 }
  91 
  92 static void pcie_wait_cmd(struct controller *ctrl)
  93 {
  94         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
  95         unsigned long duration = msecs_to_jiffies(msecs);
  96         unsigned long cmd_timeout = ctrl->cmd_started + duration;
  97         unsigned long now, timeout;
  98         int rc;
  99 
 100         /*
 101          * If the controller does not generate notifications for command
 102          * completions, we never need to wait between writes.
 103          */
 104         if (NO_CMD_CMPL(ctrl))
 105                 return;
 106 
 107         if (!ctrl->cmd_busy)
 108                 return;
 109 
 110         /*
 111          * Even if the command has already timed out, we want to call
 112          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 113          */
 114         now = jiffies;
 115         if (time_before_eq(cmd_timeout, now))
 116                 timeout = 1;
 117         else
 118                 timeout = cmd_timeout - now;
 119 
 120         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 121             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 122                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 123         else
 124                 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
 125 
 126         if (!rc)
 127                 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 128                           ctrl->slot_ctrl,
 129                           jiffies_to_msecs(jiffies - ctrl->cmd_started));
 130 }
 131 
 132 #define CC_ERRATUM_MASK         (PCI_EXP_SLTCTL_PCC |   \
 133                                  PCI_EXP_SLTCTL_PIC |   \
 134                                  PCI_EXP_SLTCTL_AIC |   \
 135                                  PCI_EXP_SLTCTL_EIC)
 136 
 137 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 138                               u16 mask, bool wait)
 139 {
 140         struct pci_dev *pdev = ctrl_dev(ctrl);
 141         u16 slot_ctrl_orig, slot_ctrl;
 142 
 143         mutex_lock(&ctrl->ctrl_lock);
 144 
 145         /*
 146          * Always wait for any previous command that might still be in progress
 147          */
 148         pcie_wait_cmd(ctrl);
 149 
 150         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 151         if (slot_ctrl == (u16) ~0) {
 152                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 153                 goto out;
 154         }
 155 
 156         slot_ctrl_orig = slot_ctrl;
 157         slot_ctrl &= ~mask;
 158         slot_ctrl |= (cmd & mask);
 159         ctrl->cmd_busy = 1;
 160         smp_mb();
 161         ctrl->slot_ctrl = slot_ctrl;
 162         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 163         ctrl->cmd_started = jiffies;
 164 
 165         /*
 166          * Controllers with the Intel CF118 and similar errata advertise
 167          * Command Completed support, but they only set Command Completed
 168          * if we change the "Control" bits for power, power indicator,
 169          * attention indicator, or interlock.  If we only change the
 170          * "Enable" bits, they never set the Command Completed bit.
 171          */
 172         if (pdev->broken_cmd_compl &&
 173             (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
 174                 ctrl->cmd_busy = 0;
 175 
 176         /*
 177          * Optionally wait for the hardware to be ready for a new command,
 178          * indicating completion of the above issued command.
 179          */
 180         if (wait)
 181                 pcie_wait_cmd(ctrl);
 182 
 183 out:
 184         mutex_unlock(&ctrl->ctrl_lock);
 185 }
 186 
 187 /**
 188  * pcie_write_cmd - Issue controller command
 189  * @ctrl: controller to which the command is issued
 190  * @cmd:  command value written to slot control register
 191  * @mask: bitmask of slot control register to be modified
 192  */
 193 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 194 {
 195         pcie_do_write_cmd(ctrl, cmd, mask, true);
 196 }
 197 
 198 /* Same as above without waiting for the hardware to latch */
 199 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
 200 {
 201         pcie_do_write_cmd(ctrl, cmd, mask, false);
 202 }
 203 
 204 /**
 205  * pciehp_check_link_active() - Is the link active
 206  * @ctrl: PCIe hotplug controller
 207  *
 208  * Check whether the downstream link is currently active. Note it is
 209  * possible that the card is removed immediately after this so the
 210  * caller may need to take it into account.
 211  *
 212  * If the hotplug controller itself is not available anymore returns
 213  * %-ENODEV.
 214  */
 215 int pciehp_check_link_active(struct controller *ctrl)
 216 {
 217         struct pci_dev *pdev = ctrl_dev(ctrl);
 218         u16 lnk_status;
 219         int ret;
 220 
 221         ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 222         if (ret == PCIBIOS_DEVICE_NOT_FOUND || lnk_status == (u16)~0)
 223                 return -ENODEV;
 224 
 225         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 226         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 227 
 228         return ret;
 229 }
 230 
 231 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 232 {
 233         u32 l;
 234         int count = 0;
 235         int delay = 1000, step = 20;
 236         bool found = false;
 237 
 238         do {
 239                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 240                 count++;
 241 
 242                 if (found)
 243                         break;
 244 
 245                 msleep(step);
 246                 delay -= step;
 247         } while (delay > 0);
 248 
 249         if (count > 1)
 250                 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 251                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 252                         PCI_FUNC(devfn), count, step, l);
 253 
 254         return found;
 255 }
 256 
 257 int pciehp_check_link_status(struct controller *ctrl)
 258 {
 259         struct pci_dev *pdev = ctrl_dev(ctrl);
 260         bool found;
 261         u16 lnk_status;
 262 
 263         if (!pcie_wait_for_link(pdev, true))
 264                 return -1;
 265 
 266         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 267                                         PCI_DEVFN(0, 0));
 268 
 269         /* ignore link or presence changes up to this point */
 270         if (found)
 271                 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
 272                            &ctrl->pending_events);
 273 
 274         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 275         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 276         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 277             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 278                 ctrl_err(ctrl, "link training error: status %#06x\n",
 279                          lnk_status);
 280                 return -1;
 281         }
 282 
 283         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 284 
 285         if (!found)
 286                 return -1;
 287 
 288         return 0;
 289 }
 290 
 291 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 292 {
 293         struct pci_dev *pdev = ctrl_dev(ctrl);
 294         u16 lnk_ctrl;
 295 
 296         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 297 
 298         if (enable)
 299                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 300         else
 301                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 302 
 303         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 304         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 305         return 0;
 306 }
 307 
 308 static int pciehp_link_enable(struct controller *ctrl)
 309 {
 310         return __pciehp_link_set(ctrl, true);
 311 }
 312 
 313 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 314                                     u8 *status)
 315 {
 316         struct controller *ctrl = to_ctrl(hotplug_slot);
 317         struct pci_dev *pdev = ctrl_dev(ctrl);
 318         u16 slot_ctrl;
 319 
 320         pci_config_pm_runtime_get(pdev);
 321         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 322         pci_config_pm_runtime_put(pdev);
 323         *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
 324         return 0;
 325 }
 326 
 327 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
 328 {
 329         struct controller *ctrl = to_ctrl(hotplug_slot);
 330         struct pci_dev *pdev = ctrl_dev(ctrl);
 331         u16 slot_ctrl;
 332 
 333         pci_config_pm_runtime_get(pdev);
 334         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 335         pci_config_pm_runtime_put(pdev);
 336         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 337                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 338 
 339         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 340         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 341                 *status = 1;    /* On */
 342                 break;
 343         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 344                 *status = 2;    /* Blink */
 345                 break;
 346         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 347                 *status = 0;    /* Off */
 348                 break;
 349         default:
 350                 *status = 0xFF;
 351                 break;
 352         }
 353 
 354         return 0;
 355 }
 356 
 357 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
 358 {
 359         struct pci_dev *pdev = ctrl_dev(ctrl);
 360         u16 slot_ctrl;
 361 
 362         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 363         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 364                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 365 
 366         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 367         case PCI_EXP_SLTCTL_PWR_ON:
 368                 *status = 1;    /* On */
 369                 break;
 370         case PCI_EXP_SLTCTL_PWR_OFF:
 371                 *status = 0;    /* Off */
 372                 break;
 373         default:
 374                 *status = 0xFF;
 375                 break;
 376         }
 377 }
 378 
 379 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
 380 {
 381         struct pci_dev *pdev = ctrl_dev(ctrl);
 382         u16 slot_status;
 383 
 384         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 385         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 386 }
 387 
 388 /**
 389  * pciehp_card_present() - Is the card present
 390  * @ctrl: PCIe hotplug controller
 391  *
 392  * Function checks whether the card is currently present in the slot and
 393  * in that case returns true. Note it is possible that the card is
 394  * removed immediately after the check so the caller may need to take
 395  * this into account.
 396  *
 397  * It the hotplug controller itself is not available anymore returns
 398  * %-ENODEV.
 399  */
 400 int pciehp_card_present(struct controller *ctrl)
 401 {
 402         struct pci_dev *pdev = ctrl_dev(ctrl);
 403         u16 slot_status;
 404         int ret;
 405 
 406         ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 407         if (ret == PCIBIOS_DEVICE_NOT_FOUND || slot_status == (u16)~0)
 408                 return -ENODEV;
 409 
 410         return !!(slot_status & PCI_EXP_SLTSTA_PDS);
 411 }
 412 
 413 /**
 414  * pciehp_card_present_or_link_active() - whether given slot is occupied
 415  * @ctrl: PCIe hotplug controller
 416  *
 417  * Unlike pciehp_card_present(), which determines presence solely from the
 418  * Presence Detect State bit, this helper also returns true if the Link Active
 419  * bit is set.  This is a concession to broken hotplug ports which hardwire
 420  * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
 421  *
 422  * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
 423  *          port is not present anymore returns %-ENODEV.
 424  */
 425 int pciehp_card_present_or_link_active(struct controller *ctrl)
 426 {
 427         int ret;
 428 
 429         ret = pciehp_card_present(ctrl);
 430         if (ret)
 431                 return ret;
 432 
 433         return pciehp_check_link_active(ctrl);
 434 }
 435 
 436 int pciehp_query_power_fault(struct controller *ctrl)
 437 {
 438         struct pci_dev *pdev = ctrl_dev(ctrl);
 439         u16 slot_status;
 440 
 441         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 442         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 443 }
 444 
 445 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 446                                     u8 status)
 447 {
 448         struct controller *ctrl = to_ctrl(hotplug_slot);
 449         struct pci_dev *pdev = ctrl_dev(ctrl);
 450 
 451         pci_config_pm_runtime_get(pdev);
 452         pcie_write_cmd_nowait(ctrl, status << 6,
 453                               PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
 454         pci_config_pm_runtime_put(pdev);
 455         return 0;
 456 }
 457 
 458 /**
 459  * pciehp_set_indicators() - set attention indicator, power indicator, or both
 460  * @ctrl: PCIe hotplug controller
 461  * @pwr: one of:
 462  *      PCI_EXP_SLTCTL_PWR_IND_ON
 463  *      PCI_EXP_SLTCTL_PWR_IND_BLINK
 464  *      PCI_EXP_SLTCTL_PWR_IND_OFF
 465  * @attn: one of:
 466  *      PCI_EXP_SLTCTL_ATTN_IND_ON
 467  *      PCI_EXP_SLTCTL_ATTN_IND_BLINK
 468  *      PCI_EXP_SLTCTL_ATTN_IND_OFF
 469  *
 470  * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
 471  * unchanged.
 472  */
 473 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
 474 {
 475         u16 cmd = 0, mask = 0;
 476 
 477         if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
 478                 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
 479                 mask |= PCI_EXP_SLTCTL_PIC;
 480         }
 481 
 482         if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
 483                 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
 484                 mask |= PCI_EXP_SLTCTL_AIC;
 485         }
 486 
 487         if (cmd) {
 488                 pcie_write_cmd_nowait(ctrl, cmd, mask);
 489                 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 490                          pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 491         }
 492 }
 493 
 494 int pciehp_power_on_slot(struct controller *ctrl)
 495 {
 496         struct pci_dev *pdev = ctrl_dev(ctrl);
 497         u16 slot_status;
 498         int retval;
 499 
 500         /* Clear power-fault bit from previous power failures */
 501         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 502         if (slot_status & PCI_EXP_SLTSTA_PFD)
 503                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 504                                            PCI_EXP_SLTSTA_PFD);
 505         ctrl->power_fault_detected = 0;
 506 
 507         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 508         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 509                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 510                  PCI_EXP_SLTCTL_PWR_ON);
 511 
 512         retval = pciehp_link_enable(ctrl);
 513         if (retval)
 514                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 515 
 516         return retval;
 517 }
 518 
 519 void pciehp_power_off_slot(struct controller *ctrl)
 520 {
 521         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 522         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 523                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 524                  PCI_EXP_SLTCTL_PWR_OFF);
 525 }
 526 
 527 static irqreturn_t pciehp_isr(int irq, void *dev_id)
 528 {
 529         struct controller *ctrl = (struct controller *)dev_id;
 530         struct pci_dev *pdev = ctrl_dev(ctrl);
 531         struct device *parent = pdev->dev.parent;
 532         u16 status, events;
 533 
 534         /*
 535          * Interrupts only occur in D3hot or shallower and only if enabled
 536          * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
 537          */
 538         if (pdev->current_state == PCI_D3cold ||
 539             (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
 540                 return IRQ_NONE;
 541 
 542         /*
 543          * Keep the port accessible by holding a runtime PM ref on its parent.
 544          * Defer resume of the parent to the IRQ thread if it's suspended.
 545          * Mask the interrupt until then.
 546          */
 547         if (parent) {
 548                 pm_runtime_get_noresume(parent);
 549                 if (!pm_runtime_active(parent)) {
 550                         pm_runtime_put(parent);
 551                         disable_irq_nosync(irq);
 552                         atomic_or(RERUN_ISR, &ctrl->pending_events);
 553                         return IRQ_WAKE_THREAD;
 554                 }
 555         }
 556 
 557         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
 558         if (status == (u16) ~0) {
 559                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 560                 if (parent)
 561                         pm_runtime_put(parent);
 562                 return IRQ_NONE;
 563         }
 564 
 565         /*
 566          * Slot Status contains plain status bits as well as event
 567          * notification bits; right now we only want the event bits.
 568          */
 569         events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 570                            PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
 571                            PCI_EXP_SLTSTA_DLLSC);
 572 
 573         /*
 574          * If we've already reported a power fault, don't report it again
 575          * until we've done something to handle it.
 576          */
 577         if (ctrl->power_fault_detected)
 578                 events &= ~PCI_EXP_SLTSTA_PFD;
 579 
 580         if (!events) {
 581                 if (parent)
 582                         pm_runtime_put(parent);
 583                 return IRQ_NONE;
 584         }
 585 
 586         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
 587         ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
 588         if (parent)
 589                 pm_runtime_put(parent);
 590 
 591         /*
 592          * Command Completed notifications are not deferred to the
 593          * IRQ thread because it may be waiting for their arrival.
 594          */
 595         if (events & PCI_EXP_SLTSTA_CC) {
 596                 ctrl->cmd_busy = 0;
 597                 smp_mb();
 598                 wake_up(&ctrl->queue);
 599 
 600                 if (events == PCI_EXP_SLTSTA_CC)
 601                         return IRQ_HANDLED;
 602 
 603                 events &= ~PCI_EXP_SLTSTA_CC;
 604         }
 605 
 606         if (pdev->ignore_hotplug) {
 607                 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
 608                 return IRQ_HANDLED;
 609         }
 610 
 611         /* Save pending events for consumption by IRQ thread. */
 612         atomic_or(events, &ctrl->pending_events);
 613         return IRQ_WAKE_THREAD;
 614 }
 615 
 616 static irqreturn_t pciehp_ist(int irq, void *dev_id)
 617 {
 618         struct controller *ctrl = (struct controller *)dev_id;
 619         struct pci_dev *pdev = ctrl_dev(ctrl);
 620         irqreturn_t ret;
 621         u32 events;
 622 
 623         ctrl->ist_running = true;
 624         pci_config_pm_runtime_get(pdev);
 625 
 626         /* rerun pciehp_isr() if the port was inaccessible on interrupt */
 627         if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
 628                 ret = pciehp_isr(irq, dev_id);
 629                 enable_irq(irq);
 630                 if (ret != IRQ_WAKE_THREAD)
 631                         goto out;
 632         }
 633 
 634         synchronize_hardirq(irq);
 635         events = atomic_xchg(&ctrl->pending_events, 0);
 636         if (!events) {
 637                 ret = IRQ_NONE;
 638                 goto out;
 639         }
 640 
 641         /* Check Attention Button Pressed */
 642         if (events & PCI_EXP_SLTSTA_ABP) {
 643                 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
 644                           slot_name(ctrl));
 645                 pciehp_handle_button_press(ctrl);
 646         }
 647 
 648         /* Check Power Fault Detected */
 649         if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 650                 ctrl->power_fault_detected = 1;
 651                 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
 652                 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
 653                                       PCI_EXP_SLTCTL_ATTN_IND_ON);
 654         }
 655 
 656         /*
 657          * Disable requests have higher priority than Presence Detect Changed
 658          * or Data Link Layer State Changed events.
 659          */
 660         down_read(&ctrl->reset_lock);
 661         if (events & DISABLE_SLOT)
 662                 pciehp_handle_disable_request(ctrl);
 663         else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
 664                 pciehp_handle_presence_or_link_change(ctrl, events);
 665         up_read(&ctrl->reset_lock);
 666 
 667         ret = IRQ_HANDLED;
 668 out:
 669         pci_config_pm_runtime_put(pdev);
 670         ctrl->ist_running = false;
 671         wake_up(&ctrl->requester);
 672         return ret;
 673 }
 674 
 675 static int pciehp_poll(void *data)
 676 {
 677         struct controller *ctrl = data;
 678 
 679         schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
 680 
 681         while (!kthread_should_stop()) {
 682                 /* poll for interrupt events or user requests */
 683                 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
 684                        atomic_read(&ctrl->pending_events))
 685                         pciehp_ist(IRQ_NOTCONNECTED, ctrl);
 686 
 687                 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
 688                         pciehp_poll_time = 2; /* clamp to sane value */
 689 
 690                 schedule_timeout_idle(pciehp_poll_time * HZ);
 691         }
 692 
 693         return 0;
 694 }
 695 
 696 static void pcie_enable_notification(struct controller *ctrl)
 697 {
 698         u16 cmd, mask;
 699 
 700         /*
 701          * TBD: Power fault detected software notification support.
 702          *
 703          * Power fault detected software notification is not enabled
 704          * now, because it caused power fault detected interrupt storm
 705          * on some machines. On those machines, power fault detected
 706          * bit in the slot status register was set again immediately
 707          * when it is cleared in the interrupt service routine, and
 708          * next power fault detected interrupt was notified again.
 709          */
 710 
 711         /*
 712          * Always enable link events: thus link-up and link-down shall
 713          * always be treated as hotplug and unplug respectively. Enable
 714          * presence detect only if Attention Button is not present.
 715          */
 716         cmd = PCI_EXP_SLTCTL_DLLSCE;
 717         if (ATTN_BUTTN(ctrl))
 718                 cmd |= PCI_EXP_SLTCTL_ABPE;
 719         else
 720                 cmd |= PCI_EXP_SLTCTL_PDCE;
 721         if (!pciehp_poll_mode)
 722                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 723 
 724         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 725                 PCI_EXP_SLTCTL_PFDE |
 726                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 727                 PCI_EXP_SLTCTL_DLLSCE);
 728 
 729         pcie_write_cmd_nowait(ctrl, cmd, mask);
 730         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 731                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 732 }
 733 
 734 static void pcie_disable_notification(struct controller *ctrl)
 735 {
 736         u16 mask;
 737 
 738         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 739                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 740                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 741                 PCI_EXP_SLTCTL_DLLSCE);
 742         pcie_write_cmd(ctrl, 0, mask);
 743         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 744                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 745 }
 746 
 747 void pcie_clear_hotplug_events(struct controller *ctrl)
 748 {
 749         pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
 750                                    PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
 751 }
 752 
 753 void pcie_enable_interrupt(struct controller *ctrl)
 754 {
 755         u16 mask;
 756 
 757         mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
 758         pcie_write_cmd(ctrl, mask, mask);
 759 }
 760 
 761 void pcie_disable_interrupt(struct controller *ctrl)
 762 {
 763         u16 mask;
 764 
 765         /*
 766          * Mask hot-plug interrupt to prevent it triggering immediately
 767          * when the link goes inactive (we still get PME when any of the
 768          * enabled events is detected). Same goes with Link Layer State
 769          * changed event which generates PME immediately when the link goes
 770          * inactive so mask it as well.
 771          */
 772         mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
 773         pcie_write_cmd(ctrl, 0, mask);
 774 }
 775 
 776 /*
 777  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 778  * bus reset of the bridge, but at the same time we want to ensure that it is
 779  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 780  * disable link state notification and presence detection change notification
 781  * momentarily, if we see that they could interfere. Also, clear any spurious
 782  * events after.
 783  */
 784 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe)
 785 {
 786         struct controller *ctrl = to_ctrl(hotplug_slot);
 787         struct pci_dev *pdev = ctrl_dev(ctrl);
 788         u16 stat_mask = 0, ctrl_mask = 0;
 789         int rc;
 790 
 791         if (probe)
 792                 return 0;
 793 
 794         down_write(&ctrl->reset_lock);
 795 
 796         if (!ATTN_BUTTN(ctrl)) {
 797                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 798                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 799         }
 800         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 801         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 802 
 803         pcie_write_cmd(ctrl, 0, ctrl_mask);
 804         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 805                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 806 
 807         rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
 808 
 809         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 810         pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
 811         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 812                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
 813 
 814         up_write(&ctrl->reset_lock);
 815         return rc;
 816 }
 817 
 818 int pcie_init_notification(struct controller *ctrl)
 819 {
 820         if (pciehp_request_irq(ctrl))
 821                 return -1;
 822         pcie_enable_notification(ctrl);
 823         ctrl->notification_enabled = 1;
 824         return 0;
 825 }
 826 
 827 void pcie_shutdown_notification(struct controller *ctrl)
 828 {
 829         if (ctrl->notification_enabled) {
 830                 pcie_disable_notification(ctrl);
 831                 pciehp_free_irq(ctrl);
 832                 ctrl->notification_enabled = 0;
 833         }
 834 }
 835 
 836 static inline void dbg_ctrl(struct controller *ctrl)
 837 {
 838         struct pci_dev *pdev = ctrl->pcie->port;
 839         u16 reg16;
 840 
 841         ctrl_dbg(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 842         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 843         ctrl_dbg(ctrl, "Slot Status            : 0x%04x\n", reg16);
 844         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 845         ctrl_dbg(ctrl, "Slot Control           : 0x%04x\n", reg16);
 846 }
 847 
 848 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 849 
 850 struct controller *pcie_init(struct pcie_device *dev)
 851 {
 852         struct controller *ctrl;
 853         u32 slot_cap, link_cap;
 854         u8 poweron;
 855         struct pci_dev *pdev = dev->port;
 856         struct pci_bus *subordinate = pdev->subordinate;
 857 
 858         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 859         if (!ctrl)
 860                 return NULL;
 861 
 862         ctrl->pcie = dev;
 863         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 864 
 865         if (pdev->hotplug_user_indicators)
 866                 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
 867 
 868         /*
 869          * We assume no Thunderbolt controllers support Command Complete events,
 870          * but some controllers falsely claim they do.
 871          */
 872         if (pdev->is_thunderbolt)
 873                 slot_cap |= PCI_EXP_SLTCAP_NCCS;
 874 
 875         ctrl->slot_cap = slot_cap;
 876         mutex_init(&ctrl->ctrl_lock);
 877         mutex_init(&ctrl->state_lock);
 878         init_rwsem(&ctrl->reset_lock);
 879         init_waitqueue_head(&ctrl->requester);
 880         init_waitqueue_head(&ctrl->queue);
 881         INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
 882         dbg_ctrl(ctrl);
 883 
 884         down_read(&pci_bus_sem);
 885         ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
 886         up_read(&pci_bus_sem);
 887 
 888         /* Check if Data Link Layer Link Active Reporting is implemented */
 889         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 890 
 891         /* Clear all remaining event bits in Slot Status register. */
 892         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 893                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 894                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
 895                 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
 896 
 897         ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
 898                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 899                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 900                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 901                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 902                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 903                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 904                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
 905                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
 906                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 907                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 908                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
 909                 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
 910 
 911         /*
 912          * If empty slot's power status is on, turn power off.  The IRQ isn't
 913          * requested yet, so avoid triggering a notification with this command.
 914          */
 915         if (POWER_CTRL(ctrl)) {
 916                 pciehp_get_power_status(ctrl, &poweron);
 917                 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
 918                         pcie_disable_notification(ctrl);
 919                         pciehp_power_off_slot(ctrl);
 920                 }
 921         }
 922 
 923         return ctrl;
 924 }
 925 
 926 void pciehp_release_ctrl(struct controller *ctrl)
 927 {
 928         cancel_delayed_work_sync(&ctrl->button_work);
 929         kfree(ctrl);
 930 }
 931 
 932 static void quirk_cmd_compl(struct pci_dev *pdev)
 933 {
 934         u32 slot_cap;
 935 
 936         if (pci_is_pcie(pdev)) {
 937                 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 938                 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
 939                     !(slot_cap & PCI_EXP_SLTCAP_NCCS))
 940                         pdev->broken_cmd_compl = 1;
 941         }
 942 }
 943 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
 944                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
 945 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
 946                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
 947 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
 948                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
 949 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
 950                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pci/hotplug/pciehp_hpc.c

DEFINITIONS
