drivers/pci/controller/pci-mvebu.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
mvebu_writel
mvebu_readl
mvebu_has_ioport
mvebu_pcie_link_up
mvebu_pcie_set_local_bus_nr
mvebu_pcie_set_local_dev_nr
mvebu_pcie_setup_wins
mvebu_pcie_setup_hw
mvebu_pcie_hw_rd_conf
mvebu_pcie_hw_wr_conf
mvebu_pcie_del_windows
mvebu_pcie_add_windows
mvebu_pcie_set_window
mvebu_pcie_handle_iobase_change
mvebu_pcie_handle_membase_change
mvebu_pci_bridge_emul_pcie_conf_read
mvebu_pci_bridge_emul_base_conf_write
mvebu_pci_bridge_emul_pcie_conf_write
mvebu_pci_bridge_emul_init
sys_to_pcie
mvebu_pcie_find_port
mvebu_pcie_wr_conf
mvebu_pcie_rd_conf
mvebu_pcie_align_resource
mvebu_pcie_map_registers
mvebu_get_tgt_attr
mvebu_pcie_suspend
mvebu_pcie_resume
mvebu_pcie_port_clk_put
mvebu_pcie_parse_port
mvebu_pcie_powerup
mvebu_pcie_powerdown
mvebu_pcie_parse_request_resources
mvebu_pci_host_probe
mvebu_pcie_probe
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCIe driver for Marvell Armada 370 and Armada XP SoCs
   4  *
   5  * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   6  */
   7 
   8 #include <linux/kernel.h>
   9 #include <linux/pci.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/gpio.h>
  13 #include <linux/init.h>
  14 #include <linux/mbus.h>
  15 #include <linux/msi.h>
  16 #include <linux/slab.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/of_pci.h>
  22 #include <linux/of_platform.h>
  23 
  24 #include "../pci.h"
  25 #include "../pci-bridge-emul.h"
  26 
  27 /*
  28  * PCIe unit register offsets.
  29  */
  30 #define PCIE_DEV_ID_OFF         0x0000
  31 #define PCIE_CMD_OFF            0x0004
  32 #define PCIE_DEV_REV_OFF        0x0008
  33 #define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
  34 #define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
  35 #define PCIE_CAP_PCIEXP         0x0060
  36 #define PCIE_HEADER_LOG_4_OFF   0x0128
  37 #define PCIE_BAR_CTRL_OFF(n)    (0x1804 + (((n) - 1) * 4))
  38 #define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
  39 #define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
  40 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  41 #define PCIE_WIN5_CTRL_OFF      0x1880
  42 #define PCIE_WIN5_BASE_OFF      0x1884
  43 #define PCIE_WIN5_REMAP_OFF     0x188c
  44 #define PCIE_CONF_ADDR_OFF      0x18f8
  45 #define  PCIE_CONF_ADDR_EN              0x80000000
  46 #define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  47 #define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
  48 #define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
  49 #define  PCIE_CONF_FUNC(f)              (((f) & 0x7) << 8)
  50 #define  PCIE_CONF_ADDR(bus, devfn, where) \
  51         (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
  52          PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
  53          PCIE_CONF_ADDR_EN)
  54 #define PCIE_CONF_DATA_OFF      0x18fc
  55 #define PCIE_MASK_OFF           0x1910
  56 #define  PCIE_MASK_ENABLE_INTS          0x0f000000
  57 #define PCIE_CTRL_OFF           0x1a00
  58 #define  PCIE_CTRL_X1_MODE              0x0001
  59 #define PCIE_STAT_OFF           0x1a04
  60 #define  PCIE_STAT_BUS                  0xff00
  61 #define  PCIE_STAT_DEV                  0x1f0000
  62 #define  PCIE_STAT_LINK_DOWN            BIT(0)
  63 #define PCIE_RC_RTSTA           0x1a14
  64 #define PCIE_DEBUG_CTRL         0x1a60
  65 #define  PCIE_DEBUG_SOFT_RESET          BIT(20)
  66 
  67 struct mvebu_pcie_port;
  68 
  69 /* Structure representing all PCIe interfaces */
  70 struct mvebu_pcie {
  71         struct platform_device *pdev;
  72         struct mvebu_pcie_port *ports;
  73         struct msi_controller *msi;
  74         struct list_head resources;
  75         struct resource io;
  76         struct resource realio;
  77         struct resource mem;
  78         struct resource busn;
  79         int nports;
  80 };
  81 
  82 struct mvebu_pcie_window {
  83         phys_addr_t base;
  84         phys_addr_t remap;
  85         size_t size;
  86 };
  87 
  88 /* Structure representing one PCIe interface */
  89 struct mvebu_pcie_port {
  90         char *name;
  91         void __iomem *base;
  92         u32 port;
  93         u32 lane;
  94         int devfn;
  95         unsigned int mem_target;
  96         unsigned int mem_attr;
  97         unsigned int io_target;
  98         unsigned int io_attr;
  99         struct clk *clk;
 100         struct gpio_desc *reset_gpio;
 101         char *reset_name;
 102         struct pci_bridge_emul bridge;
 103         struct device_node *dn;
 104         struct mvebu_pcie *pcie;
 105         struct mvebu_pcie_window memwin;
 106         struct mvebu_pcie_window iowin;
 107         u32 saved_pcie_stat;
 108 };
 109 
 110 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
 111 {
 112         writel(val, port->base + reg);
 113 }
 114 
 115 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
 116 {
 117         return readl(port->base + reg);
 118 }
 119 
 120 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
 121 {
 122         return port->io_target != -1 && port->io_attr != -1;
 123 }
 124 
 125 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
 126 {
 127         return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
 128 }
 129 
 130 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
 131 {
 132         u32 stat;
 133 
 134         stat = mvebu_readl(port, PCIE_STAT_OFF);
 135         stat &= ~PCIE_STAT_BUS;
 136         stat |= nr << 8;
 137         mvebu_writel(port, stat, PCIE_STAT_OFF);
 138 }
 139 
 140 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
 141 {
 142         u32 stat;
 143 
 144         stat = mvebu_readl(port, PCIE_STAT_OFF);
 145         stat &= ~PCIE_STAT_DEV;
 146         stat |= nr << 16;
 147         mvebu_writel(port, stat, PCIE_STAT_OFF);
 148 }
 149 
 150 /*
 151  * Setup PCIE BARs and Address Decode Wins:
 152  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
 153  * WIN[0-3] -> DRAM bank[0-3]
 154  */
 155 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
 156 {
 157         const struct mbus_dram_target_info *dram;
 158         u32 size;
 159         int i;
 160 
 161         dram = mv_mbus_dram_info();
 162 
 163         /* First, disable and clear BARs and windows. */
 164         for (i = 1; i < 3; i++) {
 165                 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
 166                 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
 167                 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
 168         }
 169 
 170         for (i = 0; i < 5; i++) {
 171                 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
 172                 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
 173                 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
 174         }
 175 
 176         mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
 177         mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
 178         mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
 179 
 180         /* Setup windows for DDR banks.  Count total DDR size on the fly. */
 181         size = 0;
 182         for (i = 0; i < dram->num_cs; i++) {
 183                 const struct mbus_dram_window *cs = dram->cs + i;
 184 
 185                 mvebu_writel(port, cs->base & 0xffff0000,
 186                              PCIE_WIN04_BASE_OFF(i));
 187                 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
 188                 mvebu_writel(port,
 189                              ((cs->size - 1) & 0xffff0000) |
 190                              (cs->mbus_attr << 8) |
 191                              (dram->mbus_dram_target_id << 4) | 1,
 192                              PCIE_WIN04_CTRL_OFF(i));
 193 
 194                 size += cs->size;
 195         }
 196 
 197         /* Round up 'size' to the nearest power of two. */
 198         if ((size & (size - 1)) != 0)
 199                 size = 1 << fls(size);
 200 
 201         /* Setup BAR[1] to all DRAM banks. */
 202         mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
 203         mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
 204         mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
 205                      PCIE_BAR_CTRL_OFF(1));
 206 }
 207 
 208 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
 209 {
 210         u32 cmd, mask;
 211 
 212         /* Point PCIe unit MBUS decode windows to DRAM space. */
 213         mvebu_pcie_setup_wins(port);
 214 
 215         /* Master + slave enable. */
 216         cmd = mvebu_readl(port, PCIE_CMD_OFF);
 217         cmd |= PCI_COMMAND_IO;
 218         cmd |= PCI_COMMAND_MEMORY;
 219         cmd |= PCI_COMMAND_MASTER;
 220         mvebu_writel(port, cmd, PCIE_CMD_OFF);
 221 
 222         /* Enable interrupt lines A-D. */
 223         mask = mvebu_readl(port, PCIE_MASK_OFF);
 224         mask |= PCIE_MASK_ENABLE_INTS;
 225         mvebu_writel(port, mask, PCIE_MASK_OFF);
 226 }
 227 
 228 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
 229                                  struct pci_bus *bus,
 230                                  u32 devfn, int where, int size, u32 *val)
 231 {
 232         void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
 233 
 234         mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
 235                      PCIE_CONF_ADDR_OFF);
 236 
 237         switch (size) {
 238         case 1:
 239                 *val = readb_relaxed(conf_data + (where & 3));
 240                 break;
 241         case 2:
 242                 *val = readw_relaxed(conf_data + (where & 2));
 243                 break;
 244         case 4:
 245                 *val = readl_relaxed(conf_data);
 246                 break;
 247         }
 248 
 249         return PCIBIOS_SUCCESSFUL;
 250 }
 251 
 252 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
 253                                  struct pci_bus *bus,
 254                                  u32 devfn, int where, int size, u32 val)
 255 {
 256         void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
 257 
 258         mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
 259                      PCIE_CONF_ADDR_OFF);
 260 
 261         switch (size) {
 262         case 1:
 263                 writeb(val, conf_data + (where & 3));
 264                 break;
 265         case 2:
 266                 writew(val, conf_data + (where & 2));
 267                 break;
 268         case 4:
 269                 writel(val, conf_data);
 270                 break;
 271         default:
 272                 return PCIBIOS_BAD_REGISTER_NUMBER;
 273         }
 274 
 275         return PCIBIOS_SUCCESSFUL;
 276 }
 277 
 278 /*
 279  * Remove windows, starting from the largest ones to the smallest
 280  * ones.
 281  */
 282 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
 283                                    phys_addr_t base, size_t size)
 284 {
 285         while (size) {
 286                 size_t sz = 1 << (fls(size) - 1);
 287 
 288                 mvebu_mbus_del_window(base, sz);
 289                 base += sz;
 290                 size -= sz;
 291         }
 292 }
 293 
 294 /*
 295  * MBus windows can only have a power of two size, but PCI BARs do not
 296  * have this constraint. Therefore, we have to split the PCI BAR into
 297  * areas each having a power of two size. We start from the largest
 298  * one (i.e highest order bit set in the size).
 299  */
 300 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
 301                                    unsigned int target, unsigned int attribute,
 302                                    phys_addr_t base, size_t size,
 303                                    phys_addr_t remap)
 304 {
 305         size_t size_mapped = 0;
 306 
 307         while (size) {
 308                 size_t sz = 1 << (fls(size) - 1);
 309                 int ret;
 310 
 311                 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
 312                                                         sz, remap);
 313                 if (ret) {
 314                         phys_addr_t end = base + sz - 1;
 315 
 316                         dev_err(&port->pcie->pdev->dev,
 317                                 "Could not create MBus window at [mem %pa-%pa]: %d\n",
 318                                 &base, &end, ret);
 319                         mvebu_pcie_del_windows(port, base - size_mapped,
 320                                                size_mapped);
 321                         return;
 322                 }
 323 
 324                 size -= sz;
 325                 size_mapped += sz;
 326                 base += sz;
 327                 if (remap != MVEBU_MBUS_NO_REMAP)
 328                         remap += sz;
 329         }
 330 }
 331 
 332 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
 333                                   unsigned int target, unsigned int attribute,
 334                                   const struct mvebu_pcie_window *desired,
 335                                   struct mvebu_pcie_window *cur)
 336 {
 337         if (desired->base == cur->base && desired->remap == cur->remap &&
 338             desired->size == cur->size)
 339                 return;
 340 
 341         if (cur->size != 0) {
 342                 mvebu_pcie_del_windows(port, cur->base, cur->size);
 343                 cur->size = 0;
 344                 cur->base = 0;
 345 
 346                 /*
 347                  * If something tries to change the window while it is enabled
 348                  * the change will not be done atomically. That would be
 349                  * difficult to do in the general case.
 350                  */
 351         }
 352 
 353         if (desired->size == 0)
 354                 return;
 355 
 356         mvebu_pcie_add_windows(port, target, attribute, desired->base,
 357                                desired->size, desired->remap);
 358         *cur = *desired;
 359 }
 360 
 361 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
 362 {
 363         struct mvebu_pcie_window desired = {};
 364         struct pci_bridge_emul_conf *conf = &port->bridge.conf;
 365 
 366         /* Are the new iobase/iolimit values invalid? */
 367         if (conf->iolimit < conf->iobase ||
 368             conf->iolimitupper < conf->iobaseupper ||
 369             !(conf->command & PCI_COMMAND_IO)) {
 370                 mvebu_pcie_set_window(port, port->io_target, port->io_attr,
 371                                       &desired, &port->iowin);
 372                 return;
 373         }
 374 
 375         if (!mvebu_has_ioport(port)) {
 376                 dev_WARN(&port->pcie->pdev->dev,
 377                          "Attempt to set IO when IO is disabled\n");
 378                 return;
 379         }
 380 
 381         /*
 382          * We read the PCI-to-PCI bridge emulated registers, and
 383          * calculate the base address and size of the address decoding
 384          * window to setup, according to the PCI-to-PCI bridge
 385          * specifications. iobase is the bus address, port->iowin_base
 386          * is the CPU address.
 387          */
 388         desired.remap = ((conf->iobase & 0xF0) << 8) |
 389                         (conf->iobaseupper << 16);
 390         desired.base = port->pcie->io.start + desired.remap;
 391         desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) |
 392                          (conf->iolimitupper << 16)) -
 393                         desired.remap) +
 394                        1;
 395 
 396         mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
 397                               &port->iowin);
 398 }
 399 
 400 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
 401 {
 402         struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
 403         struct pci_bridge_emul_conf *conf = &port->bridge.conf;
 404 
 405         /* Are the new membase/memlimit values invalid? */
 406         if (conf->memlimit < conf->membase ||
 407             !(conf->command & PCI_COMMAND_MEMORY)) {
 408                 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
 409                                       &desired, &port->memwin);
 410                 return;
 411         }
 412 
 413         /*
 414          * We read the PCI-to-PCI bridge emulated registers, and
 415          * calculate the base address and size of the address decoding
 416          * window to setup, according to the PCI-to-PCI bridge
 417          * specifications.
 418          */
 419         desired.base = ((conf->membase & 0xFFF0) << 16);
 420         desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
 421                        desired.base + 1;
 422 
 423         mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
 424                               &port->memwin);
 425 }
 426 
 427 static pci_bridge_emul_read_status_t
 428 mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
 429                                      int reg, u32 *value)
 430 {
 431         struct mvebu_pcie_port *port = bridge->data;
 432 
 433         switch (reg) {
 434         case PCI_EXP_DEVCAP:
 435                 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
 436                 break;
 437 
 438         case PCI_EXP_DEVCTL:
 439                 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
 440                                  ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
 441                                    PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
 442                 break;
 443 
 444         case PCI_EXP_LNKCAP:
 445                 /*
 446                  * PCIe requires the clock power management capability to be
 447                  * hard-wired to zero for downstream ports
 448                  */
 449                 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
 450                          ~PCI_EXP_LNKCAP_CLKPM;
 451                 break;
 452 
 453         case PCI_EXP_LNKCTL:
 454                 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
 455                 break;
 456 
 457         case PCI_EXP_SLTCTL:
 458                 *value = PCI_EXP_SLTSTA_PDS << 16;
 459                 break;
 460 
 461         case PCI_EXP_RTSTA:
 462                 *value = mvebu_readl(port, PCIE_RC_RTSTA);
 463                 break;
 464 
 465         default:
 466                 return PCI_BRIDGE_EMUL_NOT_HANDLED;
 467         }
 468 
 469         return PCI_BRIDGE_EMUL_HANDLED;
 470 }
 471 
 472 static void
 473 mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
 474                                       int reg, u32 old, u32 new, u32 mask)
 475 {
 476         struct mvebu_pcie_port *port = bridge->data;
 477         struct pci_bridge_emul_conf *conf = &bridge->conf;
 478 
 479         switch (reg) {
 480         case PCI_COMMAND:
 481         {
 482                 if (!mvebu_has_ioport(port))
 483                         conf->command &= ~PCI_COMMAND_IO;
 484 
 485                 if ((old ^ new) & PCI_COMMAND_IO)
 486                         mvebu_pcie_handle_iobase_change(port);
 487                 if ((old ^ new) & PCI_COMMAND_MEMORY)
 488                         mvebu_pcie_handle_membase_change(port);
 489 
 490                 break;
 491         }
 492 
 493         case PCI_IO_BASE:
 494                 /*
 495                  * We keep bit 1 set, it is a read-only bit that
 496                  * indicates we support 32 bits addressing for the
 497                  * I/O
 498                  */
 499                 conf->iobase |= PCI_IO_RANGE_TYPE_32;
 500                 conf->iolimit |= PCI_IO_RANGE_TYPE_32;
 501                 mvebu_pcie_handle_iobase_change(port);
 502                 break;
 503 
 504         case PCI_MEMORY_BASE:
 505                 mvebu_pcie_handle_membase_change(port);
 506                 break;
 507 
 508         case PCI_IO_BASE_UPPER16:
 509                 mvebu_pcie_handle_iobase_change(port);
 510                 break;
 511 
 512         case PCI_PRIMARY_BUS:
 513                 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
 514                 break;
 515 
 516         default:
 517                 break;
 518         }
 519 }
 520 
 521 static void
 522 mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
 523                                       int reg, u32 old, u32 new, u32 mask)
 524 {
 525         struct mvebu_pcie_port *port = bridge->data;
 526 
 527         switch (reg) {
 528         case PCI_EXP_DEVCTL:
 529                 /*
 530                  * Armada370 data says these bits must always
 531                  * be zero when in root complex mode.
 532                  */
 533                 new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
 534                          PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
 535 
 536                 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
 537                 break;
 538 
 539         case PCI_EXP_LNKCTL:
 540                 /*
 541                  * If we don't support CLKREQ, we must ensure that the
 542                  * CLKREQ enable bit always reads zero.  Since we haven't
 543                  * had this capability, and it's dependent on board wiring,
 544                  * disable it for the time being.
 545                  */
 546                 new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
 547 
 548                 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
 549                 break;
 550 
 551         case PCI_EXP_RTSTA:
 552                 mvebu_writel(port, new, PCIE_RC_RTSTA);
 553                 break;
 554         }
 555 }
 556 
 557 struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
 558         .write_base = mvebu_pci_bridge_emul_base_conf_write,
 559         .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
 560         .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
 561 };
 562 
 563 /*
 564  * Initialize the configuration space of the PCI-to-PCI bridge
 565  * associated with the given PCIe interface.
 566  */
 567 static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
 568 {
 569         struct pci_bridge_emul *bridge = &port->bridge;
 570 
 571         bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
 572         bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
 573         bridge->conf.class_revision =
 574                 mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
 575 
 576         if (mvebu_has_ioport(port)) {
 577                 /* We support 32 bits I/O addressing */
 578                 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
 579                 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
 580         }
 581 
 582         bridge->has_pcie = true;
 583         bridge->data = port;
 584         bridge->ops = &mvebu_pci_bridge_emul_ops;
 585 
 586         pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
 587 }
 588 
 589 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
 590 {
 591         return sys->private_data;
 592 }
 593 
 594 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
 595                                                     struct pci_bus *bus,
 596                                                     int devfn)
 597 {
 598         int i;
 599 
 600         for (i = 0; i < pcie->nports; i++) {
 601                 struct mvebu_pcie_port *port = &pcie->ports[i];
 602 
 603                 if (bus->number == 0 && port->devfn == devfn)
 604                         return port;
 605                 if (bus->number != 0 &&
 606                     bus->number >= port->bridge.conf.secondary_bus &&
 607                     bus->number <= port->bridge.conf.subordinate_bus)
 608                         return port;
 609         }
 610 
 611         return NULL;
 612 }
 613 
 614 /* PCI configuration space write function */
 615 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 616                               int where, int size, u32 val)
 617 {
 618         struct mvebu_pcie *pcie = bus->sysdata;
 619         struct mvebu_pcie_port *port;
 620         int ret;
 621 
 622         port = mvebu_pcie_find_port(pcie, bus, devfn);
 623         if (!port)
 624                 return PCIBIOS_DEVICE_NOT_FOUND;
 625 
 626         /* Access the emulated PCI-to-PCI bridge */
 627         if (bus->number == 0)
 628                 return pci_bridge_emul_conf_write(&port->bridge, where,
 629                                                   size, val);
 630 
 631         if (!mvebu_pcie_link_up(port))
 632                 return PCIBIOS_DEVICE_NOT_FOUND;
 633 
 634         /* Access the real PCIe interface */
 635         ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
 636                                     where, size, val);
 637 
 638         return ret;
 639 }
 640 
 641 /* PCI configuration space read function */
 642 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 643                               int size, u32 *val)
 644 {
 645         struct mvebu_pcie *pcie = bus->sysdata;
 646         struct mvebu_pcie_port *port;
 647         int ret;
 648 
 649         port = mvebu_pcie_find_port(pcie, bus, devfn);
 650         if (!port) {
 651                 *val = 0xffffffff;
 652                 return PCIBIOS_DEVICE_NOT_FOUND;
 653         }
 654 
 655         /* Access the emulated PCI-to-PCI bridge */
 656         if (bus->number == 0)
 657                 return pci_bridge_emul_conf_read(&port->bridge, where,
 658                                                  size, val);
 659 
 660         if (!mvebu_pcie_link_up(port)) {
 661                 *val = 0xffffffff;
 662                 return PCIBIOS_DEVICE_NOT_FOUND;
 663         }
 664 
 665         /* Access the real PCIe interface */
 666         ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
 667                                     where, size, val);
 668 
 669         return ret;
 670 }
 671 
 672 static struct pci_ops mvebu_pcie_ops = {
 673         .read = mvebu_pcie_rd_conf,
 674         .write = mvebu_pcie_wr_conf,
 675 };
 676 
 677 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
 678                                                  const struct resource *res,
 679                                                  resource_size_t start,
 680                                                  resource_size_t size,
 681                                                  resource_size_t align)
 682 {
 683         if (dev->bus->number != 0)
 684                 return start;
 685 
 686         /*
 687          * On the PCI-to-PCI bridge side, the I/O windows must have at
 688          * least a 64 KB size and the memory windows must have at
 689          * least a 1 MB size. Moreover, MBus windows need to have a
 690          * base address aligned on their size, and their size must be
 691          * a power of two. This means that if the BAR doesn't have a
 692          * power of two size, several MBus windows will actually be
 693          * created. We need to ensure that the biggest MBus window
 694          * (which will be the first one) is aligned on its size, which
 695          * explains the rounddown_pow_of_two() being done here.
 696          */
 697         if (res->flags & IORESOURCE_IO)
 698                 return round_up(start, max_t(resource_size_t, SZ_64K,
 699                                              rounddown_pow_of_two(size)));
 700         else if (res->flags & IORESOURCE_MEM)
 701                 return round_up(start, max_t(resource_size_t, SZ_1M,
 702                                              rounddown_pow_of_two(size)));
 703         else
 704                 return start;
 705 }
 706 
 707 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
 708                                               struct device_node *np,
 709                                               struct mvebu_pcie_port *port)
 710 {
 711         struct resource regs;
 712         int ret = 0;
 713 
 714         ret = of_address_to_resource(np, 0, &regs);
 715         if (ret)
 716                 return ERR_PTR(ret);
 717 
 718         return devm_ioremap_resource(&pdev->dev, &regs);
 719 }
 720 
 721 #define DT_FLAGS_TO_TYPE(flags)       (((flags) >> 24) & 0x03)
 722 #define    DT_TYPE_IO                 0x1
 723 #define    DT_TYPE_MEM32              0x2
 724 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
 725 #define DT_CPUADDR_TO_ATTR(cpuaddr)   (((cpuaddr) >> 48) & 0xFF)
 726 
 727 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
 728                               unsigned long type,
 729                               unsigned int *tgt,
 730                               unsigned int *attr)
 731 {
 732         const int na = 3, ns = 2;
 733         const __be32 *range;
 734         int rlen, nranges, rangesz, pna, i;
 735 
 736         *tgt = -1;
 737         *attr = -1;
 738 
 739         range = of_get_property(np, "ranges", &rlen);
 740         if (!range)
 741                 return -EINVAL;
 742 
 743         pna = of_n_addr_cells(np);
 744         rangesz = pna + na + ns;
 745         nranges = rlen / sizeof(__be32) / rangesz;
 746 
 747         for (i = 0; i < nranges; i++, range += rangesz) {
 748                 u32 flags = of_read_number(range, 1);
 749                 u32 slot = of_read_number(range + 1, 1);
 750                 u64 cpuaddr = of_read_number(range + na, pna);
 751                 unsigned long rtype;
 752 
 753                 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
 754                         rtype = IORESOURCE_IO;
 755                 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
 756                         rtype = IORESOURCE_MEM;
 757                 else
 758                         continue;
 759 
 760                 if (slot == PCI_SLOT(devfn) && type == rtype) {
 761                         *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
 762                         *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
 763                         return 0;
 764                 }
 765         }
 766 
 767         return -ENOENT;
 768 }
 769 
 770 #ifdef CONFIG_PM_SLEEP
 771 static int mvebu_pcie_suspend(struct device *dev)
 772 {
 773         struct mvebu_pcie *pcie;
 774         int i;
 775 
 776         pcie = dev_get_drvdata(dev);
 777         for (i = 0; i < pcie->nports; i++) {
 778                 struct mvebu_pcie_port *port = pcie->ports + i;
 779                 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
 780         }
 781 
 782         return 0;
 783 }
 784 
 785 static int mvebu_pcie_resume(struct device *dev)
 786 {
 787         struct mvebu_pcie *pcie;
 788         int i;
 789 
 790         pcie = dev_get_drvdata(dev);
 791         for (i = 0; i < pcie->nports; i++) {
 792                 struct mvebu_pcie_port *port = pcie->ports + i;
 793                 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
 794                 mvebu_pcie_setup_hw(port);
 795         }
 796 
 797         return 0;
 798 }
 799 #endif
 800 
 801 static void mvebu_pcie_port_clk_put(void *data)
 802 {
 803         struct mvebu_pcie_port *port = data;
 804 
 805         clk_put(port->clk);
 806 }
 807 
 808 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
 809         struct mvebu_pcie_port *port, struct device_node *child)
 810 {
 811         struct device *dev = &pcie->pdev->dev;
 812         enum of_gpio_flags flags;
 813         int reset_gpio, ret;
 814 
 815         port->pcie = pcie;
 816 
 817         if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
 818                 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
 819                          child);
 820                 goto skip;
 821         }
 822 
 823         if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
 824                 port->lane = 0;
 825 
 826         port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
 827                                     port->lane);
 828         if (!port->name) {
 829                 ret = -ENOMEM;
 830                 goto err;
 831         }
 832 
 833         port->devfn = of_pci_get_devfn(child);
 834         if (port->devfn < 0)
 835                 goto skip;
 836 
 837         ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
 838                                  &port->mem_target, &port->mem_attr);
 839         if (ret < 0) {
 840                 dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
 841                         port->name);
 842                 goto skip;
 843         }
 844 
 845         if (resource_size(&pcie->io) != 0) {
 846                 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
 847                                    &port->io_target, &port->io_attr);
 848         } else {
 849                 port->io_target = -1;
 850                 port->io_attr = -1;
 851         }
 852 
 853         reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
 854         if (reset_gpio == -EPROBE_DEFER) {
 855                 ret = reset_gpio;
 856                 goto err;
 857         }
 858 
 859         if (gpio_is_valid(reset_gpio)) {
 860                 unsigned long gpio_flags;
 861 
 862                 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
 863                                                   port->name);
 864                 if (!port->reset_name) {
 865                         ret = -ENOMEM;
 866                         goto err;
 867                 }
 868 
 869                 if (flags & OF_GPIO_ACTIVE_LOW) {
 870                         dev_info(dev, "%pOF: reset gpio is active low\n",
 871                                  child);
 872                         gpio_flags = GPIOF_ACTIVE_LOW |
 873                                      GPIOF_OUT_INIT_LOW;
 874                 } else {
 875                         gpio_flags = GPIOF_OUT_INIT_HIGH;
 876                 }
 877 
 878                 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
 879                                             port->reset_name);
 880                 if (ret) {
 881                         if (ret == -EPROBE_DEFER)
 882                                 goto err;
 883                         goto skip;
 884                 }
 885 
 886                 port->reset_gpio = gpio_to_desc(reset_gpio);
 887         }
 888 
 889         port->clk = of_clk_get_by_name(child, NULL);
 890         if (IS_ERR(port->clk)) {
 891                 dev_err(dev, "%s: cannot get clock\n", port->name);
 892                 goto skip;
 893         }
 894 
 895         ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
 896         if (ret < 0) {
 897                 clk_put(port->clk);
 898                 goto err;
 899         }
 900 
 901         return 1;
 902 
 903 skip:
 904         ret = 0;
 905 
 906         /* In the case of skipping, we need to free these */
 907         devm_kfree(dev, port->reset_name);
 908         port->reset_name = NULL;
 909         devm_kfree(dev, port->name);
 910         port->name = NULL;
 911 
 912 err:
 913         return ret;
 914 }
 915 
 916 /*
 917  * Power up a PCIe port.  PCIe requires the refclk to be stable for 100µs
 918  * prior to releasing PERST.  See table 2-4 in section 2.6.2 AC Specifications
 919  * of the PCI Express Card Electromechanical Specification, 1.1.
 920  */
 921 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
 922 {
 923         int ret;
 924 
 925         ret = clk_prepare_enable(port->clk);
 926         if (ret < 0)
 927                 return ret;
 928 
 929         if (port->reset_gpio) {
 930                 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
 931 
 932                 of_property_read_u32(port->dn, "reset-delay-us",
 933                                      &reset_udelay);
 934 
 935                 udelay(100);
 936 
 937                 gpiod_set_value_cansleep(port->reset_gpio, 0);
 938                 msleep(reset_udelay / 1000);
 939         }
 940 
 941         return 0;
 942 }
 943 
 944 /*
 945  * Power down a PCIe port.  Strictly, PCIe requires us to place the card
 946  * in D3hot state before asserting PERST#.
 947  */
 948 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
 949 {
 950         gpiod_set_value_cansleep(port->reset_gpio, 1);
 951 
 952         clk_disable_unprepare(port->clk);
 953 }
 954 
 955 /*
 956  * We can't use devm_of_pci_get_host_bridge_resources() because we
 957  * need to parse our special DT properties encoding the MEM and IO
 958  * apertures.
 959  */
 960 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 961 {
 962         struct device *dev = &pcie->pdev->dev;
 963         struct device_node *np = dev->of_node;
 964         int ret;
 965 
 966         INIT_LIST_HEAD(&pcie->resources);
 967 
 968         /* Get the bus range */
 969         ret = of_pci_parse_bus_range(np, &pcie->busn);
 970         if (ret) {
 971                 dev_err(dev, "failed to parse bus-range property: %d\n", ret);
 972                 return ret;
 973         }
 974         pci_add_resource(&pcie->resources, &pcie->busn);
 975 
 976         /* Get the PCIe memory aperture */
 977         mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
 978         if (resource_size(&pcie->mem) == 0) {
 979                 dev_err(dev, "invalid memory aperture size\n");
 980                 return -EINVAL;
 981         }
 982 
 983         pcie->mem.name = "PCI MEM";
 984         pci_add_resource(&pcie->resources, &pcie->mem);
 985 
 986         /* Get the PCIe IO aperture */
 987         mvebu_mbus_get_pcie_io_aperture(&pcie->io);
 988 
 989         if (resource_size(&pcie->io) != 0) {
 990                 pcie->realio.flags = pcie->io.flags;
 991                 pcie->realio.start = PCIBIOS_MIN_IO;
 992                 pcie->realio.end = min_t(resource_size_t,
 993                                          IO_SPACE_LIMIT - SZ_64K,
 994                                          resource_size(&pcie->io) - 1);
 995                 pcie->realio.name = "PCI I/O";
 996 
 997                 pci_add_resource(&pcie->resources, &pcie->realio);
 998         }
 999 
1000         return devm_request_pci_bus_resources(dev, &pcie->resources);
1001 }
1002 
1003 /*
1004  * This is a copy of pci_host_probe(), except that it does the I/O
1005  * remap as the last step, once we are sure we won't fail.
1006  *
1007  * It should be removed once the I/O remap error handling issue has
1008  * been sorted out.
1009  */
1010 static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
1011 {
1012         struct mvebu_pcie *pcie;
1013         struct pci_bus *bus, *child;
1014         int ret;
1015 
1016         ret = pci_scan_root_bus_bridge(bridge);
1017         if (ret < 0) {
1018                 dev_err(bridge->dev.parent, "Scanning root bridge failed");
1019                 return ret;
1020         }
1021 
1022         pcie = pci_host_bridge_priv(bridge);
1023         if (resource_size(&pcie->io) != 0) {
1024                 unsigned int i;
1025 
1026                 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
1027                         pci_ioremap_io(i, pcie->io.start + i);
1028         }
1029 
1030         bus = bridge->bus;
1031 
1032         /*
1033          * We insert PCI resources into the iomem_resource and
1034          * ioport_resource trees in either pci_bus_claim_resources()
1035          * or pci_bus_assign_resources().
1036          */
1037         if (pci_has_flag(PCI_PROBE_ONLY)) {
1038                 pci_bus_claim_resources(bus);
1039         } else {
1040                 pci_bus_size_bridges(bus);
1041                 pci_bus_assign_resources(bus);
1042 
1043                 list_for_each_entry(child, &bus->children, node)
1044                         pcie_bus_configure_settings(child);
1045         }
1046 
1047         pci_bus_add_devices(bus);
1048         return 0;
1049 }
1050 
1051 static int mvebu_pcie_probe(struct platform_device *pdev)
1052 {
1053         struct device *dev = &pdev->dev;
1054         struct mvebu_pcie *pcie;
1055         struct pci_host_bridge *bridge;
1056         struct device_node *np = dev->of_node;
1057         struct device_node *child;
1058         int num, i, ret;
1059 
1060         bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie));
1061         if (!bridge)
1062                 return -ENOMEM;
1063 
1064         pcie = pci_host_bridge_priv(bridge);
1065         pcie->pdev = pdev;
1066         platform_set_drvdata(pdev, pcie);
1067 
1068         ret = mvebu_pcie_parse_request_resources(pcie);
1069         if (ret)
1070                 return ret;
1071 
1072         num = of_get_available_child_count(np);
1073 
1074         pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
1075         if (!pcie->ports)
1076                 return -ENOMEM;
1077 
1078         i = 0;
1079         for_each_available_child_of_node(np, child) {
1080                 struct mvebu_pcie_port *port = &pcie->ports[i];
1081 
1082                 ret = mvebu_pcie_parse_port(pcie, port, child);
1083                 if (ret < 0) {
1084                         of_node_put(child);
1085                         return ret;
1086                 } else if (ret == 0) {
1087                         continue;
1088                 }
1089 
1090                 port->dn = child;
1091                 i++;
1092         }
1093         pcie->nports = i;
1094 
1095         for (i = 0; i < pcie->nports; i++) {
1096                 struct mvebu_pcie_port *port = &pcie->ports[i];
1097 
1098                 child = port->dn;
1099                 if (!child)
1100                         continue;
1101 
1102                 ret = mvebu_pcie_powerup(port);
1103                 if (ret < 0)
1104                         continue;
1105 
1106                 port->base = mvebu_pcie_map_registers(pdev, child, port);
1107                 if (IS_ERR(port->base)) {
1108                         dev_err(dev, "%s: cannot map registers\n", port->name);
1109                         port->base = NULL;
1110                         mvebu_pcie_powerdown(port);
1111                         continue;
1112                 }
1113 
1114                 mvebu_pcie_setup_hw(port);
1115                 mvebu_pcie_set_local_dev_nr(port, 1);
1116                 mvebu_pci_bridge_emul_init(port);
1117         }
1118 
1119         pcie->nports = i;
1120 
1121         list_splice_init(&pcie->resources, &bridge->windows);
1122         bridge->dev.parent = dev;
1123         bridge->sysdata = pcie;
1124         bridge->busnr = 0;
1125         bridge->ops = &mvebu_pcie_ops;
1126         bridge->map_irq = of_irq_parse_and_map_pci;
1127         bridge->swizzle_irq = pci_common_swizzle;
1128         bridge->align_resource = mvebu_pcie_align_resource;
1129         bridge->msi = pcie->msi;
1130 
1131         return mvebu_pci_host_probe(bridge);
1132 }
1133 
1134 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1135         { .compatible = "marvell,armada-xp-pcie", },
1136         { .compatible = "marvell,armada-370-pcie", },
1137         { .compatible = "marvell,dove-pcie", },
1138         { .compatible = "marvell,kirkwood-pcie", },
1139         {},
1140 };
1141 
1142 static const struct dev_pm_ops mvebu_pcie_pm_ops = {
1143         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume)
1144 };
1145 
1146 static struct platform_driver mvebu_pcie_driver = {
1147         .driver = {
1148                 .name = "mvebu-pcie",
1149                 .of_match_table = mvebu_pcie_of_match_table,
1150                 /* driver unloading/unbinding currently not supported */
1151                 .suppress_bind_attrs = true,
1152                 .pm = &mvebu_pcie_pm_ops,
1153         },
1154         .probe = mvebu_pcie_probe,
1155 };
1156 builtin_platform_driver(mvebu_pcie_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pci/controller/pci-mvebu.c

DEFINITIONS
