This source file includes following definitions.
- to_tegra_pcie
- appl_writel
- appl_readl
- apply_bad_link_workaround
- tegra_pcie_rp_irq_handler
- tegra_pcie_irq_handler
- tegra_pcie_dw_rd_own_conf
- tegra_pcie_dw_wr_own_conf
- disable_aspm_l11
- disable_aspm_l12
- event_counter_prog
- aspm_state_cnt
- init_host_aspm
- init_debugfs
- disable_aspm_l12
- disable_aspm_l11
- init_host_aspm
- init_debugfs
- tegra_pcie_enable_system_interrupts
- tegra_pcie_enable_legacy_interrupts
- tegra_pcie_enable_msi_interrupts
- tegra_pcie_enable_interrupts
- config_gen3_gen4_eq_presets
- tegra_pcie_prepare_host
- tegra_pcie_dw_host_init
- tegra_pcie_dw_link_up
- tegra_pcie_set_msi_vec_num
- tegra_pcie_disable_phy
- tegra_pcie_enable_phy
- tegra_pcie_dw_parse_dt
- tegra_pcie_bpmp_set_ctrl_state
- tegra_pcie_downstream_dev_to_D0
- tegra_pcie_get_slot_regulators
- tegra_pcie_enable_slot_regulators
- tegra_pcie_disable_slot_regulators
- tegra_pcie_config_controller
- __deinit_controller
- tegra_pcie_init_controller
- tegra_pcie_try_link_l2
- tegra_pcie_dw_pme_turnoff
- tegra_pcie_deinit_controller
- tegra_pcie_config_rp
- tegra_pcie_dw_probe
- tegra_pcie_dw_remove
- tegra_pcie_dw_suspend_late
- tegra_pcie_dw_suspend_noirq
- tegra_pcie_dw_resume_noirq
- tegra_pcie_dw_resume_early
- tegra_pcie_dw_shutdown
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10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/interrupt.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_pci.h>
23 #include <linux/pci.h>
24 #include <linux/phy/phy.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/random.h>
29 #include <linux/reset.h>
30 #include <linux/resource.h>
31 #include <linux/types.h>
32 #include "pcie-designware.h"
33 #include <soc/tegra/bpmp.h>
34 #include <soc/tegra/bpmp-abi.h>
35 #include "../../pci.h"
36
37 #define APPL_PINMUX 0x0
38 #define APPL_PINMUX_PEX_RST BIT(0)
39 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2)
40 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3)
41 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4)
42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5)
43 #define APPL_PINMUX_CLKREQ_OUT_OVRD_EN BIT(9)
44 #define APPL_PINMUX_CLKREQ_OUT_OVRD BIT(10)
45
46 #define APPL_CTRL 0x4
47 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6)
48 #define APPL_CTRL_LTSSM_EN BIT(7)
49 #define APPL_CTRL_HW_HOT_RST_EN BIT(20)
50 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
51 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22
52 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
53
54 #define APPL_INTR_EN_L0_0 0x8
55 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0)
56 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4)
57 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8)
58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19)
59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30)
60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31)
61
62 #define APPL_INTR_STATUS_L0 0xC
63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0)
64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8)
65 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18)
66
67 #define APPL_INTR_EN_L1_0_0 0x1C
68 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
69
70 #define APPL_INTR_STATUS_L1_0_0 0x20
71 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
72
73 #define APPL_INTR_STATUS_L1_1 0x2C
74 #define APPL_INTR_STATUS_L1_2 0x30
75 #define APPL_INTR_STATUS_L1_3 0x34
76 #define APPL_INTR_STATUS_L1_6 0x3C
77 #define APPL_INTR_STATUS_L1_7 0x40
78
79 #define APPL_INTR_EN_L1_8_0 0x44
80 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2)
81 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3)
82 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11)
83 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15)
84
85 #define APPL_INTR_STATUS_L1_8_0 0x4C
86 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6)
87 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2)
88 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3)
89
90 #define APPL_INTR_STATUS_L1_9 0x54
91 #define APPL_INTR_STATUS_L1_10 0x58
92 #define APPL_INTR_STATUS_L1_11 0x64
93 #define APPL_INTR_STATUS_L1_13 0x74
94 #define APPL_INTR_STATUS_L1_14 0x78
95 #define APPL_INTR_STATUS_L1_15 0x7C
96 #define APPL_INTR_STATUS_L1_17 0x88
97
98 #define APPL_INTR_EN_L1_18 0x90
99 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2)
100 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
101 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
102
103 #define APPL_INTR_STATUS_L1_18 0x94
104 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2)
105 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
106 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
107
108 #define APPL_MSI_CTRL_2 0xB0
109
110 #define APPL_LTR_MSG_1 0xC4
111 #define LTR_MSG_REQ BIT(15)
112 #define LTR_MST_NO_SNOOP_SHIFT 16
113
114 #define APPL_LTR_MSG_2 0xC8
115 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3)
116
117 #define APPL_LINK_STATUS 0xCC
118 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0)
119
120 #define APPL_DEBUG 0xD0
121 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21)
122 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11
123 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)
124 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3
125 #define LTSSM_STATE_PRE_DETECT 5
126
127 #define APPL_RADM_STATUS 0xE4
128 #define APPL_PM_XMT_TURNOFF_STATE BIT(0)
129
130 #define APPL_DM_TYPE 0x100
131 #define APPL_DM_TYPE_MASK GENMASK(3, 0)
132 #define APPL_DM_TYPE_RP 0x4
133 #define APPL_DM_TYPE_EP 0x0
134
135 #define APPL_CFG_BASE_ADDR 0x104
136 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12)
137
138 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108
139 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18)
140
141 #define APPL_CFG_MISC 0x110
142 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14)
143 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10)
144 #define APPL_CFG_MISC_ARCACHE_SHIFT 10
145 #define APPL_CFG_MISC_ARCACHE_VAL 3
146
147 #define APPL_CFG_SLCG_OVERRIDE 0x114
148 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0)
149
150 #define APPL_CAR_RESET_OVRD 0x12C
151 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0)
152
153 #define IO_BASE_IO_DECODE BIT(0)
154 #define IO_BASE_IO_DECODE_BIT8 BIT(8)
155
156 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0)
157 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16)
158
159 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718
160 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19)
161
162 #define EVENT_COUNTER_ALL_CLEAR 0x3
163 #define EVENT_COUNTER_ENABLE_ALL 0x7
164 #define EVENT_COUNTER_ENABLE_SHIFT 2
165 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
166 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16
167 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2
168 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3
169 #define EVENT_COUNTER_EVENT_L1 0x5
170 #define EVENT_COUNTER_EVENT_L1_1 0x7
171 #define EVENT_COUNTER_EVENT_L1_2 0x8
172 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24
173 #define EVENT_COUNTER_GROUP_5 0x5
174
175 #define PORT_LOGIC_ACK_F_ASPM_CTRL 0x70C
176 #define ENTER_ASPM BIT(30)
177 #define L0S_ENTRANCE_LAT_SHIFT 24
178 #define L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
179 #define L1_ENTRANCE_LAT_SHIFT 27
180 #define L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
181 #define N_FTS_SHIFT 8
182 #define N_FTS_MASK GENMASK(7, 0)
183 #define N_FTS_VAL 52
184
185 #define PORT_LOGIC_GEN2_CTRL 0x80C
186 #define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17)
187 #define FTS_MASK GENMASK(7, 0)
188 #define FTS_VAL 52
189
190 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
191
192 #define GEN3_EQ_CONTROL_OFF 0x8a8
193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8
194 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
195 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
196
197 #define GEN3_RELATED_OFF 0x890
198 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
199 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
201 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
202
203 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
204 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
205 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
206 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0
207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1
208 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2
209
210 #define PORT_LOGIC_MSIX_DOORBELL 0x948
211
212 #define CAP_SPCIE_CAP_OFF 0x154
213 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0)
214 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8)
215 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8
216
217 #define PME_ACK_TIMEOUT 10000
218
219 #define LTSSM_TIMEOUT 50000
220
221 #define GEN3_GEN4_EQ_PRESET_INIT 5
222
223 #define GEN1_CORE_CLK_FREQ 62500000
224 #define GEN2_CORE_CLK_FREQ 125000000
225 #define GEN3_CORE_CLK_FREQ 250000000
226 #define GEN4_CORE_CLK_FREQ 500000000
227
228 static const unsigned int pcie_gen_freq[] = {
229 GEN1_CORE_CLK_FREQ,
230 GEN2_CORE_CLK_FREQ,
231 GEN3_CORE_CLK_FREQ,
232 GEN4_CORE_CLK_FREQ
233 };
234
235 static const u32 event_cntr_ctrl_offset[] = {
236 0x1d8,
237 0x1a8,
238 0x1a8,
239 0x1a8,
240 0x1c4,
241 0x1d8
242 };
243
244 static const u32 event_cntr_data_offset[] = {
245 0x1dc,
246 0x1ac,
247 0x1ac,
248 0x1ac,
249 0x1c8,
250 0x1dc
251 };
252
253 struct tegra_pcie_dw {
254 struct device *dev;
255 struct resource *appl_res;
256 struct resource *dbi_res;
257 struct resource *atu_dma_res;
258 void __iomem *appl_base;
259 struct clk *core_clk;
260 struct reset_control *core_apb_rst;
261 struct reset_control *core_rst;
262 struct dw_pcie pci;
263 struct tegra_bpmp *bpmp;
264
265 bool supports_clkreq;
266 bool enable_cdm_check;
267 bool link_state;
268 bool update_fc_fixup;
269 u8 init_link_width;
270 u32 msi_ctrl_int;
271 u32 num_lanes;
272 u32 max_speed;
273 u32 cid;
274 u32 cfg_link_cap_l1sub;
275 u32 pcie_cap_base;
276 u32 aspm_cmrt;
277 u32 aspm_pwr_on_t;
278 u32 aspm_l0s_enter_lat;
279
280 struct regulator *pex_ctl_supply;
281 struct regulator *slot_ctl_3v3;
282 struct regulator *slot_ctl_12v;
283
284 unsigned int phy_count;
285 struct phy **phys;
286
287 struct dentry *debugfs;
288 };
289
290 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
291 {
292 return container_of(pci, struct tegra_pcie_dw, pci);
293 }
294
295 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
296 const u32 reg)
297 {
298 writel_relaxed(value, pcie->appl_base + reg);
299 }
300
301 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
302 {
303 return readl_relaxed(pcie->appl_base + reg);
304 }
305
306 struct tegra_pcie_soc {
307 enum dw_pcie_device_mode mode;
308 };
309
310 static void apply_bad_link_workaround(struct pcie_port *pp)
311 {
312 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
313 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
314 u32 current_link_width;
315 u16 val;
316
317
318
319
320
321
322 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
323 if (val & PCI_EXP_LNKSTA_LBMS) {
324 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
325 PCI_EXP_LNKSTA_NLW_SHIFT;
326 if (pcie->init_link_width > current_link_width) {
327 dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
328 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
329 PCI_EXP_LNKCTL2);
330 val &= ~PCI_EXP_LNKCTL2_TLS;
331 val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
332 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
333 PCI_EXP_LNKCTL2, val);
334
335 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
336 PCI_EXP_LNKCTL);
337 val |= PCI_EXP_LNKCTL_RL;
338 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
339 PCI_EXP_LNKCTL, val);
340 }
341 }
342 }
343
344 static irqreturn_t tegra_pcie_rp_irq_handler(struct tegra_pcie_dw *pcie)
345 {
346 struct dw_pcie *pci = &pcie->pci;
347 struct pcie_port *pp = &pci->pp;
348 u32 val, tmp;
349 u16 val_w;
350
351 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
352 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
353 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
354 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
355 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
356
357
358 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
359 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
360 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
361 udelay(1);
362 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
363 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
364 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
365
366 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
367 val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE;
368 dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
369 }
370 }
371
372 if (val & APPL_INTR_STATUS_L0_INT_INT) {
373 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
374 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
375 appl_writel(pcie,
376 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
377 APPL_INTR_STATUS_L1_8_0);
378 apply_bad_link_workaround(pp);
379 }
380 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
381 appl_writel(pcie,
382 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
383 APPL_INTR_STATUS_L1_8_0);
384
385 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
386 PCI_EXP_LNKSTA);
387 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w &
388 PCI_EXP_LNKSTA_CLS);
389 }
390 }
391
392 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
393 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
394 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
395 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
396 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
397 dev_info(pci->dev, "CDM check complete\n");
398 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
399 }
400 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
401 dev_err(pci->dev, "CDM comparison mismatch\n");
402 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
403 }
404 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
405 dev_err(pci->dev, "CDM Logic error\n");
406 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
407 }
408 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
409 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
410 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
411 }
412
413 return IRQ_HANDLED;
414 }
415
416 static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
417 {
418 struct tegra_pcie_dw *pcie = arg;
419
420 return tegra_pcie_rp_irq_handler(pcie);
421 }
422
423 static int tegra_pcie_dw_rd_own_conf(struct pcie_port *pp, int where, int size,
424 u32 *val)
425 {
426 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
427
428
429
430
431
432
433
434 if (where == PORT_LOGIC_MSIX_DOORBELL) {
435 *val = 0x00000000;
436 return PCIBIOS_SUCCESSFUL;
437 }
438
439 return dw_pcie_read(pci->dbi_base + where, size, val);
440 }
441
442 static int tegra_pcie_dw_wr_own_conf(struct pcie_port *pp, int where, int size,
443 u32 val)
444 {
445 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
446
447
448
449
450
451
452
453 if (where == PORT_LOGIC_MSIX_DOORBELL)
454 return PCIBIOS_SUCCESSFUL;
455
456 return dw_pcie_write(pci->dbi_base + where, size, val);
457 }
458
459 #if defined(CONFIG_PCIEASPM)
460 static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
461 {
462 u32 val;
463
464 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
465 val &= ~PCI_L1SS_CAP_ASPM_L1_1;
466 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
467 }
468
469 static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
470 {
471 u32 val;
472
473 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
474 val &= ~PCI_L1SS_CAP_ASPM_L1_2;
475 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
476 }
477
478 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
479 {
480 u32 val;
481
482 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
483 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
484 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
485 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
486 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
487 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
488 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
489
490 return val;
491 }
492
493 static int aspm_state_cnt(struct seq_file *s, void *data)
494 {
495 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
496 dev_get_drvdata(s->private);
497 u32 val;
498
499 seq_printf(s, "Tx L0s entry count : %u\n",
500 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
501
502 seq_printf(s, "Rx L0s entry count : %u\n",
503 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
504
505 seq_printf(s, "Link L1 entry count : %u\n",
506 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
507
508 seq_printf(s, "Link L1.1 entry count : %u\n",
509 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
510
511 seq_printf(s, "Link L1.2 entry count : %u\n",
512 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
513
514
515 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
516 EVENT_COUNTER_ALL_CLEAR);
517
518
519 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
520 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
521 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
522
523 return 0;
524 }
525
526 static void init_host_aspm(struct tegra_pcie_dw *pcie)
527 {
528 struct dw_pcie *pci = &pcie->pci;
529 u32 val;
530
531 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
532 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
533
534
535 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
536 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
537 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
538
539
540 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
541 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
542 val |= (pcie->aspm_cmrt << 8);
543 val |= (pcie->aspm_pwr_on_t << 19);
544 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
545
546
547 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
548 val &= ~L0S_ENTRANCE_LAT_MASK;
549 val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT);
550 val |= ENTER_ASPM;
551 dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
552 }
553
554 static int init_debugfs(struct tegra_pcie_dw *pcie)
555 {
556 struct dentry *d;
557
558 d = debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt",
559 pcie->debugfs, aspm_state_cnt);
560 if (IS_ERR_OR_NULL(d))
561 dev_err(pcie->dev,
562 "Failed to create debugfs file \"aspm_state_cnt\"\n");
563
564 return 0;
565 }
566 #else
567 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
568 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
569 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
570 static inline int init_debugfs(struct tegra_pcie_dw *pcie) { return 0; }
571 #endif
572
573 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
574 {
575 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
576 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
577 u32 val;
578 u16 val_w;
579
580 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
581 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
582 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
583
584 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
585 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
586 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
587
588 if (pcie->enable_cdm_check) {
589 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
590 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
591 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
592
593 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
594 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
595 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
596 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
597 }
598
599 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
600 PCI_EXP_LNKSTA);
601 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
602 PCI_EXP_LNKSTA_NLW_SHIFT;
603
604 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
605 PCI_EXP_LNKCTL);
606 val_w |= PCI_EXP_LNKCTL_LBMIE;
607 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
608 val_w);
609 }
610
611 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
612 {
613 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
614 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
615 u32 val;
616
617
618 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
619 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
620 val |= APPL_INTR_EN_L0_0_INT_INT_EN;
621 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
622
623 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
624 val |= APPL_INTR_EN_L1_8_INTX_EN;
625 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
626 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
627 if (IS_ENABLED(CONFIG_PCIEAER))
628 val |= APPL_INTR_EN_L1_8_AER_INT_EN;
629 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
630 }
631
632 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
633 {
634 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
635 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
636 u32 val;
637
638 dw_pcie_msi_init(pp);
639
640
641 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
642 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
643 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
644 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
645 }
646
647 static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
648 {
649 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
650 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
651
652
653 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
654 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
655 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
656 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
657 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
658 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
659 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
660 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
661 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
662 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
663 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
664 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
665 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
666 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
667 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
668
669 tegra_pcie_enable_system_interrupts(pp);
670 tegra_pcie_enable_legacy_interrupts(pp);
671 if (IS_ENABLED(CONFIG_PCI_MSI))
672 tegra_pcie_enable_msi_interrupts(pp);
673 }
674
675 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
676 {
677 struct dw_pcie *pci = &pcie->pci;
678 u32 val, offset, i;
679
680
681 for (i = 0; i < pcie->num_lanes; i++) {
682 dw_pcie_read(pci->dbi_base + CAP_SPCIE_CAP_OFF
683 + (i * 2), 2, &val);
684 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
685 val |= GEN3_GEN4_EQ_PRESET_INIT;
686 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
687 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
688 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
689 dw_pcie_write(pci->dbi_base + CAP_SPCIE_CAP_OFF
690 + (i * 2), 2, val);
691
692 offset = dw_pcie_find_ext_capability(pci,
693 PCI_EXT_CAP_ID_PL_16GT) +
694 PCI_PL_16GT_LE_CTRL;
695 dw_pcie_read(pci->dbi_base + offset + i, 1, &val);
696 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
697 val |= GEN3_GEN4_EQ_PRESET_INIT;
698 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
699 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
700 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
701 dw_pcie_write(pci->dbi_base + offset + i, 1, val);
702 }
703
704 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
705 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
706 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
707
708 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
709 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
710 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
711 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
712 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
713
714 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
715 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
716 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
717 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
718
719 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
720 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
721 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
722 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
723 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
724
725 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
726 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
727 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
728 }
729
730 static void tegra_pcie_prepare_host(struct pcie_port *pp)
731 {
732 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
733 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
734 u32 val;
735
736 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
737 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
738 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
739
740 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
741 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
742 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
743 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
744
745 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
746
747
748 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
749 val &= ~(N_FTS_MASK << N_FTS_SHIFT);
750 val |= N_FTS_VAL << N_FTS_SHIFT;
751 dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
752
753 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
754 val &= ~FTS_MASK;
755 val |= FTS_VAL;
756 dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
757
758
759 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
760 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
761 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
762 AMBA_ERROR_RESPONSE_CRS_SHIFT);
763 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
764
765
766 if (pcie->max_speed && pcie->max_speed != -EINVAL) {
767 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base +
768 PCI_EXP_LNKCAP);
769 val &= ~PCI_EXP_LNKCAP_SLS;
770 val |= pcie->max_speed;
771 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP,
772 val);
773 }
774
775
776 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
777 val &= ~PCI_EXP_LNKCAP_MLW;
778 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
779 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
780
781 config_gen3_gen4_eq_presets(pcie);
782
783 init_host_aspm(pcie);
784
785 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
786 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
787 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
788
789 if (pcie->update_fc_fixup) {
790 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
791 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
792 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
793 }
794
795 dw_pcie_setup_rc(pp);
796
797 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
798
799
800 val = appl_readl(pcie, APPL_PINMUX);
801 val &= ~APPL_PINMUX_PEX_RST;
802 appl_writel(pcie, val, APPL_PINMUX);
803
804 usleep_range(100, 200);
805
806
807 val = appl_readl(pcie, APPL_CTRL);
808 val |= APPL_CTRL_LTSSM_EN;
809 appl_writel(pcie, val, APPL_CTRL);
810
811
812 val = appl_readl(pcie, APPL_PINMUX);
813 val |= APPL_PINMUX_PEX_RST;
814 appl_writel(pcie, val, APPL_PINMUX);
815
816 msleep(100);
817 }
818
819 static int tegra_pcie_dw_host_init(struct pcie_port *pp)
820 {
821 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
822 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
823 u32 val, tmp, offset, speed;
824
825 tegra_pcie_prepare_host(pp);
826
827 if (dw_pcie_wait_for_link(pci)) {
828
829
830
831
832
833
834
835
836 val = appl_readl(pcie, APPL_DEBUG);
837 val &= APPL_DEBUG_LTSSM_STATE_MASK;
838 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
839 tmp = appl_readl(pcie, APPL_LINK_STATUS);
840 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
841 if (!(val == 0x11 && !tmp)) {
842
843 return 0;
844 }
845
846 dev_info(pci->dev, "Link is down in DLL");
847 dev_info(pci->dev, "Trying again with DLFE disabled\n");
848
849 val = appl_readl(pcie, APPL_CTRL);
850 val &= ~APPL_CTRL_LTSSM_EN;
851 appl_writel(pcie, val, APPL_CTRL);
852
853 reset_control_assert(pcie->core_rst);
854 reset_control_deassert(pcie->core_rst);
855
856 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
857 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
858 val &= ~PCI_DLF_EXCHANGE_ENABLE;
859 dw_pcie_writel_dbi(pci, offset, val);
860
861 tegra_pcie_prepare_host(pp);
862
863 if (dw_pcie_wait_for_link(pci))
864 return 0;
865 }
866
867 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
868 PCI_EXP_LNKSTA_CLS;
869 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
870
871 tegra_pcie_enable_interrupts(pp);
872
873 return 0;
874 }
875
876 static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
877 {
878 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
879 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
880
881 return !!(val & PCI_EXP_LNKSTA_DLLLA);
882 }
883
884 static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp)
885 {
886 pp->num_vectors = MAX_MSI_IRQS;
887 }
888
889 static const struct dw_pcie_ops tegra_dw_pcie_ops = {
890 .link_up = tegra_pcie_dw_link_up,
891 };
892
893 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
894 .rd_own_conf = tegra_pcie_dw_rd_own_conf,
895 .wr_own_conf = tegra_pcie_dw_wr_own_conf,
896 .host_init = tegra_pcie_dw_host_init,
897 .set_num_vectors = tegra_pcie_set_msi_vec_num,
898 };
899
900 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
901 {
902 unsigned int phy_count = pcie->phy_count;
903
904 while (phy_count--) {
905 phy_power_off(pcie->phys[phy_count]);
906 phy_exit(pcie->phys[phy_count]);
907 }
908 }
909
910 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
911 {
912 unsigned int i;
913 int ret;
914
915 for (i = 0; i < pcie->phy_count; i++) {
916 ret = phy_init(pcie->phys[i]);
917 if (ret < 0)
918 goto phy_power_off;
919
920 ret = phy_power_on(pcie->phys[i]);
921 if (ret < 0)
922 goto phy_exit;
923 }
924
925 return 0;
926
927 phy_power_off:
928 while (i--) {
929 phy_power_off(pcie->phys[i]);
930 phy_exit:
931 phy_exit(pcie->phys[i]);
932 }
933
934 return ret;
935 }
936
937 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
938 {
939 struct device_node *np = pcie->dev->of_node;
940 int ret;
941
942 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
943 if (ret < 0) {
944 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
945 return ret;
946 }
947
948 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
949 &pcie->aspm_pwr_on_t);
950 if (ret < 0)
951 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
952 ret);
953
954 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
955 &pcie->aspm_l0s_enter_lat);
956 if (ret < 0)
957 dev_info(pcie->dev,
958 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
959
960 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
961 if (ret < 0) {
962 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
963 return ret;
964 }
965
966 pcie->max_speed = of_pci_get_max_link_speed(np);
967
968 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
969 if (ret) {
970 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
971 return ret;
972 }
973
974 ret = of_property_count_strings(np, "phy-names");
975 if (ret < 0) {
976 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
977 ret);
978 return ret;
979 }
980 pcie->phy_count = ret;
981
982 if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
983 pcie->update_fc_fixup = true;
984
985 pcie->supports_clkreq =
986 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
987
988 pcie->enable_cdm_check =
989 of_property_read_bool(np, "snps,enable-cdm-check");
990
991 return 0;
992 }
993
994 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
995 bool enable)
996 {
997 struct mrq_uphy_response resp;
998 struct tegra_bpmp_message msg;
999 struct mrq_uphy_request req;
1000
1001
1002 if (pcie->cid == 5)
1003 return 0;
1004
1005 memset(&req, 0, sizeof(req));
1006 memset(&resp, 0, sizeof(resp));
1007
1008 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
1009 req.controller_state.pcie_controller = pcie->cid;
1010 req.controller_state.enable = enable;
1011
1012 memset(&msg, 0, sizeof(msg));
1013 msg.mrq = MRQ_UPHY;
1014 msg.tx.data = &req;
1015 msg.tx.size = sizeof(req);
1016 msg.rx.data = &resp;
1017 msg.rx.size = sizeof(resp);
1018
1019 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1020 }
1021
1022 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
1023 {
1024 struct pcie_port *pp = &pcie->pci.pp;
1025 struct pci_bus *child, *root_bus = NULL;
1026 struct pci_dev *pdev;
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037 list_for_each_entry(child, &pp->root_bus->children, node) {
1038
1039 if (child->parent == pp->root_bus) {
1040 root_bus = child;
1041 break;
1042 }
1043 }
1044
1045 if (!root_bus) {
1046 dev_err(pcie->dev, "Failed to find downstream devices\n");
1047 return;
1048 }
1049
1050 list_for_each_entry(pdev, &root_bus->devices, bus_list) {
1051 if (PCI_SLOT(pdev->devfn) == 0) {
1052 if (pci_set_power_state(pdev, PCI_D0))
1053 dev_err(pcie->dev,
1054 "Failed to transition %s to D0 state\n",
1055 dev_name(&pdev->dev));
1056 }
1057 }
1058 }
1059
1060 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
1061 {
1062 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1063 if (IS_ERR(pcie->slot_ctl_3v3)) {
1064 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1065 return PTR_ERR(pcie->slot_ctl_3v3);
1066
1067 pcie->slot_ctl_3v3 = NULL;
1068 }
1069
1070 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1071 if (IS_ERR(pcie->slot_ctl_12v)) {
1072 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1073 return PTR_ERR(pcie->slot_ctl_12v);
1074
1075 pcie->slot_ctl_12v = NULL;
1076 }
1077
1078 return 0;
1079 }
1080
1081 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
1082 {
1083 int ret;
1084
1085 if (pcie->slot_ctl_3v3) {
1086 ret = regulator_enable(pcie->slot_ctl_3v3);
1087 if (ret < 0) {
1088 dev_err(pcie->dev,
1089 "Failed to enable 3.3V slot supply: %d\n", ret);
1090 return ret;
1091 }
1092 }
1093
1094 if (pcie->slot_ctl_12v) {
1095 ret = regulator_enable(pcie->slot_ctl_12v);
1096 if (ret < 0) {
1097 dev_err(pcie->dev,
1098 "Failed to enable 12V slot supply: %d\n", ret);
1099 goto fail_12v_enable;
1100 }
1101 }
1102
1103
1104
1105
1106
1107
1108 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1109 msleep(100);
1110
1111 return 0;
1112
1113 fail_12v_enable:
1114 if (pcie->slot_ctl_3v3)
1115 regulator_disable(pcie->slot_ctl_3v3);
1116 return ret;
1117 }
1118
1119 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
1120 {
1121 if (pcie->slot_ctl_12v)
1122 regulator_disable(pcie->slot_ctl_12v);
1123 if (pcie->slot_ctl_3v3)
1124 regulator_disable(pcie->slot_ctl_3v3);
1125 }
1126
1127 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
1128 bool en_hw_hot_rst)
1129 {
1130 int ret;
1131 u32 val;
1132
1133 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1134 if (ret) {
1135 dev_err(pcie->dev,
1136 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1137 return ret;
1138 }
1139
1140 ret = tegra_pcie_enable_slot_regulators(pcie);
1141 if (ret < 0)
1142 goto fail_slot_reg_en;
1143
1144 ret = regulator_enable(pcie->pex_ctl_supply);
1145 if (ret < 0) {
1146 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1147 goto fail_reg_en;
1148 }
1149
1150 ret = clk_prepare_enable(pcie->core_clk);
1151 if (ret) {
1152 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1153 goto fail_core_clk;
1154 }
1155
1156 ret = reset_control_deassert(pcie->core_apb_rst);
1157 if (ret) {
1158 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1159 ret);
1160 goto fail_core_apb_rst;
1161 }
1162
1163 if (en_hw_hot_rst) {
1164
1165 val = appl_readl(pcie, APPL_CTRL);
1166 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1167 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
1168 val |= APPL_CTRL_HW_HOT_RST_EN;
1169 appl_writel(pcie, val, APPL_CTRL);
1170 }
1171
1172 ret = tegra_pcie_enable_phy(pcie);
1173 if (ret) {
1174 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1175 goto fail_phy;
1176 }
1177
1178
1179 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1180 APPL_CFG_BASE_ADDR);
1181
1182
1183 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1184
1185 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1186
1187 val = appl_readl(pcie, APPL_CTRL);
1188 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1189
1190 val = appl_readl(pcie, APPL_CFG_MISC);
1191 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1192 appl_writel(pcie, val, APPL_CFG_MISC);
1193
1194 if (!pcie->supports_clkreq) {
1195 val = appl_readl(pcie, APPL_PINMUX);
1196 val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
1197 val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
1198 appl_writel(pcie, val, APPL_PINMUX);
1199 }
1200
1201
1202 appl_writel(pcie,
1203 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1204 APPL_CFG_IATU_DMA_BASE_ADDR);
1205
1206 reset_control_deassert(pcie->core_rst);
1207
1208 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1209 PCI_CAP_ID_EXP);
1210
1211
1212 if (!pcie->supports_clkreq) {
1213 disable_aspm_l11(pcie);
1214 disable_aspm_l12(pcie);
1215 }
1216
1217 return ret;
1218
1219 fail_phy:
1220 reset_control_assert(pcie->core_apb_rst);
1221 fail_core_apb_rst:
1222 clk_disable_unprepare(pcie->core_clk);
1223 fail_core_clk:
1224 regulator_disable(pcie->pex_ctl_supply);
1225 fail_reg_en:
1226 tegra_pcie_disable_slot_regulators(pcie);
1227 fail_slot_reg_en:
1228 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1229
1230 return ret;
1231 }
1232
1233 static int __deinit_controller(struct tegra_pcie_dw *pcie)
1234 {
1235 int ret;
1236
1237 ret = reset_control_assert(pcie->core_rst);
1238 if (ret) {
1239 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n",
1240 ret);
1241 return ret;
1242 }
1243
1244 tegra_pcie_disable_phy(pcie);
1245
1246 ret = reset_control_assert(pcie->core_apb_rst);
1247 if (ret) {
1248 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1249 return ret;
1250 }
1251
1252 clk_disable_unprepare(pcie->core_clk);
1253
1254 ret = regulator_disable(pcie->pex_ctl_supply);
1255 if (ret) {
1256 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1257 return ret;
1258 }
1259
1260 tegra_pcie_disable_slot_regulators(pcie);
1261
1262 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1263 if (ret) {
1264 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1265 pcie->cid, ret);
1266 return ret;
1267 }
1268
1269 return ret;
1270 }
1271
1272 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
1273 {
1274 struct dw_pcie *pci = &pcie->pci;
1275 struct pcie_port *pp = &pci->pp;
1276 int ret;
1277
1278 ret = tegra_pcie_config_controller(pcie, false);
1279 if (ret < 0)
1280 return ret;
1281
1282 pp->ops = &tegra_pcie_dw_host_ops;
1283
1284 ret = dw_pcie_host_init(pp);
1285 if (ret < 0) {
1286 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1287 goto fail_host_init;
1288 }
1289
1290 return 0;
1291
1292 fail_host_init:
1293 return __deinit_controller(pcie);
1294 }
1295
1296 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
1297 {
1298 u32 val;
1299
1300 if (!tegra_pcie_dw_link_up(&pcie->pci))
1301 return 0;
1302
1303 val = appl_readl(pcie, APPL_RADM_STATUS);
1304 val |= APPL_PM_XMT_TURNOFF_STATE;
1305 appl_writel(pcie, val, APPL_RADM_STATUS);
1306
1307 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1308 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
1309 1, PME_ACK_TIMEOUT);
1310 }
1311
1312 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
1313 {
1314 u32 data;
1315 int err;
1316
1317 if (!tegra_pcie_dw_link_up(&pcie->pci)) {
1318 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1319 return;
1320 }
1321
1322 if (tegra_pcie_try_link_l2(pcie)) {
1323 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1324
1325
1326
1327
1328
1329
1330 data = appl_readl(pcie, APPL_PINMUX);
1331 data &= ~APPL_PINMUX_PEX_RST;
1332 appl_writel(pcie, data, APPL_PINMUX);
1333
1334 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1335 data,
1336 ((data &
1337 APPL_DEBUG_LTSSM_STATE_MASK) >>
1338 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1339 LTSSM_STATE_PRE_DETECT,
1340 1, LTSSM_TIMEOUT);
1341 if (err) {
1342 dev_info(pcie->dev, "Link didn't go to detect state\n");
1343 } else {
1344
1345 data = appl_readl(pcie, APPL_CTRL);
1346 data &= ~APPL_CTRL_LTSSM_EN;
1347 appl_writel(pcie, data, APPL_CTRL);
1348 }
1349 }
1350
1351
1352
1353
1354 data = appl_readl(pcie, APPL_PINMUX);
1355 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE);
1356
1357 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1358 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1359 appl_writel(pcie, data, APPL_PINMUX);
1360 }
1361
1362 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
1363 {
1364 tegra_pcie_downstream_dev_to_D0(pcie);
1365 dw_pcie_host_deinit(&pcie->pci.pp);
1366 tegra_pcie_dw_pme_turnoff(pcie);
1367
1368 return __deinit_controller(pcie);
1369 }
1370
1371 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
1372 {
1373 struct pcie_port *pp = &pcie->pci.pp;
1374 struct device *dev = pcie->dev;
1375 char *name;
1376 int ret;
1377
1378 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1379 pp->msi_irq = of_irq_get_byname(dev->of_node, "msi");
1380 if (!pp->msi_irq) {
1381 dev_err(dev, "Failed to get MSI interrupt\n");
1382 return -ENODEV;
1383 }
1384 }
1385
1386 pm_runtime_enable(dev);
1387
1388 ret = pm_runtime_get_sync(dev);
1389 if (ret < 0) {
1390 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1391 ret);
1392 goto fail_pm_get_sync;
1393 }
1394
1395 ret = pinctrl_pm_select_default_state(dev);
1396 if (ret < 0) {
1397 dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
1398 goto fail_pinctrl;
1399 }
1400
1401 tegra_pcie_init_controller(pcie);
1402
1403 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
1404 if (!pcie->link_state) {
1405 ret = -ENOMEDIUM;
1406 goto fail_host_init;
1407 }
1408
1409 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1410 if (!name) {
1411 ret = -ENOMEM;
1412 goto fail_host_init;
1413 }
1414
1415 pcie->debugfs = debugfs_create_dir(name, NULL);
1416 if (!pcie->debugfs)
1417 dev_err(dev, "Failed to create debugfs\n");
1418 else
1419 init_debugfs(pcie);
1420
1421 return ret;
1422
1423 fail_host_init:
1424 tegra_pcie_deinit_controller(pcie);
1425 fail_pinctrl:
1426 pm_runtime_put_sync(dev);
1427 fail_pm_get_sync:
1428 pm_runtime_disable(dev);
1429 return ret;
1430 }
1431
1432 static int tegra_pcie_dw_probe(struct platform_device *pdev)
1433 {
1434 struct device *dev = &pdev->dev;
1435 struct resource *atu_dma_res;
1436 struct tegra_pcie_dw *pcie;
1437 struct resource *dbi_res;
1438 struct pcie_port *pp;
1439 struct dw_pcie *pci;
1440 struct phy **phys;
1441 char *name;
1442 int ret;
1443 u32 i;
1444
1445 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1446 if (!pcie)
1447 return -ENOMEM;
1448
1449 pci = &pcie->pci;
1450 pci->dev = &pdev->dev;
1451 pci->ops = &tegra_dw_pcie_ops;
1452 pp = &pci->pp;
1453 pcie->dev = &pdev->dev;
1454
1455 ret = tegra_pcie_dw_parse_dt(pcie);
1456 if (ret < 0) {
1457 dev_err(dev, "Failed to parse device tree: %d\n", ret);
1458 return ret;
1459 }
1460
1461 ret = tegra_pcie_get_slot_regulators(pcie);
1462 if (ret < 0) {
1463 dev_err(dev, "Failed to get slot regulators: %d\n", ret);
1464 return ret;
1465 }
1466
1467 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
1468 if (IS_ERR(pcie->pex_ctl_supply)) {
1469 ret = PTR_ERR(pcie->pex_ctl_supply);
1470 if (ret != -EPROBE_DEFER)
1471 dev_err(dev, "Failed to get regulator: %ld\n",
1472 PTR_ERR(pcie->pex_ctl_supply));
1473 return ret;
1474 }
1475
1476 pcie->core_clk = devm_clk_get(dev, "core");
1477 if (IS_ERR(pcie->core_clk)) {
1478 dev_err(dev, "Failed to get core clock: %ld\n",
1479 PTR_ERR(pcie->core_clk));
1480 return PTR_ERR(pcie->core_clk);
1481 }
1482
1483 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1484 "appl");
1485 if (!pcie->appl_res) {
1486 dev_err(dev, "Failed to find \"appl\" region\n");
1487 return -ENODEV;
1488 }
1489
1490 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
1491 if (IS_ERR(pcie->appl_base))
1492 return PTR_ERR(pcie->appl_base);
1493
1494 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
1495 if (IS_ERR(pcie->core_apb_rst)) {
1496 dev_err(dev, "Failed to get APB reset: %ld\n",
1497 PTR_ERR(pcie->core_apb_rst));
1498 return PTR_ERR(pcie->core_apb_rst);
1499 }
1500
1501 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
1502 if (!phys)
1503 return -ENOMEM;
1504
1505 for (i = 0; i < pcie->phy_count; i++) {
1506 name = kasprintf(GFP_KERNEL, "p2u-%u", i);
1507 if (!name) {
1508 dev_err(dev, "Failed to create P2U string\n");
1509 return -ENOMEM;
1510 }
1511 phys[i] = devm_phy_get(dev, name);
1512 kfree(name);
1513 if (IS_ERR(phys[i])) {
1514 ret = PTR_ERR(phys[i]);
1515 if (ret != -EPROBE_DEFER)
1516 dev_err(dev, "Failed to get PHY: %d\n", ret);
1517 return ret;
1518 }
1519 }
1520
1521 pcie->phys = phys;
1522
1523 dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1524 if (!dbi_res) {
1525 dev_err(dev, "Failed to find \"dbi\" region\n");
1526 return -ENODEV;
1527 }
1528 pcie->dbi_res = dbi_res;
1529
1530 pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
1531 if (IS_ERR(pci->dbi_base))
1532 return PTR_ERR(pci->dbi_base);
1533
1534
1535 pci->dbi_base2 = pci->dbi_base + 0x1000;
1536
1537 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1538 "atu_dma");
1539 if (!atu_dma_res) {
1540 dev_err(dev, "Failed to find \"atu_dma\" region\n");
1541 return -ENODEV;
1542 }
1543 pcie->atu_dma_res = atu_dma_res;
1544
1545 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
1546 if (IS_ERR(pci->atu_base))
1547 return PTR_ERR(pci->atu_base);
1548
1549 pcie->core_rst = devm_reset_control_get(dev, "core");
1550 if (IS_ERR(pcie->core_rst)) {
1551 dev_err(dev, "Failed to get core reset: %ld\n",
1552 PTR_ERR(pcie->core_rst));
1553 return PTR_ERR(pcie->core_rst);
1554 }
1555
1556 pp->irq = platform_get_irq_byname(pdev, "intr");
1557 if (!pp->irq) {
1558 dev_err(dev, "Failed to get \"intr\" interrupt\n");
1559 return -ENODEV;
1560 }
1561
1562 ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
1563 IRQF_SHARED, "tegra-pcie-intr", pcie);
1564 if (ret) {
1565 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
1566 return ret;
1567 }
1568
1569 pcie->bpmp = tegra_bpmp_get(dev);
1570 if (IS_ERR(pcie->bpmp))
1571 return PTR_ERR(pcie->bpmp);
1572
1573 platform_set_drvdata(pdev, pcie);
1574
1575 ret = tegra_pcie_config_rp(pcie);
1576 if (ret && ret != -ENOMEDIUM)
1577 goto fail;
1578 else
1579 return 0;
1580
1581 fail:
1582 tegra_bpmp_put(pcie->bpmp);
1583 return ret;
1584 }
1585
1586 static int tegra_pcie_dw_remove(struct platform_device *pdev)
1587 {
1588 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
1589
1590 if (!pcie->link_state)
1591 return 0;
1592
1593 debugfs_remove_recursive(pcie->debugfs);
1594 tegra_pcie_deinit_controller(pcie);
1595 pm_runtime_put_sync(pcie->dev);
1596 pm_runtime_disable(pcie->dev);
1597 tegra_bpmp_put(pcie->bpmp);
1598
1599 return 0;
1600 }
1601
1602 static int tegra_pcie_dw_suspend_late(struct device *dev)
1603 {
1604 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
1605 u32 val;
1606
1607 if (!pcie->link_state)
1608 return 0;
1609
1610
1611 val = appl_readl(pcie, APPL_CTRL);
1612 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1613 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
1614 val |= APPL_CTRL_HW_HOT_RST_EN;
1615 appl_writel(pcie, val, APPL_CTRL);
1616
1617 return 0;
1618 }
1619
1620 static int tegra_pcie_dw_suspend_noirq(struct device *dev)
1621 {
1622 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
1623
1624 if (!pcie->link_state)
1625 return 0;
1626
1627
1628 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
1629 PORT_LOGIC_MSI_CTRL_INT_0_EN);
1630 tegra_pcie_downstream_dev_to_D0(pcie);
1631 tegra_pcie_dw_pme_turnoff(pcie);
1632
1633 return __deinit_controller(pcie);
1634 }
1635
1636 static int tegra_pcie_dw_resume_noirq(struct device *dev)
1637 {
1638 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
1639 int ret;
1640
1641 if (!pcie->link_state)
1642 return 0;
1643
1644 ret = tegra_pcie_config_controller(pcie, true);
1645 if (ret < 0)
1646 return ret;
1647
1648 ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
1649 if (ret < 0) {
1650 dev_err(dev, "Failed to init host: %d\n", ret);
1651 goto fail_host_init;
1652 }
1653
1654
1655 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
1656 pcie->msi_ctrl_int);
1657
1658 return 0;
1659
1660 fail_host_init:
1661 return __deinit_controller(pcie);
1662 }
1663
1664 static int tegra_pcie_dw_resume_early(struct device *dev)
1665 {
1666 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
1667 u32 val;
1668
1669 if (!pcie->link_state)
1670 return 0;
1671
1672
1673 val = appl_readl(pcie, APPL_CTRL);
1674 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1675 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
1676 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
1677 APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
1678 val &= ~APPL_CTRL_HW_HOT_RST_EN;
1679 appl_writel(pcie, val, APPL_CTRL);
1680
1681 return 0;
1682 }
1683
1684 static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
1685 {
1686 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
1687
1688 if (!pcie->link_state)
1689 return;
1690
1691 debugfs_remove_recursive(pcie->debugfs);
1692 tegra_pcie_downstream_dev_to_D0(pcie);
1693
1694 disable_irq(pcie->pci.pp.irq);
1695 if (IS_ENABLED(CONFIG_PCI_MSI))
1696 disable_irq(pcie->pci.pp.msi_irq);
1697
1698 tegra_pcie_dw_pme_turnoff(pcie);
1699 __deinit_controller(pcie);
1700 }
1701
1702 static const struct of_device_id tegra_pcie_dw_of_match[] = {
1703 {
1704 .compatible = "nvidia,tegra194-pcie",
1705 },
1706 {},
1707 };
1708
1709 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
1710 .suspend_late = tegra_pcie_dw_suspend_late,
1711 .suspend_noirq = tegra_pcie_dw_suspend_noirq,
1712 .resume_noirq = tegra_pcie_dw_resume_noirq,
1713 .resume_early = tegra_pcie_dw_resume_early,
1714 };
1715
1716 static struct platform_driver tegra_pcie_dw_driver = {
1717 .probe = tegra_pcie_dw_probe,
1718 .remove = tegra_pcie_dw_remove,
1719 .shutdown = tegra_pcie_dw_shutdown,
1720 .driver = {
1721 .name = "tegra194-pcie",
1722 .pm = &tegra_pcie_dw_pm_ops,
1723 .of_match_table = tegra_pcie_dw_of_match,
1724 },
1725 };
1726 module_platform_driver(tegra_pcie_dw_driver);
1727
1728 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
1729
1730 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
1731 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
1732 MODULE_LICENSE("GPL v2");