drivers/pci/controller/pcie-altera.c

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This source file includes following definitions.
cra_writel
cra_readl
altera_pcie_link_up
s10_altera_pcie_link_up
altera_pcie_hide_rc_bar
tlp_write_tx
s10_tlp_write_tx
altera_pcie_valid_device
tlp_read_packet
s10_tlp_read_packet
tlp_write_packet
s10_tlp_write_packet
get_tlp_header
tlp_cfg_dword_read
tlp_cfg_dword_write
s10_rp_read_cfg
s10_rp_write_cfg
_altera_pcie_cfg_read
_altera_pcie_cfg_write
altera_pcie_cfg_read
altera_pcie_cfg_write
altera_read_cap_word
altera_write_cap_word
altera_wait_link_retrain
altera_pcie_retrain
altera_pcie_intx_map
altera_pcie_isr
altera_pcie_parse_request_of_pci_ranges
altera_pcie_init_irq_domain
altera_pcie_irq_teardown
altera_pcie_parse_dt
altera_pcie_host_init
altera_pcie_probe
altera_pcie_remove
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
   4  *
   5  * Author: Ley Foon Tan <lftan@altera.com>
   6  * Description: Altera PCIe host controller driver
   7  */
   8 
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/irqchip/chained_irq.h>
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/pci.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 
  22 #include "../pci.h"
  23 
  24 #define RP_TX_REG0                      0x2000
  25 #define RP_TX_REG1                      0x2004
  26 #define RP_TX_CNTRL                     0x2008
  27 #define RP_TX_EOP                       0x2
  28 #define RP_TX_SOP                       0x1
  29 #define RP_RXCPL_STATUS                 0x2010
  30 #define RP_RXCPL_EOP                    0x2
  31 #define RP_RXCPL_SOP                    0x1
  32 #define RP_RXCPL_REG0                   0x2014
  33 #define RP_RXCPL_REG1                   0x2018
  34 #define P2A_INT_STATUS                  0x3060
  35 #define P2A_INT_STS_ALL                 0xf
  36 #define P2A_INT_ENABLE                  0x3070
  37 #define P2A_INT_ENA_ALL                 0xf
  38 #define RP_LTSSM                        0x3c64
  39 #define RP_LTSSM_MASK                   0x1f
  40 #define LTSSM_L0                        0xf
  41 
  42 #define S10_RP_TX_CNTRL                 0x2004
  43 #define S10_RP_RXCPL_REG                0x2008
  44 #define S10_RP_RXCPL_STATUS             0x200C
  45 #define S10_RP_CFG_ADDR(pcie, reg)      \
  46         (((pcie)->hip_base) + (reg) + (1 << 20))
  47 #define S10_RP_SECONDARY(pcie)          \
  48         readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
  49 
  50 /* TLP configuration type 0 and 1 */
  51 #define TLP_FMTTYPE_CFGRD0              0x04    /* Configuration Read Type 0 */
  52 #define TLP_FMTTYPE_CFGWR0              0x44    /* Configuration Write Type 0 */
  53 #define TLP_FMTTYPE_CFGRD1              0x05    /* Configuration Read Type 1 */
  54 #define TLP_FMTTYPE_CFGWR1              0x45    /* Configuration Write Type 1 */
  55 #define TLP_PAYLOAD_SIZE                0x01
  56 #define TLP_READ_TAG                    0x1d
  57 #define TLP_WRITE_TAG                   0x10
  58 #define RP_DEVFN                        0
  59 #define TLP_REQ_ID(bus, devfn)          (((bus) << 8) | (devfn))
  60 #define TLP_CFG_DW0(pcie, cfg)          \
  61                 (((cfg) << 24) |        \
  62                   TLP_PAYLOAD_SIZE)
  63 #define TLP_CFG_DW1(pcie, tag, be)      \
  64         (((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
  65 #define TLP_CFG_DW2(bus, devfn, offset) \
  66                                 (((bus) << 24) | ((devfn) << 16) | (offset))
  67 #define TLP_COMP_STATUS(s)              (((s) >> 13) & 7)
  68 #define TLP_BYTE_COUNT(s)               (((s) >> 0) & 0xfff)
  69 #define TLP_HDR_SIZE                    3
  70 #define TLP_LOOP                        500
  71 
  72 #define LINK_UP_TIMEOUT                 HZ
  73 #define LINK_RETRAIN_TIMEOUT            HZ
  74 
  75 #define DWORD_MASK                      3
  76 
  77 #define S10_TLP_FMTTYPE_CFGRD0          0x05
  78 #define S10_TLP_FMTTYPE_CFGRD1          0x04
  79 #define S10_TLP_FMTTYPE_CFGWR0          0x45
  80 #define S10_TLP_FMTTYPE_CFGWR1          0x44
  81 
  82 enum altera_pcie_version {
  83         ALTERA_PCIE_V1 = 0,
  84         ALTERA_PCIE_V2,
  85 };
  86 
  87 struct altera_pcie {
  88         struct platform_device  *pdev;
  89         void __iomem            *cra_base;
  90         void __iomem            *hip_base;
  91         int                     irq;
  92         u8                      root_bus_nr;
  93         struct irq_domain       *irq_domain;
  94         struct resource         bus_range;
  95         struct list_head        resources;
  96         const struct altera_pcie_data   *pcie_data;
  97 };
  98 
  99 struct altera_pcie_ops {
 100         int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
 101         void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
 102                               u32 data, bool align);
 103         bool (*get_link_status)(struct altera_pcie *pcie);
 104         int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
 105                            int size, u32 *value);
 106         int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
 107                             int where, int size, u32 value);
 108 };
 109 
 110 struct altera_pcie_data {
 111         const struct altera_pcie_ops *ops;
 112         enum altera_pcie_version version;
 113         u32 cap_offset;         /* PCIe capability structure register offset */
 114         u32 cfgrd0;
 115         u32 cfgrd1;
 116         u32 cfgwr0;
 117         u32 cfgwr1;
 118 };
 119 
 120 struct tlp_rp_regpair_t {
 121         u32 ctrl;
 122         u32 reg0;
 123         u32 reg1;
 124 };
 125 
 126 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
 127                               const u32 reg)
 128 {
 129         writel_relaxed(value, pcie->cra_base + reg);
 130 }
 131 
 132 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
 133 {
 134         return readl_relaxed(pcie->cra_base + reg);
 135 }
 136 
 137 static bool altera_pcie_link_up(struct altera_pcie *pcie)
 138 {
 139         return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 140 }
 141 
 142 static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
 143 {
 144         void __iomem *addr = S10_RP_CFG_ADDR(pcie,
 145                                    pcie->pcie_data->cap_offset +
 146                                    PCI_EXP_LNKSTA);
 147 
 148         return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
 149 }
 150 
 151 /*
 152  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 153  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 154  * using these registers, so it can be reached by DMA from EP devices.
 155  * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 156  * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 157  * should be hidden during enumeration to avoid the sizing and resource
 158  * allocation by PCIe core.
 159  */
 160 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
 161                                     int offset)
 162 {
 163         if (pci_is_root_bus(bus) && (devfn == 0) &&
 164             (offset == PCI_BASE_ADDRESS_0))
 165                 return true;
 166 
 167         return false;
 168 }
 169 
 170 static void tlp_write_tx(struct altera_pcie *pcie,
 171                          struct tlp_rp_regpair_t *tlp_rp_regdata)
 172 {
 173         cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
 174         cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
 175         cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
 176 }
 177 
 178 static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)
 179 {
 180         cra_writel(pcie, reg0, RP_TX_REG0);
 181         cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);
 182 }
 183 
 184 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
 185                                      struct pci_bus *bus, int dev)
 186 {
 187         /* If there is no link, then there is no device */
 188         if (bus->number != pcie->root_bus_nr) {
 189                 if (!pcie->pcie_data->ops->get_link_status(pcie))
 190                         return false;
 191         }
 192 
 193         /* access only one slot on each root port */
 194         if (bus->number == pcie->root_bus_nr && dev > 0)
 195                 return false;
 196 
 197          return true;
 198 }
 199 
 200 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 201 {
 202         int i;
 203         bool sop = false;
 204         u32 ctrl;
 205         u32 reg0, reg1;
 206         u32 comp_status = 1;
 207 
 208         /*
 209          * Minimum 2 loops to read TLP headers and 1 loop to read data
 210          * payload.
 211          */
 212         for (i = 0; i < TLP_LOOP; i++) {
 213                 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
 214                 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
 215                         reg0 = cra_readl(pcie, RP_RXCPL_REG0);
 216                         reg1 = cra_readl(pcie, RP_RXCPL_REG1);
 217 
 218                         if (ctrl & RP_RXCPL_SOP) {
 219                                 sop = true;
 220                                 comp_status = TLP_COMP_STATUS(reg1);
 221                         }
 222 
 223                         if (ctrl & RP_RXCPL_EOP) {
 224                                 if (comp_status)
 225                                         return PCIBIOS_DEVICE_NOT_FOUND;
 226 
 227                                 if (value)
 228                                         *value = reg0;
 229 
 230                                 return PCIBIOS_SUCCESSFUL;
 231                         }
 232                 }
 233                 udelay(5);
 234         }
 235 
 236         return PCIBIOS_DEVICE_NOT_FOUND;
 237 }
 238 
 239 static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 240 {
 241         u32 ctrl;
 242         u32 comp_status;
 243         u32 dw[4];
 244         u32 count;
 245         struct device *dev = &pcie->pdev->dev;
 246 
 247         for (count = 0; count < TLP_LOOP; count++) {
 248                 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
 249                 if (ctrl & RP_RXCPL_SOP) {
 250                         /* Read first DW */
 251                         dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
 252                         break;
 253                 }
 254 
 255                 udelay(5);
 256         }
 257 
 258         /* SOP detection failed, return error */
 259         if (count == TLP_LOOP)
 260                 return PCIBIOS_DEVICE_NOT_FOUND;
 261 
 262         count = 1;
 263 
 264         /* Poll for EOP */
 265         while (count < ARRAY_SIZE(dw)) {
 266                 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
 267                 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);
 268                 if (ctrl & RP_RXCPL_EOP) {
 269                         comp_status = TLP_COMP_STATUS(dw[1]);
 270                         if (comp_status)
 271                                 return PCIBIOS_DEVICE_NOT_FOUND;
 272 
 273                         if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
 274                             count == 4)
 275                                 *value = dw[3];
 276 
 277                         return PCIBIOS_SUCCESSFUL;
 278                 }
 279         }
 280 
 281         dev_warn(dev, "Malformed TLP packet\n");
 282 
 283         return PCIBIOS_DEVICE_NOT_FOUND;
 284 }
 285 
 286 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 287                              u32 data, bool align)
 288 {
 289         struct tlp_rp_regpair_t tlp_rp_regdata;
 290 
 291         tlp_rp_regdata.reg0 = headers[0];
 292         tlp_rp_regdata.reg1 = headers[1];
 293         tlp_rp_regdata.ctrl = RP_TX_SOP;
 294         tlp_write_tx(pcie, &tlp_rp_regdata);
 295 
 296         if (align) {
 297                 tlp_rp_regdata.reg0 = headers[2];
 298                 tlp_rp_regdata.reg1 = 0;
 299                 tlp_rp_regdata.ctrl = 0;
 300                 tlp_write_tx(pcie, &tlp_rp_regdata);
 301 
 302                 tlp_rp_regdata.reg0 = data;
 303                 tlp_rp_regdata.reg1 = 0;
 304         } else {
 305                 tlp_rp_regdata.reg0 = headers[2];
 306                 tlp_rp_regdata.reg1 = data;
 307         }
 308 
 309         tlp_rp_regdata.ctrl = RP_TX_EOP;
 310         tlp_write_tx(pcie, &tlp_rp_regdata);
 311 }
 312 
 313 static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 314                                  u32 data, bool dummy)
 315 {
 316         s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
 317         s10_tlp_write_tx(pcie, headers[1], 0);
 318         s10_tlp_write_tx(pcie, headers[2], 0);
 319         s10_tlp_write_tx(pcie, data, RP_TX_EOP);
 320 }
 321 
 322 static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
 323                            int where, u8 byte_en, bool read, u32 *headers)
 324 {
 325         u8 cfg;
 326         u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
 327         u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
 328         u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
 329 
 330         if (pcie->pcie_data->version == ALTERA_PCIE_V1)
 331                 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
 332         else
 333                 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
 334 
 335         headers[0] = TLP_CFG_DW0(pcie, cfg);
 336         headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
 337         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 338 }
 339 
 340 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
 341                               int where, u8 byte_en, u32 *value)
 342 {
 343         u32 headers[TLP_HDR_SIZE];
 344 
 345         get_tlp_header(pcie, bus, devfn, where, byte_en, true,
 346                        headers);
 347 
 348         pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
 349 
 350         return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
 351 }
 352 
 353 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
 354                                int where, u8 byte_en, u32 value)
 355 {
 356         u32 headers[TLP_HDR_SIZE];
 357         int ret;
 358 
 359         get_tlp_header(pcie, bus, devfn, where, byte_en, false,
 360                        headers);
 361 
 362         /* check alignment to Qword */
 363         if ((where & 0x7) == 0)
 364                 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
 365                                                     value, true);
 366         else
 367                 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
 368                                                     value, false);
 369 
 370         ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
 371         if (ret != PCIBIOS_SUCCESSFUL)
 372                 return ret;
 373 
 374         /*
 375          * Monitor changes to PCI_PRIMARY_BUS register on root port
 376          * and update local copy of root bus number accordingly.
 377          */
 378         if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
 379                 pcie->root_bus_nr = (u8)(value);
 380 
 381         return PCIBIOS_SUCCESSFUL;
 382 }
 383 
 384 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,
 385                            int size, u32 *value)
 386 {
 387         void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
 388 
 389         switch (size) {
 390         case 1:
 391                 *value = readb(addr);
 392                 break;
 393         case 2:
 394                 *value = readw(addr);
 395                 break;
 396         default:
 397                 *value = readl(addr);
 398                 break;
 399         }
 400 
 401         return PCIBIOS_SUCCESSFUL;
 402 }
 403 
 404 static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
 405                             int where, int size, u32 value)
 406 {
 407         void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
 408 
 409         switch (size) {
 410         case 1:
 411                 writeb(value, addr);
 412                 break;
 413         case 2:
 414                 writew(value, addr);
 415                 break;
 416         default:
 417                 writel(value, addr);
 418                 break;
 419         }
 420 
 421         /*
 422          * Monitor changes to PCI_PRIMARY_BUS register on root port
 423          * and update local copy of root bus number accordingly.
 424          */
 425         if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
 426                 pcie->root_bus_nr = value & 0xff;
 427 
 428         return PCIBIOS_SUCCESSFUL;
 429 }
 430 
 431 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
 432                                  unsigned int devfn, int where, int size,
 433                                  u32 *value)
 434 {
 435         int ret;
 436         u32 data;
 437         u8 byte_en;
 438 
 439         if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
 440                 return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
 441                                                          size, value);
 442 
 443         switch (size) {
 444         case 1:
 445                 byte_en = 1 << (where & 3);
 446                 break;
 447         case 2:
 448                 byte_en = 3 << (where & 3);
 449                 break;
 450         default:
 451                 byte_en = 0xf;
 452                 break;
 453         }
 454 
 455         ret = tlp_cfg_dword_read(pcie, busno, devfn,
 456                                  (where & ~DWORD_MASK), byte_en, &data);
 457         if (ret != PCIBIOS_SUCCESSFUL)
 458                 return ret;
 459 
 460         switch (size) {
 461         case 1:
 462                 *value = (data >> (8 * (where & 0x3))) & 0xff;
 463                 break;
 464         case 2:
 465                 *value = (data >> (8 * (where & 0x2))) & 0xffff;
 466                 break;
 467         default:
 468                 *value = data;
 469                 break;
 470         }
 471 
 472         return PCIBIOS_SUCCESSFUL;
 473 }
 474 
 475 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
 476                                   unsigned int devfn, int where, int size,
 477                                   u32 value)
 478 {
 479         u32 data32;
 480         u32 shift = 8 * (where & 3);
 481         u8 byte_en;
 482 
 483         if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
 484                 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
 485                                                      where, size, value);
 486 
 487         switch (size) {
 488         case 1:
 489                 data32 = (value & 0xff) << shift;
 490                 byte_en = 1 << (where & 3);
 491                 break;
 492         case 2:
 493                 data32 = (value & 0xffff) << shift;
 494                 byte_en = 3 << (where & 3);
 495                 break;
 496         default:
 497                 data32 = value;
 498                 byte_en = 0xf;
 499                 break;
 500         }
 501 
 502         return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
 503                                    byte_en, data32);
 504 }
 505 
 506 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
 507                                 int where, int size, u32 *value)
 508 {
 509         struct altera_pcie *pcie = bus->sysdata;
 510 
 511         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 512                 return PCIBIOS_BAD_REGISTER_NUMBER;
 513 
 514         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
 515                 *value = 0xffffffff;
 516                 return PCIBIOS_DEVICE_NOT_FOUND;
 517         }
 518 
 519         return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
 520                                      value);
 521 }
 522 
 523 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
 524                                  int where, int size, u32 value)
 525 {
 526         struct altera_pcie *pcie = bus->sysdata;
 527 
 528         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 529                 return PCIBIOS_BAD_REGISTER_NUMBER;
 530 
 531         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
 532                 return PCIBIOS_DEVICE_NOT_FOUND;
 533 
 534         return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
 535                                      value);
 536 }
 537 
 538 static struct pci_ops altera_pcie_ops = {
 539         .read = altera_pcie_cfg_read,
 540         .write = altera_pcie_cfg_write,
 541 };
 542 
 543 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
 544                                 unsigned int devfn, int offset, u16 *value)
 545 {
 546         u32 data;
 547         int ret;
 548 
 549         ret = _altera_pcie_cfg_read(pcie, busno, devfn,
 550                                     pcie->pcie_data->cap_offset + offset,
 551                                     sizeof(*value),
 552                                     &data);
 553         *value = data;
 554         return ret;
 555 }
 556 
 557 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
 558                                  unsigned int devfn, int offset, u16 value)
 559 {
 560         return _altera_pcie_cfg_write(pcie, busno, devfn,
 561                                       pcie->pcie_data->cap_offset + offset,
 562                                       sizeof(value),
 563                                       value);
 564 }
 565 
 566 static void altera_wait_link_retrain(struct altera_pcie *pcie)
 567 {
 568         struct device *dev = &pcie->pdev->dev;
 569         u16 reg16;
 570         unsigned long start_jiffies;
 571 
 572         /* Wait for link training end. */
 573         start_jiffies = jiffies;
 574         for (;;) {
 575                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 576                                      PCI_EXP_LNKSTA, &reg16);
 577                 if (!(reg16 & PCI_EXP_LNKSTA_LT))
 578                         break;
 579 
 580                 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
 581                         dev_err(dev, "link retrain timeout\n");
 582                         break;
 583                 }
 584                 udelay(100);
 585         }
 586 
 587         /* Wait for link is up */
 588         start_jiffies = jiffies;
 589         for (;;) {
 590                 if (pcie->pcie_data->ops->get_link_status(pcie))
 591                         break;
 592 
 593                 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
 594                         dev_err(dev, "link up timeout\n");
 595                         break;
 596                 }
 597                 udelay(100);
 598         }
 599 }
 600 
 601 static void altera_pcie_retrain(struct altera_pcie *pcie)
 602 {
 603         u16 linkcap, linkstat, linkctl;
 604 
 605         if (!pcie->pcie_data->ops->get_link_status(pcie))
 606                 return;
 607 
 608         /*
 609          * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
 610          * current speed is 2.5 GB/s.
 611          */
 612         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
 613                              &linkcap);
 614         if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
 615                 return;
 616 
 617         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
 618                              &linkstat);
 619         if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
 620                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 621                                      PCI_EXP_LNKCTL, &linkctl);
 622                 linkctl |= PCI_EXP_LNKCTL_RL;
 623                 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 624                                       PCI_EXP_LNKCTL, linkctl);
 625 
 626                 altera_wait_link_retrain(pcie);
 627         }
 628 }
 629 
 630 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 631                                 irq_hw_number_t hwirq)
 632 {
 633         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 634         irq_set_chip_data(irq, domain->host_data);
 635         return 0;
 636 }
 637 
 638 static const struct irq_domain_ops intx_domain_ops = {
 639         .map = altera_pcie_intx_map,
 640         .xlate = pci_irqd_intx_xlate,
 641 };
 642 
 643 static void altera_pcie_isr(struct irq_desc *desc)
 644 {
 645         struct irq_chip *chip = irq_desc_get_chip(desc);
 646         struct altera_pcie *pcie;
 647         struct device *dev;
 648         unsigned long status;
 649         u32 bit;
 650         u32 virq;
 651 
 652         chained_irq_enter(chip, desc);
 653         pcie = irq_desc_get_handler_data(desc);
 654         dev = &pcie->pdev->dev;
 655 
 656         while ((status = cra_readl(pcie, P2A_INT_STATUS)
 657                 & P2A_INT_STS_ALL) != 0) {
 658                 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
 659                         /* clear interrupts */
 660                         cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
 661 
 662                         virq = irq_find_mapping(pcie->irq_domain, bit);
 663                         if (virq)
 664                                 generic_handle_irq(virq);
 665                         else
 666                                 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
 667                 }
 668         }
 669 
 670         chained_irq_exit(chip, desc);
 671 }
 672 
 673 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
 674 {
 675         int err, res_valid = 0;
 676         struct device *dev = &pcie->pdev->dev;
 677         struct resource_entry *win;
 678 
 679         err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
 680                                                     &pcie->resources, NULL);
 681         if (err)
 682                 return err;
 683 
 684         err = devm_request_pci_bus_resources(dev, &pcie->resources);
 685         if (err)
 686                 goto out_release_res;
 687 
 688         resource_list_for_each_entry(win, &pcie->resources) {
 689                 struct resource *res = win->res;
 690 
 691                 if (resource_type(res) == IORESOURCE_MEM)
 692                         res_valid |= !(res->flags & IORESOURCE_PREFETCH);
 693         }
 694 
 695         if (res_valid)
 696                 return 0;
 697 
 698         dev_err(dev, "non-prefetchable memory resource required\n");
 699         err = -EINVAL;
 700 
 701 out_release_res:
 702         pci_free_resource_list(&pcie->resources);
 703         return err;
 704 }
 705 
 706 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
 707 {
 708         struct device *dev = &pcie->pdev->dev;
 709         struct device_node *node = dev->of_node;
 710 
 711         /* Setup INTx */
 712         pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
 713                                         &intx_domain_ops, pcie);
 714         if (!pcie->irq_domain) {
 715                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 716                 return -ENOMEM;
 717         }
 718 
 719         return 0;
 720 }
 721 
 722 static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
 723 {
 724         irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
 725         irq_domain_remove(pcie->irq_domain);
 726         irq_dispose_mapping(pcie->irq);
 727 }
 728 
 729 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 730 {
 731         struct device *dev = &pcie->pdev->dev;
 732         struct platform_device *pdev = pcie->pdev;
 733         struct resource *cra;
 734         struct resource *hip;
 735 
 736         cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
 737         pcie->cra_base = devm_ioremap_resource(dev, cra);
 738         if (IS_ERR(pcie->cra_base))
 739                 return PTR_ERR(pcie->cra_base);
 740 
 741         if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
 742                 hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
 743                 pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
 744                 if (IS_ERR(pcie->hip_base))
 745                         return PTR_ERR(pcie->hip_base);
 746         }
 747 
 748         /* setup IRQ */
 749         pcie->irq = platform_get_irq(pdev, 0);
 750         if (pcie->irq < 0) {
 751                 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq);
 752                 return pcie->irq;
 753         }
 754 
 755         irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
 756         return 0;
 757 }
 758 
 759 static void altera_pcie_host_init(struct altera_pcie *pcie)
 760 {
 761         altera_pcie_retrain(pcie);
 762 }
 763 
 764 static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
 765         .tlp_read_pkt = tlp_read_packet,
 766         .tlp_write_pkt = tlp_write_packet,
 767         .get_link_status = altera_pcie_link_up,
 768 };
 769 
 770 static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
 771         .tlp_read_pkt = s10_tlp_read_packet,
 772         .tlp_write_pkt = s10_tlp_write_packet,
 773         .get_link_status = s10_altera_pcie_link_up,
 774         .rp_read_cfg = s10_rp_read_cfg,
 775         .rp_write_cfg = s10_rp_write_cfg,
 776 };
 777 
 778 static const struct altera_pcie_data altera_pcie_1_0_data = {
 779         .ops = &altera_pcie_ops_1_0,
 780         .cap_offset = 0x80,
 781         .version = ALTERA_PCIE_V1,
 782         .cfgrd0 = TLP_FMTTYPE_CFGRD0,
 783         .cfgrd1 = TLP_FMTTYPE_CFGRD1,
 784         .cfgwr0 = TLP_FMTTYPE_CFGWR0,
 785         .cfgwr1 = TLP_FMTTYPE_CFGWR1,
 786 };
 787 
 788 static const struct altera_pcie_data altera_pcie_2_0_data = {
 789         .ops = &altera_pcie_ops_2_0,
 790         .version = ALTERA_PCIE_V2,
 791         .cap_offset = 0x70,
 792         .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
 793         .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
 794         .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
 795         .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
 796 };
 797 
 798 static const struct of_device_id altera_pcie_of_match[] = {
 799         {.compatible = "altr,pcie-root-port-1.0",
 800          .data = &altera_pcie_1_0_data },
 801         {.compatible = "altr,pcie-root-port-2.0",
 802          .data = &altera_pcie_2_0_data },
 803         {},
 804 };
 805 
 806 static int altera_pcie_probe(struct platform_device *pdev)
 807 {
 808         struct device *dev = &pdev->dev;
 809         struct altera_pcie *pcie;
 810         struct pci_bus *bus;
 811         struct pci_bus *child;
 812         struct pci_host_bridge *bridge;
 813         int ret;
 814         const struct of_device_id *match;
 815 
 816         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 817         if (!bridge)
 818                 return -ENOMEM;
 819 
 820         pcie = pci_host_bridge_priv(bridge);
 821         pcie->pdev = pdev;
 822         platform_set_drvdata(pdev, pcie);
 823 
 824         match = of_match_device(altera_pcie_of_match, &pdev->dev);
 825         if (!match)
 826                 return -ENODEV;
 827 
 828         pcie->pcie_data = match->data;
 829 
 830         ret = altera_pcie_parse_dt(pcie);
 831         if (ret) {
 832                 dev_err(dev, "Parsing DT failed\n");
 833                 return ret;
 834         }
 835 
 836         INIT_LIST_HEAD(&pcie->resources);
 837 
 838         ret = altera_pcie_parse_request_of_pci_ranges(pcie);
 839         if (ret) {
 840                 dev_err(dev, "Failed add resources\n");
 841                 return ret;
 842         }
 843 
 844         ret = altera_pcie_init_irq_domain(pcie);
 845         if (ret) {
 846                 dev_err(dev, "Failed creating IRQ Domain\n");
 847                 return ret;
 848         }
 849 
 850         /* clear all interrupts */
 851         cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
 852         /* enable all interrupts */
 853         cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
 854         altera_pcie_host_init(pcie);
 855 
 856         list_splice_init(&pcie->resources, &bridge->windows);
 857         bridge->dev.parent = dev;
 858         bridge->sysdata = pcie;
 859         bridge->busnr = pcie->root_bus_nr;
 860         bridge->ops = &altera_pcie_ops;
 861         bridge->map_irq = of_irq_parse_and_map_pci;
 862         bridge->swizzle_irq = pci_common_swizzle;
 863 
 864         ret = pci_scan_root_bus_bridge(bridge);
 865         if (ret < 0)
 866                 return ret;
 867 
 868         bus = bridge->bus;
 869 
 870         pci_assign_unassigned_bus_resources(bus);
 871 
 872         /* Configure PCI Express setting. */
 873         list_for_each_entry(child, &bus->children, node)
 874                 pcie_bus_configure_settings(child);
 875 
 876         pci_bus_add_devices(bus);
 877         return ret;
 878 }
 879 
 880 static int altera_pcie_remove(struct platform_device *pdev)
 881 {
 882         struct altera_pcie *pcie = platform_get_drvdata(pdev);
 883         struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
 884 
 885         pci_stop_root_bus(bridge->bus);
 886         pci_remove_root_bus(bridge->bus);
 887         pci_free_resource_list(&pcie->resources);
 888         altera_pcie_irq_teardown(pcie);
 889 
 890         return 0;
 891 }
 892 
 893 static struct platform_driver altera_pcie_driver = {
 894         .probe          = altera_pcie_probe,
 895         .remove         = altera_pcie_remove,
 896         .driver = {
 897                 .name   = "altera-pcie",
 898                 .of_match_table = altera_pcie_of_match,
 899         },
 900 };
 901 
 902 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
 903 module_platform_driver(altera_pcie_driver);
 904 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pci/controller/pcie-altera.c

DEFINITIONS
