root/drivers/pci/quirks.c

DEFINITIONS

1. fixup_debug_start
2. fixup_debug_report
3. pci_do_fixups
4. pci_fixup_device
5. pci_apply_final_quirks
6. quirk_mmio_always_on
7. quirk_mellanox_tavor
8. quirk_passive_release
9. quirk_isa_dma_hangs
10. quirk_tigerpoint_bm_sts
11. quirk_nopcipci
12. quirk_nopciamd
13. quirk_triton
14. quirk_vialatency
15. quirk_viaetbf
16. quirk_vsfx
17. quirk_alimagik
18. quirk_natoma
19. quirk_citrine
20. quirk_nfp6000
21. quirk_extend_bar_to_page
22. quirk_s3_64M
23. quirk_io
24. quirk_cs5536_vsa
25. quirk_io_region
26. quirk_ati_exploding_mce
27. quirk_amd_nl_class
28. quirk_synopsys_haps
29. quirk_ali7101_acpi
30. piix4_io_quirk
31. piix4_mem_quirk
32. quirk_piix4_acpi
33. quirk_ich4_lpc_acpi
34. ich6_lpc_acpi_gpio
35. ich6_lpc_generic_decode
36. quirk_ich6_lpc
37. ich7_lpc_generic_decode
38. quirk_ich7_lpc
39. quirk_vt82c586_acpi
40. quirk_vt82c686_acpi
41. quirk_vt8235_acpi
42. quirk_xio2000a
43. quirk_via_ioapic
44. quirk_via_vt8237_bypass_apic_deassert
45. quirk_amd_ioapic
46. quirk_cavium_sriov_rnm_link
47. quirk_amd_8131_mmrbc
48. quirk_via_acpi
49. quirk_via_bridge
50. quirk_via_vlink
51. quirk_vt82c598_id
52. quirk_cardbus_legacy
53. quirk_amd_ordering
54. quirk_dunord
55. quirk_transparent_bridge
56. quirk_mediagx_master
57. quirk_disable_pxb
58. quirk_amd_ide_mode
59. quirk_svwks_csb5ide
60. quirk_ide_samemode
61. quirk_no_ata_d3
62. quirk_eisa_bridge
63. asus_hides_smbus_hostbridge
64. asus_hides_smbus_lpc
65. asus_hides_smbus_lpc_ich6_suspend
66. asus_hides_smbus_lpc_ich6_resume_early
67. asus_hides_smbus_lpc_ich6_resume
68. asus_hides_smbus_lpc_ich6
69. quirk_sis_96x_smbus
70. quirk_sis_503
71. asus_hides_ac97_lpc
72. quirk_jmicron_ata
73. quirk_jmicron_async_suspend
74. quirk_alder_ioapic
75. quirk_pcie_mch
76. quirk_pcie_pxh
77. quirk_intel_pcie_pm
78. quirk_d3hot_delay
79. quirk_radeon_pm
80. quirk_ryzen_xhci_d3hot
81. dmi_disable_ioapicreroute
82. quirk_reroute_to_boot_interrupts_intel
83. quirk_disable_intel_boot_interrupt
84. quirk_disable_broadcom_boot_interrupt
85. quirk_disable_amd_813x_boot_interrupt
86. quirk_disable_amd_8111_boot_interrupt
87. quirk_tc86c001_ide
88. quirk_plx_pci9050
89. quirk_netmos
90. quirk_e100_interrupt
91. quirk_disable_aspm_l0s
92. quirk_enable_clear_retrain_link
93. fixup_rev1_53c810
94. quirk_p64h2_1k_io
95. quirk_nvidia_ck804_pcie_aer_ext_cap
96. quirk_via_cx700_pci_parking_caching
97. quirk_brcm_5719_limit_mrrs
98. quirk_unhide_mch_dev6
99. quirk_disable_all_msi
100. quirk_disable_msi
101. quirk_amd_780_apc_msi
102. msi_ht_cap_enabled
103. quirk_msi_ht_cap
104. quirk_nvidia_ck804_msi_ht_cap
105. ht_enable_msi_mapping
106. nvenet_msi_disable
107. pci_quirk_nvidia_tegra_disable_rp_msi
108. nvbridge_check_legacy_irq_routing
109. ht_check_msi_mapping
110. host_bridge_with_leaf
111. is_end_of_ht_chain
112. nv_ht_enable_msi_mapping
113. ht_disable_msi_mapping
114. __nv_msi_ht_cap_quirk
115. nv_msi_ht_cap_quirk_all
116. nv_msi_ht_cap_quirk_leaf
117. quirk_msi_intx_disable_bug
118. quirk_msi_intx_disable_ati_bug
119. quirk_msi_intx_disable_qca_bug
120. quirk_al_msi_disable
121. quirk_hotplug_bridge
122. ricoh_mmc_fixup_rl5c476
123. ricoh_mmc_fixup_r5c832
124. vtd_mask_spec_errors
125. fixup_ti816x_class
126. fixup_mpss_256
127. quirk_intel_mc_errata
128. quirk_intel_ntb
129. disable_igfx_irq
130. quirk_remove_d3_delay
131. quirk_broken_intx_masking
132. mellanox_check_broken_intx_masking
133. quirk_no_bus_reset
134. quirk_no_pm_reset
135. quirk_thunderbolt_hotplug_msi
136. quirk_apple_poweroff_thunderbolt
137. quirk_apple_wait_for_thunderbolt
138. reset_intel_82599_sfp_virtfn
139. reset_ivb_igd
140. reset_chelsio_generic_dev
141. nvme_disable_and_flr
142. delay_250ms_after_flr
143. pci_dev_specific_reset
144. quirk_dma_func0_alias
145. quirk_dma_func1_alias
146. quirk_fixed_dma_alias
147. quirk_use_pcie_bridge_dma_alias
148. quirk_mic_x200_dma_alias
149. quirk_pex_vca_alias
150. quirk_bridge_cavm_thrx2_pcie_root
151. quirk_tw686x_class
152. quirk_relaxedordering_disable
153. quirk_disable_root_port_attributes
154. quirk_chelsio_T5_disable_root_port_attributes
155. pci_acs_ctrl_enabled
156. pci_quirk_zhaoxin_pcie_ports_acs
157. pci_quirk_amd_sb_acs
158. pci_quirk_cavium_acs_match
159. pci_quirk_cavium_acs
160. pci_quirk_xgene_acs
161. pci_quirk_intel_pch_acs_match
162. pci_quirk_intel_pch_acs
163. pci_quirk_qcom_rp_acs
164. pci_quirk_al_acs
165. pci_quirk_intel_spt_pch_acs_match
166. pci_quirk_intel_spt_pch_acs
167. pci_quirk_mf_endpoint_acs
168. pci_quirk_brcm_acs
169. pci_dev_specific_acs_enabled
170. pci_quirk_enable_intel_lpc_acs
171. pci_quirk_enable_intel_rp_mpc_acs
172. pci_quirk_enable_intel_pch_acs
173. pci_quirk_enable_intel_spt_pch_acs
174. pci_quirk_disable_intel_spt_pch_acs_redir
175. pci_dev_specific_enable_acs
176. pci_dev_specific_disable_acs_redir
177. quirk_intel_qat_vf_cap
178. quirk_intel_no_flr
179. quirk_no_ext_tags
180. quirk_amd_harvest_no_ats
181. quirk_fsl_no_msi
182. pci_create_device_link
183. quirk_gpu_hda
184. quirk_gpu_usb
185. quirk_gpu_usb_typec_ucsi
186. quirk_nvidia_hda
187. pci_idt_bus_quirk
188. quirk_switchtec_ntb_dma_alias
189. quirk_plx_ntb_dma_alias
190. quirk_reset_lenovo_thinkpad_p50_nvgpu
191. pci_fixup_no_d0_pme
192. apex_pci_fixup_class

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file contains work-arounds for many known PCI hardware bugs.
   4  * Devices present only on certain architectures (host bridges et cetera)
   5  * should be handled in arch-specific code.
   6  *
   7  * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
   8  *
   9  * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
  10  *
  11  * Init/reset quirks for USB host controllers should be in the USB quirks
  12  * file, where their drivers can use them.
  13  */
  14 
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/export.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/acpi.h>
  22 #include <linux/dmi.h>
  23 #include <linux/ioport.h>
  24 #include <linux/sched.h>
  25 #include <linux/ktime.h>
  26 #include <linux/mm.h>
  27 #include <linux/nvme.h>
  28 #include <linux/platform_data/x86/apple.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/switchtec.h>
  31 #include <asm/dma.h>    /* isa_dma_bridge_buggy */
  32 #include "pci.h"
  33 
  34 static ktime_t fixup_debug_start(struct pci_dev *dev,
  35                                  void (*fn)(struct pci_dev *dev))
  36 {
  37         if (initcall_debug)
  38                 pci_info(dev, "calling  %pS @ %i\n", fn, task_pid_nr(current));
  39 
  40         return ktime_get();
  41 }
  42 
  43 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
  44                                void (*fn)(struct pci_dev *dev))
  45 {
  46         ktime_t delta, rettime;
  47         unsigned long long duration;
  48 
  49         rettime = ktime_get();
  50         delta = ktime_sub(rettime, calltime);
  51         duration = (unsigned long long) ktime_to_ns(delta) >> 10;
  52         if (initcall_debug || duration > 10000)
  53                 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
  54 }
  55 
  56 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
  57                           struct pci_fixup *end)
  58 {
  59         ktime_t calltime;
  60 
  61         for (; f < end; f++)
  62                 if ((f->class == (u32) (dev->class >> f->class_shift) ||
  63                      f->class == (u32) PCI_ANY_ID) &&
  64                     (f->vendor == dev->vendor ||
  65                      f->vendor == (u16) PCI_ANY_ID) &&
  66                     (f->device == dev->device ||
  67                      f->device == (u16) PCI_ANY_ID)) {
  68                         void (*hook)(struct pci_dev *dev);
  69 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
  70                         hook = offset_to_ptr(&f->hook_offset);
  71 #else
  72                         hook = f->hook;
  73 #endif
  74                         calltime = fixup_debug_start(dev, hook);
  75                         hook(dev);
  76                         fixup_debug_report(dev, calltime, hook);
  77                 }
  78 }
  79 
  80 extern struct pci_fixup __start_pci_fixups_early[];
  81 extern struct pci_fixup __end_pci_fixups_early[];
  82 extern struct pci_fixup __start_pci_fixups_header[];
  83 extern struct pci_fixup __end_pci_fixups_header[];
  84 extern struct pci_fixup __start_pci_fixups_final[];
  85 extern struct pci_fixup __end_pci_fixups_final[];
  86 extern struct pci_fixup __start_pci_fixups_enable[];
  87 extern struct pci_fixup __end_pci_fixups_enable[];
  88 extern struct pci_fixup __start_pci_fixups_resume[];
  89 extern struct pci_fixup __end_pci_fixups_resume[];
  90 extern struct pci_fixup __start_pci_fixups_resume_early[];
  91 extern struct pci_fixup __end_pci_fixups_resume_early[];
  92 extern struct pci_fixup __start_pci_fixups_suspend[];
  93 extern struct pci_fixup __end_pci_fixups_suspend[];
  94 extern struct pci_fixup __start_pci_fixups_suspend_late[];
  95 extern struct pci_fixup __end_pci_fixups_suspend_late[];
  96 
  97 static bool pci_apply_fixup_final_quirks;
  98 
  99 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
 100 {
 101         struct pci_fixup *start, *end;
 102 
 103         switch (pass) {
 104         case pci_fixup_early:
 105                 start = __start_pci_fixups_early;
 106                 end = __end_pci_fixups_early;
 107                 break;
 108 
 109         case pci_fixup_header:
 110                 start = __start_pci_fixups_header;
 111                 end = __end_pci_fixups_header;
 112                 break;
 113 
 114         case pci_fixup_final:
 115                 if (!pci_apply_fixup_final_quirks)
 116                         return;
 117                 start = __start_pci_fixups_final;
 118                 end = __end_pci_fixups_final;
 119                 break;
 120 
 121         case pci_fixup_enable:
 122                 start = __start_pci_fixups_enable;
 123                 end = __end_pci_fixups_enable;
 124                 break;
 125 
 126         case pci_fixup_resume:
 127                 start = __start_pci_fixups_resume;
 128                 end = __end_pci_fixups_resume;
 129                 break;
 130 
 131         case pci_fixup_resume_early:
 132                 start = __start_pci_fixups_resume_early;
 133                 end = __end_pci_fixups_resume_early;
 134                 break;
 135 
 136         case pci_fixup_suspend:
 137                 start = __start_pci_fixups_suspend;
 138                 end = __end_pci_fixups_suspend;
 139                 break;
 140 
 141         case pci_fixup_suspend_late:
 142                 start = __start_pci_fixups_suspend_late;
 143                 end = __end_pci_fixups_suspend_late;
 144                 break;
 145 
 146         default:
 147                 /* stupid compiler warning, you would think with an enum... */
 148                 return;
 149         }
 150         pci_do_fixups(dev, start, end);
 151 }
 152 EXPORT_SYMBOL(pci_fixup_device);
 153 
 154 static int __init pci_apply_final_quirks(void)
 155 {
 156         struct pci_dev *dev = NULL;
 157         u8 cls = 0;
 158         u8 tmp;
 159 
 160         if (pci_cache_line_size)
 161                 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
 162 
 163         pci_apply_fixup_final_quirks = true;
 164         for_each_pci_dev(dev) {
 165                 pci_fixup_device(pci_fixup_final, dev);
 166                 /*
 167                  * If arch hasn't set it explicitly yet, use the CLS
 168                  * value shared by all PCI devices.  If there's a
 169                  * mismatch, fall back to the default value.
 170                  */
 171                 if (!pci_cache_line_size) {
 172                         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
 173                         if (!cls)
 174                                 cls = tmp;
 175                         if (!tmp || cls == tmp)
 176                                 continue;
 177 
 178                         pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
 179                                  cls << 2, tmp << 2,
 180                                  pci_dfl_cache_line_size << 2);
 181                         pci_cache_line_size = pci_dfl_cache_line_size;
 182                 }
 183         }
 184 
 185         if (!pci_cache_line_size) {
 186                 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
 187                         pci_dfl_cache_line_size << 2);
 188                 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
 189         }
 190 
 191         return 0;
 192 }
 193 fs_initcall_sync(pci_apply_final_quirks);
 194 
 195 /*
 196  * Decoding should be disabled for a PCI device during BAR sizing to avoid
 197  * conflict. But doing so may cause problems on host bridge and perhaps other
 198  * key system devices. For devices that need to have mmio decoding always-on,
 199  * we need to set the dev->mmio_always_on bit.
 200  */
 201 static void quirk_mmio_always_on(struct pci_dev *dev)
 202 {
 203         dev->mmio_always_on = 1;
 204 }
 205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
 206                                 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
 207 
 208 /*
 209  * The Mellanox Tavor device gives false positive parity errors.  Mark this
 210  * device with a broken_parity_status to allow PCI scanning code to "skip"
 211  * this now blacklisted device.
 212  */
 213 static void quirk_mellanox_tavor(struct pci_dev *dev)
 214 {
 215         dev->broken_parity_status = 1;  /* This device gives false positives */
 216 }
 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
 219 
 220 /*
 221  * Deal with broken BIOSes that neglect to enable passive release,
 222  * which can cause problems in combination with the 82441FX/PPro MTRRs
 223  */
 224 static void quirk_passive_release(struct pci_dev *dev)
 225 {
 226         struct pci_dev *d = NULL;
 227         unsigned char dlc;
 228 
 229         /*
 230          * We have to make sure a particular bit is set in the PIIX3
 231          * ISA bridge, so we have to go out and find it.
 232          */
 233         while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
 234                 pci_read_config_byte(d, 0x82, &dlc);
 235                 if (!(dlc & 1<<1)) {
 236                         pci_info(d, "PIIX3: Enabling Passive Release\n");
 237                         dlc |= 1<<1;
 238                         pci_write_config_byte(d, 0x82, dlc);
 239                 }
 240         }
 241 }
 242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
 243 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
 244 
 245 /*
 246  * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
 247  * workaround but VIA don't answer queries. If you happen to have good
 248  * contacts at VIA ask them for me please -- Alan
 249  *
 250  * This appears to be BIOS not version dependent. So presumably there is a
 251  * chipset level fix.
 252  */
 253 static void quirk_isa_dma_hangs(struct pci_dev *dev)
 254 {
 255         if (!isa_dma_bridge_buggy) {
 256                 isa_dma_bridge_buggy = 1;
 257                 pci_info(dev, "Activating ISA DMA hang workarounds\n");
 258         }
 259 }
 260 /*
 261  * It's not totally clear which chipsets are the problematic ones.  We know
 262  * 82C586 and 82C596 variants are affected.
 263  */
 264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs);
 265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs);
 266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
 267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1533,         quirk_isa_dma_hangs);
 268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs);
 269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs);
 270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs);
 271 
 272 /*
 273  * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
 274  * for some HT machines to use C4 w/o hanging.
 275  */
 276 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
 277 {
 278         u32 pmbase;
 279         u16 pm1a;
 280 
 281         pci_read_config_dword(dev, 0x40, &pmbase);
 282         pmbase = pmbase & 0xff80;
 283         pm1a = inw(pmbase);
 284 
 285         if (pm1a & 0x10) {
 286                 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
 287                 outw(0x10, pmbase);
 288         }
 289 }
 290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
 291 
 292 /* Chipsets where PCI->PCI transfers vanish or hang */
 293 static void quirk_nopcipci(struct pci_dev *dev)
 294 {
 295         if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
 296                 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
 297                 pci_pci_problems |= PCIPCI_FAIL;
 298         }
 299 }
 300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci);
 301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci);
 302 
 303 static void quirk_nopciamd(struct pci_dev *dev)
 304 {
 305         u8 rev;
 306         pci_read_config_byte(dev, 0x08, &rev);
 307         if (rev == 0x13) {
 308                 /* Erratum 24 */
 309                 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
 310                 pci_pci_problems |= PCIAGP_FAIL;
 311         }
 312 }
 313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8151_0,       quirk_nopciamd);
 314 
 315 /* Triton requires workarounds to be used by the drivers */
 316 static void quirk_triton(struct pci_dev *dev)
 317 {
 318         if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
 319                 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
 320                 pci_pci_problems |= PCIPCI_TRITON;
 321         }
 322 }
 323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton);
 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton);
 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton);
 326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton);
 327 
 328 /*
 329  * VIA Apollo KT133 needs PCI latency patch
 330  * Made according to a Windows driver-based patch by George E. Breese;
 331  * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 332  * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
 333  * which Mr Breese based his work.
 334  *
 335  * Updated based on further information from the site and also on
 336  * information provided by VIA
 337  */
 338 static void quirk_vialatency(struct pci_dev *dev)
 339 {
 340         struct pci_dev *p;
 341         u8 busarb;
 342 
 343         /*
 344          * Ok, we have a potential problem chipset here. Now see if we have
 345          * a buggy southbridge.
 346          */
 347         p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
 348         if (p != NULL) {
 349 
 350                 /*
 351                  * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
 352                  * thanks Dan Hollis.
 353                  * Check for buggy part revisions
 354                  */
 355                 if (p->revision < 0x40 || p->revision > 0x42)
 356                         goto exit;
 357         } else {
 358                 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
 359                 if (p == NULL)  /* No problem parts */
 360                         goto exit;
 361 
 362                 /* Check for buggy part revisions */
 363                 if (p->revision < 0x10 || p->revision > 0x12)
 364                         goto exit;
 365         }
 366 
 367         /*
 368          * Ok we have the problem. Now set the PCI master grant to occur
 369          * every master grant. The apparent bug is that under high PCI load
 370          * (quite common in Linux of course) you can get data loss when the
 371          * CPU is held off the bus for 3 bus master requests.  This happens
 372          * to include the IDE controllers....
 373          *
 374          * VIA only apply this fix when an SB Live! is present but under
 375          * both Linux and Windows this isn't enough, and we have seen
 376          * corruption without SB Live! but with things like 3 UDMA IDE
 377          * controllers. So we ignore that bit of the VIA recommendation..
 378          */
 379         pci_read_config_byte(dev, 0x76, &busarb);
 380 
 381         /*
 382          * Set bit 4 and bit 5 of byte 76 to 0x01
 383          * "Master priority rotation on every PCI master grant"
 384          */
 385         busarb &= ~(1<<5);
 386         busarb |= (1<<4);
 387         pci_write_config_byte(dev, 0x76, busarb);
 388         pci_info(dev, "Applying VIA southbridge workaround\n");
 389 exit:
 390         pci_dev_put(p);
 391 }
 392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 395 /* Must restore this on a resume from RAM */
 396 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 397 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 398 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 399 
 400 /* VIA Apollo VP3 needs ETBF on BT848/878 */
 401 static void quirk_viaetbf(struct pci_dev *dev)
 402 {
 403         if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
 404                 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
 405                 pci_pci_problems |= PCIPCI_VIAETBF;
 406         }
 407 }
 408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_viaetbf);
 409 
 410 static void quirk_vsfx(struct pci_dev *dev)
 411 {
 412         if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
 413                 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
 414                 pci_pci_problems |= PCIPCI_VSFX;
 415         }
 416 }
 417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C576,       quirk_vsfx);
 418 
 419 /*
 420  * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
 421  * space. Latency must be set to 0xA and Triton workaround applied too.
 422  * [Info kindly provided by ALi]
 423  */
 424 static void quirk_alimagik(struct pci_dev *dev)
 425 {
 426         if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
 427                 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
 428                 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
 429         }
 430 }
 431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik);
 432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik);
 433 
 434 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
 435 static void quirk_natoma(struct pci_dev *dev)
 436 {
 437         if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
 438                 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
 439                 pci_pci_problems |= PCIPCI_NATOMA;
 440         }
 441 }
 442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma);
 443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma);
 444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma);
 445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma);
 446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma);
 447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma);
 448 
 449 /*
 450  * This chip can cause PCI parity errors if config register 0xA0 is read
 451  * while DMAs are occurring.
 452  */
 453 static void quirk_citrine(struct pci_dev *dev)
 454 {
 455         dev->cfg_size = 0xA0;
 456 }
 457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CITRINE,      quirk_citrine);
 458 
 459 /*
 460  * This chip can cause bus lockups if config addresses above 0x600
 461  * are read or written.
 462  */
 463 static void quirk_nfp6000(struct pci_dev *dev)
 464 {
 465         dev->cfg_size = 0x600;
 466 }
 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP4000,        quirk_nfp6000);
 468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP6000,        quirk_nfp6000);
 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP5000,        quirk_nfp6000);
 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP6000_VF,     quirk_nfp6000);
 471 
 472 /*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
 473 static void quirk_extend_bar_to_page(struct pci_dev *dev)
 474 {
 475         int i;
 476 
 477         for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
 478                 struct resource *r = &dev->resource[i];
 479 
 480                 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
 481                         r->end = PAGE_SIZE - 1;
 482                         r->start = 0;
 483                         r->flags |= IORESOURCE_UNSET;
 484                         pci_info(dev, "expanded BAR %d to page size: %pR\n",
 485                                  i, r);
 486                 }
 487         }
 488 }
 489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
 490 
 491 /*
 492  * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 493  * If it's needed, re-allocate the region.
 494  */
 495 static void quirk_s3_64M(struct pci_dev *dev)
 496 {
 497         struct resource *r = &dev->resource[0];
 498 
 499         if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
 500                 r->flags |= IORESOURCE_UNSET;
 501                 r->start = 0;
 502                 r->end = 0x3ffffff;
 503         }
 504 }
 505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_868,           quirk_s3_64M);
 506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_968,           quirk_s3_64M);
 507 
 508 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
 509                      const char *name)
 510 {
 511         u32 region;
 512         struct pci_bus_region bus_region;
 513         struct resource *res = dev->resource + pos;
 514 
 515         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
 516 
 517         if (!region)
 518                 return;
 519 
 520         res->name = pci_name(dev);
 521         res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
 522         res->flags |=
 523                 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
 524         region &= ~(size - 1);
 525 
 526         /* Convert from PCI bus to resource space */
 527         bus_region.start = region;
 528         bus_region.end = region + size - 1;
 529         pcibios_bus_to_resource(dev->bus, res, &bus_region);
 530 
 531         pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
 532                  name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
 533 }
 534 
 535 /*
 536  * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
 537  * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
 538  * BAR0 should be 8 bytes; instead, it may be set to something like 8k
 539  * (which conflicts w/ BAR1's memory range).
 540  *
 541  * CS553x's ISA PCI BARs may also be read-only (ref:
 542  * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
 543  */
 544 static void quirk_cs5536_vsa(struct pci_dev *dev)
 545 {
 546         static char *name = "CS5536 ISA bridge";
 547 
 548         if (pci_resource_len(dev, 0) != 8) {
 549                 quirk_io(dev, 0,   8, name);    /* SMB */
 550                 quirk_io(dev, 1, 256, name);    /* GPIO */
 551                 quirk_io(dev, 2,  64, name);    /* MFGPT */
 552                 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
 553                          name);
 554         }
 555 }
 556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
 557 
 558 static void quirk_io_region(struct pci_dev *dev, int port,
 559                                 unsigned size, int nr, const char *name)
 560 {
 561         u16 region;
 562         struct pci_bus_region bus_region;
 563         struct resource *res = dev->resource + nr;
 564 
 565         pci_read_config_word(dev, port, &region);
 566         region &= ~(size - 1);
 567 
 568         if (!region)
 569                 return;
 570 
 571         res->name = pci_name(dev);
 572         res->flags = IORESOURCE_IO;
 573 
 574         /* Convert from PCI bus to resource space */
 575         bus_region.start = region;
 576         bus_region.end = region + size - 1;
 577         pcibios_bus_to_resource(dev->bus, res, &bus_region);
 578 
 579         if (!pci_claim_resource(dev, nr))
 580                 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
 581 }
 582 
 583 /*
 584  * ATI Northbridge setups MCE the processor if you even read somewhere
 585  * between 0x3b0->0x3bb or read 0x3d3
 586  */
 587 static void quirk_ati_exploding_mce(struct pci_dev *dev)
 588 {
 589         pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
 590         /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
 591         request_region(0x3b0, 0x0C, "RadeonIGP");
 592         request_region(0x3d3, 0x01, "RadeonIGP");
 593 }
 594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
 595 
 596 /*
 597  * In the AMD NL platform, this device ([1022:7912]) has a class code of
 598  * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
 599  * claim it.
 600  *
 601  * But the dwc3 driver is a more specific driver for this device, and we'd
 602  * prefer to use it instead of xhci. To prevent xhci from claiming the
 603  * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
 604  * defines as "USB device (not host controller)". The dwc3 driver can then
 605  * claim it based on its Vendor and Device ID.
 606  */
 607 static void quirk_amd_nl_class(struct pci_dev *pdev)
 608 {
 609         u32 class = pdev->class;
 610 
 611         /* Use "USB Device (not host controller)" class */
 612         pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
 613         pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
 614                  class, pdev->class);
 615 }
 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
 617                 quirk_amd_nl_class);
 618 
 619 /*
 620  * Synopsys USB 3.x host HAPS platform has a class code of
 621  * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it.  However, these
 622  * devices should use dwc3-haps driver.  Change these devices' class code to
 623  * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
 624  * them.
 625  */
 626 static void quirk_synopsys_haps(struct pci_dev *pdev)
 627 {
 628         u32 class = pdev->class;
 629 
 630         switch (pdev->device) {
 631         case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
 632         case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
 633         case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
 634                 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
 635                 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
 636                          class, pdev->class);
 637                 break;
 638         }
 639 }
 640 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
 641                                PCI_CLASS_SERIAL_USB_XHCI, 0,
 642                                quirk_synopsys_haps);
 643 
 644 /*
 645  * Let's make the southbridge information explicit instead of having to
 646  * worry about people probing the ACPI areas, for example.. (Yes, it
 647  * happens, and if you read the wrong ACPI register it will put the machine
 648  * to sleep with no way of waking it up again. Bummer).
 649  *
 650  * ALI M7101: Two IO regions pointed to by words at
 651  *      0xE0 (64 bytes of ACPI registers)
 652  *      0xE2 (32 bytes of SMB registers)
 653  */
 654 static void quirk_ali7101_acpi(struct pci_dev *dev)
 655 {
 656         quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
 657         quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
 658 }
 659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,      PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi);
 660 
 661 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 662 {
 663         u32 devres;
 664         u32 mask, size, base;
 665 
 666         pci_read_config_dword(dev, port, &devres);
 667         if ((devres & enable) != enable)
 668                 return;
 669         mask = (devres >> 16) & 15;
 670         base = devres & 0xffff;
 671         size = 16;
 672         for (;;) {
 673                 unsigned bit = size >> 1;
 674                 if ((bit & mask) == bit)
 675                         break;
 676                 size = bit;
 677         }
 678         /*
 679          * For now we only print it out. Eventually we'll want to
 680          * reserve it (at least if it's in the 0x1000+ range), but
 681          * let's get enough confirmation reports first.
 682          */
 683         base &= -size;
 684         pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
 685 }
 686 
 687 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 688 {
 689         u32 devres;
 690         u32 mask, size, base;
 691 
 692         pci_read_config_dword(dev, port, &devres);
 693         if ((devres & enable) != enable)
 694                 return;
 695         base = devres & 0xffff0000;
 696         mask = (devres & 0x3f) << 16;
 697         size = 128 << 16;
 698         for (;;) {
 699                 unsigned bit = size >> 1;
 700                 if ((bit & mask) == bit)
 701                         break;
 702                 size = bit;
 703         }
 704 
 705         /*
 706          * For now we only print it out. Eventually we'll want to
 707          * reserve it, but let's get enough confirmation reports first.
 708          */
 709         base &= -size;
 710         pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
 711 }
 712 
 713 /*
 714  * PIIX4 ACPI: Two IO regions pointed to by longwords at
 715  *      0x40 (64 bytes of ACPI registers)
 716  *      0x90 (16 bytes of SMB registers)
 717  * and a few strange programmable PIIX4 device resources.
 718  */
 719 static void quirk_piix4_acpi(struct pci_dev *dev)
 720 {
 721         u32 res_a;
 722 
 723         quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
 724         quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
 725 
 726         /* Device resource A has enables for some of the other ones */
 727         pci_read_config_dword(dev, 0x5c, &res_a);
 728 
 729         piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
 730         piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
 731 
 732         /* Device resource D is just bitfields for static resources */
 733 
 734         /* Device 12 enabled? */
 735         if (res_a & (1 << 29)) {
 736                 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
 737                 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
 738         }
 739         /* Device 13 enabled? */
 740         if (res_a & (1 << 30)) {
 741                 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
 742                 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
 743         }
 744         piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
 745         piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
 746 }
 747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi);
 748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82443MX_3,  quirk_piix4_acpi);
 749 
 750 #define ICH_PMBASE      0x40
 751 #define ICH_ACPI_CNTL   0x44
 752 #define  ICH4_ACPI_EN   0x10
 753 #define  ICH6_ACPI_EN   0x80
 754 #define ICH4_GPIOBASE   0x58
 755 #define ICH4_GPIO_CNTL  0x5c
 756 #define  ICH4_GPIO_EN   0x10
 757 #define ICH6_GPIOBASE   0x48
 758 #define ICH6_GPIO_CNTL  0x4c
 759 #define  ICH6_GPIO_EN   0x10
 760 
 761 /*
 762  * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 763  *      0x40 (128 bytes of ACPI, GPIO & TCO registers)
 764  *      0x58 (64 bytes of GPIO I/O space)
 765  */
 766 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
 767 {
 768         u8 enable;
 769 
 770         /*
 771          * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
 772          * with low legacy (and fixed) ports. We don't know the decoding
 773          * priority and can't tell whether the legacy device or the one created
 774          * here is really at that address.  This happens on boards with broken
 775          * BIOSes.
 776          */
 777         pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
 778         if (enable & ICH4_ACPI_EN)
 779                 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
 780                                  "ICH4 ACPI/GPIO/TCO");
 781 
 782         pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
 783         if (enable & ICH4_GPIO_EN)
 784                 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
 785                                 "ICH4 GPIO");
 786 }
 787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,         quirk_ich4_lpc_acpi);
 788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,         quirk_ich4_lpc_acpi);
 789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,         quirk_ich4_lpc_acpi);
 790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,        quirk_ich4_lpc_acpi);
 791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,         quirk_ich4_lpc_acpi);
 792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,        quirk_ich4_lpc_acpi);
 793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,         quirk_ich4_lpc_acpi);
 794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,        quirk_ich4_lpc_acpi);
 795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,         quirk_ich4_lpc_acpi);
 796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,             quirk_ich4_lpc_acpi);
 797 
 798 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
 799 {
 800         u8 enable;
 801 
 802         pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
 803         if (enable & ICH6_ACPI_EN)
 804                 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
 805                                  "ICH6 ACPI/GPIO/TCO");
 806 
 807         pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
 808         if (enable & ICH6_GPIO_EN)
 809                 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
 810                                 "ICH6 GPIO");
 811 }
 812 
 813 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
 814                                     const char *name, int dynsize)
 815 {
 816         u32 val;
 817         u32 size, base;
 818 
 819         pci_read_config_dword(dev, reg, &val);
 820 
 821         /* Enabled? */
 822         if (!(val & 1))
 823                 return;
 824         base = val & 0xfffc;
 825         if (dynsize) {
 826                 /*
 827                  * This is not correct. It is 16, 32 or 64 bytes depending on
 828                  * register D31:F0:ADh bits 5:4.
 829                  *
 830                  * But this gets us at least _part_ of it.
 831                  */
 832                 size = 16;
 833         } else {
 834                 size = 128;
 835         }
 836         base &= ~(size-1);
 837 
 838         /*
 839          * Just print it out for now. We should reserve it after more
 840          * debugging.
 841          */
 842         pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
 843 }
 844 
 845 static void quirk_ich6_lpc(struct pci_dev *dev)
 846 {
 847         /* Shared ACPI/GPIO decode with all ICH6+ */
 848         ich6_lpc_acpi_gpio(dev);
 849 
 850         /* ICH6-specific generic IO decode */
 851         ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
 852         ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
 853 }
 854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
 855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
 856 
 857 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
 858                                     const char *name)
 859 {
 860         u32 val;
 861         u32 mask, base;
 862 
 863         pci_read_config_dword(dev, reg, &val);
 864 
 865         /* Enabled? */
 866         if (!(val & 1))
 867                 return;
 868 
 869         /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
 870         base = val & 0xfffc;
 871         mask = (val >> 16) & 0xfc;
 872         mask |= 3;
 873 
 874         /*
 875          * Just print it out for now. We should reserve it after more
 876          * debugging.
 877          */
 878         pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
 879 }
 880 
 881 /* ICH7-10 has the same common LPC generic IO decode registers */
 882 static void quirk_ich7_lpc(struct pci_dev *dev)
 883 {
 884         /* We share the common ACPI/GPIO decode with ICH6 */
 885         ich6_lpc_acpi_gpio(dev);
 886 
 887         /* And have 4 ICH7+ generic decodes */
 888         ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
 889         ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
 890         ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
 891         ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
 892 }
 893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
 906 
 907 /*
 908  * VIA ACPI: One IO region pointed to by longword at
 909  *      0x48 or 0x20 (256 bytes of ACPI registers)
 910  */
 911 static void quirk_vt82c586_acpi(struct pci_dev *dev)
 912 {
 913         if (dev->revision & 0x10)
 914                 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
 915                                 "vt82c586 ACPI");
 916 }
 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi);
 918 
 919 /*
 920  * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 921  *      0x48 (256 bytes of ACPI registers)
 922  *      0x70 (128 bytes of hardware monitoring register)
 923  *      0x90 (16 bytes of SMB registers)
 924  */
 925 static void quirk_vt82c686_acpi(struct pci_dev *dev)
 926 {
 927         quirk_vt82c586_acpi(dev);
 928 
 929         quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
 930                                  "vt82c686 HW-mon");
 931 
 932         quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
 933 }
 934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi);
 935 
 936 /*
 937  * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 938  *      0x88 (128 bytes of power management registers)
 939  *      0xd0 (16 bytes of SMB registers)
 940  */
 941 static void quirk_vt8235_acpi(struct pci_dev *dev)
 942 {
 943         quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
 944         quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
 945 }
 946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
 947 
 948 /*
 949  * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
 950  * back-to-back: Disable fast back-to-back on the secondary bus segment
 951  */
 952 static void quirk_xio2000a(struct pci_dev *dev)
 953 {
 954         struct pci_dev *pdev;
 955         u16 command;
 956 
 957         pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
 958         list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
 959                 pci_read_config_word(pdev, PCI_COMMAND, &command);
 960                 if (command & PCI_COMMAND_FAST_BACK)
 961                         pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
 962         }
 963 }
 964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
 965                         quirk_xio2000a);
 966 
 967 #ifdef CONFIG_X86_IO_APIC
 968 
 969 #include <asm/io_apic.h>
 970 
 971 /*
 972  * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 973  * devices to the external APIC.
 974  *
 975  * TODO: When we have device-specific interrupt routers, this code will go
 976  * away from quirks.
 977  */
 978 static void quirk_via_ioapic(struct pci_dev *dev)
 979 {
 980         u8 tmp;
 981 
 982         if (nr_ioapics < 1)
 983                 tmp = 0;    /* nothing routed to external APIC */
 984         else
 985                 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
 986 
 987         pci_info(dev, "%sbling VIA external APIC routing\n",
 988                tmp == 0 ? "Disa" : "Ena");
 989 
 990         /* Offset 0x58: External APIC IRQ output control */
 991         pci_write_config_byte(dev, 0x58, tmp);
 992 }
 993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 994 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 995 
 996 /*
 997  * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
 998  * This leads to doubled level interrupt rates.
 999  * Set this bit to get rid of cycle wastage.
1000  * Otherwise uncritical.
1001  */
1002 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1003 {
1004         u8 misc_control2;
1005 #define BYPASS_APIC_DEASSERT 8
1006 
1007         pci_read_config_byte(dev, 0x5B, &misc_control2);
1008         if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1009                 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1010                 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1011         }
1012 }
1013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
1014 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
1015 
1016 /*
1017  * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1018  * We check all revs >= B0 (yet not in the pre production!) as the bug
1019  * is currently marked NoFix
1020  *
1021  * We have multiple reports of hangs with this chipset that went away with
1022  * noapic specified. For the moment we assume it's the erratum. We may be wrong
1023  * of course. However the advice is demonstrably good even if so.
1024  */
1025 static void quirk_amd_ioapic(struct pci_dev *dev)
1026 {
1027         if (dev->revision >= 0x02) {
1028                 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1029                 pci_warn(dev, "        : booting with the \"noapic\" option\n");
1030         }
1031 }
1032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
1033 #endif /* CONFIG_X86_IO_APIC */
1034 
1035 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1036 
1037 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1038 {
1039         /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1040         if (dev->subsystem_device == 0xa118)
1041                 dev->sriov->link = dev->devfn;
1042 }
1043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1044 #endif
1045 
1046 /*
1047  * Some settings of MMRBC can lead to data corruption so block changes.
1048  * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1049  */
1050 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1051 {
1052         if (dev->subordinate && dev->revision <= 0x12) {
1053                 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1054                          dev->revision);
1055                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1056         }
1057 }
1058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1059 
1060 /*
1061  * FIXME: it is questionable that quirk_via_acpi() is needed.  It shows up
1062  * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1063  * at all.  Therefore it seems like setting the pci_dev's IRQ to the value
1064  * of the ACPI SCI interrupt is only done for convenience.
1065  *      -jgarzik
1066  */
1067 static void quirk_via_acpi(struct pci_dev *d)
1068 {
1069         u8 irq;
1070 
1071         /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1072         pci_read_config_byte(d, 0x42, &irq);
1073         irq &= 0xf;
1074         if (irq && (irq != 2))
1075                 d->irq = irq;
1076 }
1077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_via_acpi);
1078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_via_acpi);
1079 
1080 /* VIA bridges which have VLink */
1081 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1082 
1083 static void quirk_via_bridge(struct pci_dev *dev)
1084 {
1085         /* See what bridge we have and find the device ranges */
1086         switch (dev->device) {
1087         case PCI_DEVICE_ID_VIA_82C686:
1088                 /*
1089                  * The VT82C686 is special; it attaches to PCI and can have
1090                  * any device number. All its subdevices are functions of
1091                  * that single device.
1092                  */
1093                 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1094                 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1095                 break;
1096         case PCI_DEVICE_ID_VIA_8237:
1097         case PCI_DEVICE_ID_VIA_8237A:
1098                 via_vlink_dev_lo = 15;
1099                 break;
1100         case PCI_DEVICE_ID_VIA_8235:
1101                 via_vlink_dev_lo = 16;
1102                 break;
1103         case PCI_DEVICE_ID_VIA_8231:
1104         case PCI_DEVICE_ID_VIA_8233_0:
1105         case PCI_DEVICE_ID_VIA_8233A:
1106         case PCI_DEVICE_ID_VIA_8233C_0:
1107                 via_vlink_dev_lo = 17;
1108                 break;
1109         }
1110 }
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686,       quirk_via_bridge);
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8231,         quirk_via_bridge);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233_0,       quirk_via_bridge);
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233A,        quirk_via_bridge);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233C_0,      quirk_via_bridge);
1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235,         quirk_via_bridge);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237,         quirk_via_bridge);
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237A,        quirk_via_bridge);
1119 
1120 /*
1121  * quirk_via_vlink              -       VIA VLink IRQ number update
1122  * @dev: PCI device
1123  *
1124  * If the device we are dealing with is on a PIC IRQ we need to ensure that
1125  * the IRQ line register which usually is not relevant for PCI cards, is
1126  * actually written so that interrupts get sent to the right place.
1127  *
1128  * We only do this on systems where a VIA south bridge was detected, and
1129  * only for VIA devices on the motherboard (see quirk_via_bridge above).
1130  */
1131 static void quirk_via_vlink(struct pci_dev *dev)
1132 {
1133         u8 irq, new_irq;
1134 
1135         /* Check if we have VLink at all */
1136         if (via_vlink_dev_lo == -1)
1137                 return;
1138 
1139         new_irq = dev->irq;
1140 
1141         /* Don't quirk interrupts outside the legacy IRQ range */
1142         if (!new_irq || new_irq > 15)
1143                 return;
1144 
1145         /* Internal device ? */
1146         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1147             PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1148                 return;
1149 
1150         /*
1151          * This is an internal VLink device on a PIC interrupt. The BIOS
1152          * ought to have set this but may not have, so we redo it.
1153          */
1154         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1155         if (new_irq != irq) {
1156                 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1157                         irq, new_irq);
1158                 udelay(15);     /* unknown if delay really needed */
1159                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1160         }
1161 }
1162 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1163 
1164 /*
1165  * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1166  * of VT82C597 for backward compatibility.  We need to switch it off to be
1167  * able to recognize the real type of the chip.
1168  */
1169 static void quirk_vt82c598_id(struct pci_dev *dev)
1170 {
1171         pci_write_config_byte(dev, 0xfc, 0);
1172         pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1173 }
1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C597_0,     quirk_vt82c598_id);
1175 
1176 /*
1177  * CardBus controllers have a legacy base address that enables them to
1178  * respond as i82365 pcmcia controllers.  We don't want them to do this
1179  * even if the Linux CardBus driver is not loaded, because the Linux i82365
1180  * driver does not (and should not) handle CardBus.
1181  */
1182 static void quirk_cardbus_legacy(struct pci_dev *dev)
1183 {
1184         pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1185 }
1186 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1187                         PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1188 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1189                         PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1190 
1191 /*
1192  * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1193  * what the designers were smoking but let's not inhale...
1194  *
1195  * To be fair to AMD, it follows the spec by default, it's BIOS people who
1196  * turn it off!
1197  */
1198 static void quirk_amd_ordering(struct pci_dev *dev)
1199 {
1200         u32 pcic;
1201         pci_read_config_dword(dev, 0x4C, &pcic);
1202         if ((pcic & 6) != 6) {
1203                 pcic |= 6;
1204                 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1205                 pci_write_config_dword(dev, 0x4C, pcic);
1206                 pci_read_config_dword(dev, 0x84, &pcic);
1207                 pcic |= (1 << 23);      /* Required in this mode */
1208                 pci_write_config_dword(dev, 0x84, pcic);
1209         }
1210 }
1211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,       PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1213 
1214 /*
1215  * DreamWorks-provided workaround for Dunord I-3000 problem
1216  *
1217  * This card decodes and responds to addresses not apparently assigned to
1218  * it.  We force a larger allocation to ensure that nothing gets put too
1219  * close to it.
1220  */
1221 static void quirk_dunord(struct pci_dev *dev)
1222 {
1223         struct resource *r = &dev->resource[1];
1224 
1225         r->flags |= IORESOURCE_UNSET;
1226         r->start = 0;
1227         r->end = 0xffffff;
1228 }
1229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,  PCI_DEVICE_ID_DUNORD_I3000,     quirk_dunord);
1230 
1231 /*
1232  * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1233  * decoding (transparent), and does indicate this in the ProgIf.
1234  * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1235  */
1236 static void quirk_transparent_bridge(struct pci_dev *dev)
1237 {
1238         dev->transparent = 1;
1239 }
1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82380FB,    quirk_transparent_bridge);
1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605,  quirk_transparent_bridge);
1242 
1243 /*
1244  * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1245  * PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1 datasheets
1246  * found at http://www.national.com/analog for info on what these bits do.
1247  * <christer@weinigel.se>
1248  */
1249 static void quirk_mediagx_master(struct pci_dev *dev)
1250 {
1251         u8 reg;
1252 
1253         pci_read_config_byte(dev, 0x41, &reg);
1254         if (reg & 2) {
1255                 reg &= ~2;
1256                 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1257                          reg);
1258                 pci_write_config_byte(dev, 0x41, reg);
1259         }
1260 }
1261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,    PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,   PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1263 
1264 /*
1265  * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1266  * in the odd case it is not the results are corruption hence the presence
1267  * of a Linux check.
1268  */
1269 static void quirk_disable_pxb(struct pci_dev *pdev)
1270 {
1271         u16 config;
1272 
1273         if (pdev->revision != 0x04)             /* Only C0 requires this */
1274                 return;
1275         pci_read_config_word(pdev, 0x40, &config);
1276         if (config & (1<<6)) {
1277                 config &= ~(1<<6);
1278                 pci_write_config_word(pdev, 0x40, config);
1279                 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1280         }
1281 }
1282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
1283 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
1284 
1285 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1286 {
1287         /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1288         u8 tmp;
1289 
1290         pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1291         if (tmp == 0x01) {
1292                 pci_read_config_byte(pdev, 0x40, &tmp);
1293                 pci_write_config_byte(pdev, 0x40, tmp|1);
1294                 pci_write_config_byte(pdev, 0x9, 1);
1295                 pci_write_config_byte(pdev, 0xa, 6);
1296                 pci_write_config_byte(pdev, 0x40, tmp);
1297 
1298                 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1299                 pci_info(pdev, "set SATA to AHCI mode\n");
1300         }
1301 }
1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1310 
1311 /* Serverworks CSB5 IDE does not fully support native mode */
1312 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1313 {
1314         u8 prog;
1315         pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1316         if (prog & 5) {
1317                 prog &= ~5;
1318                 pdev->class &= ~5;
1319                 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1320                 /* PCI layer will sort out resources */
1321         }
1322 }
1323 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1324 
1325 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1326 static void quirk_ide_samemode(struct pci_dev *pdev)
1327 {
1328         u8 prog;
1329 
1330         pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1331 
1332         if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1333                 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1334                 prog &= ~5;
1335                 pdev->class &= ~5;
1336                 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1337         }
1338 }
1339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1340 
1341 /* Some ATA devices break if put into D3 */
1342 static void quirk_no_ata_d3(struct pci_dev *pdev)
1343 {
1344         pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1345 }
1346 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1347 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1348                                 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1349 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1350                                 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1351 /* ALi loses some register settings that we cannot then restore */
1352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1353                                 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1355    occur when mode detecting */
1356 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1357                                 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1358 
1359 /*
1360  * This was originally an Alpha-specific thing, but it really fits here.
1361  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1362  */
1363 static void quirk_eisa_bridge(struct pci_dev *dev)
1364 {
1365         dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1366 }
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82375,      quirk_eisa_bridge);
1368 
1369 /*
1370  * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1371  * is not activated. The myth is that Asus said that they do not want the
1372  * users to be irritated by just another PCI Device in the Win98 device
1373  * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1374  * package 2.7.0 for details)
1375  *
1376  * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1377  * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1378  * becomes necessary to do this tweak in two steps -- the chosen trigger
1379  * is either the Host bridge (preferred) or on-board VGA controller.
1380  *
1381  * Note that we used to unhide the SMBus that way on Toshiba laptops
1382  * (Satellite A40 and Tecra M2) but then found that the thermal management
1383  * was done by SMM code, which could cause unsynchronized concurrent
1384  * accesses to the SMBus registers, with potentially bad effects. Thus you
1385  * should be very careful when adding new entries: if SMM is accessing the
1386  * Intel SMBus, this is a very good reason to leave it hidden.
1387  *
1388  * Likewise, many recent laptops use ACPI for thermal management. If the
1389  * ACPI DSDT code accesses the SMBus, then Linux should not access it
1390  * natively, and keeping the SMBus hidden is the right thing to do. If you
1391  * are about to add an entry in the table below, please first disassemble
1392  * the DSDT and double-check that there is no code accessing the SMBus.
1393  */
1394 static int asus_hides_smbus;
1395 
1396 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1397 {
1398         if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1399                 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1400                         switch (dev->subsystem_device) {
1401                         case 0x8025: /* P4B-LX */
1402                         case 0x8070: /* P4B */
1403                         case 0x8088: /* P4B533 */
1404                         case 0x1626: /* L3C notebook */
1405                                 asus_hides_smbus = 1;
1406                         }
1407                 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1408                         switch (dev->subsystem_device) {
1409                         case 0x80b1: /* P4GE-V */
1410                         case 0x80b2: /* P4PE */
1411                         case 0x8093: /* P4B533-V */
1412                                 asus_hides_smbus = 1;
1413                         }
1414                 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1415                         switch (dev->subsystem_device) {
1416                         case 0x8030: /* P4T533 */
1417                                 asus_hides_smbus = 1;
1418                         }
1419                 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1420                         switch (dev->subsystem_device) {
1421                         case 0x8070: /* P4G8X Deluxe */
1422                                 asus_hides_smbus = 1;
1423                         }
1424                 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1425                         switch (dev->subsystem_device) {
1426                         case 0x80c9: /* PU-DLS */
1427                                 asus_hides_smbus = 1;
1428                         }
1429                 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1430                         switch (dev->subsystem_device) {
1431                         case 0x1751: /* M2N notebook */
1432                         case 0x1821: /* M5N notebook */
1433                         case 0x1897: /* A6L notebook */
1434                                 asus_hides_smbus = 1;
1435                         }
1436                 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1437                         switch (dev->subsystem_device) {
1438                         case 0x184b: /* W1N notebook */
1439                         case 0x186a: /* M6Ne notebook */
1440                                 asus_hides_smbus = 1;
1441                         }
1442                 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1443                         switch (dev->subsystem_device) {
1444                         case 0x80f2: /* P4P800-X */
1445                                 asus_hides_smbus = 1;
1446                         }
1447                 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1448                         switch (dev->subsystem_device) {
1449                         case 0x1882: /* M6V notebook */
1450                         case 0x1977: /* A6VA notebook */
1451                                 asus_hides_smbus = 1;
1452                         }
1453         } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1454                 if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1455                         switch (dev->subsystem_device) {
1456                         case 0x088C: /* HP Compaq nc8000 */
1457                         case 0x0890: /* HP Compaq nc6000 */
1458                                 asus_hides_smbus = 1;
1459                         }
1460                 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1461                         switch (dev->subsystem_device) {
1462                         case 0x12bc: /* HP D330L */
1463                         case 0x12bd: /* HP D530 */
1464                         case 0x006a: /* HP Compaq nx9500 */
1465                                 asus_hides_smbus = 1;
1466                         }
1467                 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1468                         switch (dev->subsystem_device) {
1469                         case 0x12bf: /* HP xw4100 */
1470                                 asus_hides_smbus = 1;
1471                         }
1472         } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1473                 if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1474                         switch (dev->subsystem_device) {
1475                         case 0xC00C: /* Samsung P35 notebook */
1476                                 asus_hides_smbus = 1;
1477                 }
1478         } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1479                 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1480                         switch (dev->subsystem_device) {
1481                         case 0x0058: /* Compaq Evo N620c */
1482                                 asus_hides_smbus = 1;
1483                         }
1484                 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1485                         switch (dev->subsystem_device) {
1486                         case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1487                                 /* Motherboard doesn't have Host bridge
1488                                  * subvendor/subdevice IDs, therefore checking
1489                                  * its on-board VGA controller */
1490                                 asus_hides_smbus = 1;
1491                         }
1492                 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1493                         switch (dev->subsystem_device) {
1494                         case 0x00b8: /* Compaq Evo D510 CMT */
1495                         case 0x00b9: /* Compaq Evo D510 SFF */
1496                         case 0x00ba: /* Compaq Evo D510 USDT */
1497                                 /* Motherboard doesn't have Host bridge
1498                                  * subvendor/subdevice IDs and on-board VGA
1499                                  * controller is disabled if an AGP card is
1500                                  * inserted, therefore checking USB UHCI
1501                                  * Controller #1 */
1502                                 asus_hides_smbus = 1;
1503                         }
1504                 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1505                         switch (dev->subsystem_device) {
1506                         case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1507                                 /* Motherboard doesn't have host bridge
1508                                  * subvendor/subdevice IDs, therefore checking
1509                                  * its on-board VGA controller */
1510                                 asus_hides_smbus = 1;
1511                         }
1512         }
1513 }
1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845_HB,   asus_hides_smbus_hostbridge);
1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845G_HB,  asus_hides_smbus_hostbridge);
1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82850_HB,   asus_hides_smbus_hostbridge);
1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82865_HB,   asus_hides_smbus_hostbridge);
1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82875_HB,   asus_hides_smbus_hostbridge);
1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_7205_0,     asus_hides_smbus_hostbridge);
1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_E7501_MCH,  asus_hides_smbus_hostbridge);
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1524 
1525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82810_IG3,  asus_hides_smbus_hostbridge);
1526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_2,  asus_hides_smbus_hostbridge);
1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82815_CGC,  asus_hides_smbus_hostbridge);
1528 
1529 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1530 {
1531         u16 val;
1532 
1533         if (likely(!asus_hides_smbus))
1534                 return;
1535 
1536         pci_read_config_word(dev, 0xF2, &val);
1537         if (val & 0x8) {
1538                 pci_write_config_word(dev, 0xF2, val & (~0x8));
1539                 pci_read_config_word(dev, 0xF2, &val);
1540                 if (val & 0x8)
1541                         pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1542                                  val);
1543                 else
1544                         pci_info(dev, "Enabled i801 SMBus device\n");
1545         }
1546 }
1547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1557 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1559 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1560 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1561 
1562 /* It appears we just have one such device. If not, we have a warning */
1563 static void __iomem *asus_rcba_base;
1564 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1565 {
1566         u32 rcba;
1567 
1568         if (likely(!asus_hides_smbus))
1569                 return;
1570         WARN_ON(asus_rcba_base);
1571 
1572         pci_read_config_dword(dev, 0xF0, &rcba);
1573         /* use bits 31:14, 16 kB aligned */
1574         asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1575         if (asus_rcba_base == NULL)
1576                 return;
1577 }
1578 
1579 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1580 {
1581         u32 val;
1582 
1583         if (likely(!asus_hides_smbus || !asus_rcba_base))
1584                 return;
1585 
1586         /* read the Function Disable register, dword mode only */
1587         val = readl(asus_rcba_base + 0x3418);
1588 
1589         /* enable the SMBus device */
1590         writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1591 }
1592 
1593 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1594 {
1595         if (likely(!asus_hides_smbus || !asus_rcba_base))
1596                 return;
1597 
1598         iounmap(asus_rcba_base);
1599         asus_rcba_base = NULL;
1600         pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1601 }
1602 
1603 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1604 {
1605         asus_hides_smbus_lpc_ich6_suspend(dev);
1606         asus_hides_smbus_lpc_ich6_resume_early(dev);
1607         asus_hides_smbus_lpc_ich6_resume(dev);
1608 }
1609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6);
1610 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_suspend);
1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume);
1612 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume_early);
1613 
1614 /* SiS 96x south bridge: BIOS typically hides SMBus device...  */
1615 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1616 {
1617         u8 val = 0;
1618         pci_read_config_byte(dev, 0x77, &val);
1619         if (val & 0x10) {
1620                 pci_info(dev, "Enabling SiS 96x SMBus\n");
1621                 pci_write_config_byte(dev, 0x77, val & ~0x10);
1622         }
1623 }
1624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1628 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1629 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1630 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1631 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1632 
1633 /*
1634  * ... This is further complicated by the fact that some SiS96x south
1635  * bridges pretend to be 85C503/5513 instead.  In that case see if we
1636  * spotted a compatible north bridge to make sure.
1637  * (pci_find_device() doesn't work yet)
1638  *
1639  * We can also enable the sis96x bit in the discovery register..
1640  */
1641 #define SIS_DETECT_REGISTER 0x40
1642 
1643 static void quirk_sis_503(struct pci_dev *dev)
1644 {
1645         u8 reg;
1646         u16 devid;
1647 
1648         pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1649         pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1650         pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1651         if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1652                 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1653                 return;
1654         }
1655 
1656         /*
1657          * Ok, it now shows up as a 96x.  Run the 96x quirk by hand in case
1658          * it has already been processed.  (Depends on link order, which is
1659          * apparently not guaranteed)
1660          */
1661         dev->device = devid;
1662         quirk_sis_96x_smbus(dev);
1663 }
1664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1665 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1666 
1667 /*
1668  * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1669  * and MC97 modem controller are disabled when a second PCI soundcard is
1670  * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1671  * -- bjd
1672  */
1673 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1674 {
1675         u8 val;
1676         int asus_hides_ac97 = 0;
1677 
1678         if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1679                 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1680                         asus_hides_ac97 = 1;
1681         }
1682 
1683         if (!asus_hides_ac97)
1684                 return;
1685 
1686         pci_read_config_byte(dev, 0x50, &val);
1687         if (val & 0xc0) {
1688                 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1689                 pci_read_config_byte(dev, 0x50, &val);
1690                 if (val & 0xc0)
1691                         pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1692                                  val);
1693                 else
1694                         pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1695         }
1696 }
1697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1699 
1700 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1701 
1702 /*
1703  * If we are using libata we can drive this chip properly but must do this
1704  * early on to make the additional device appear during the PCI scanning.
1705  */
1706 static void quirk_jmicron_ata(struct pci_dev *pdev)
1707 {
1708         u32 conf1, conf5, class;
1709         u8 hdr;
1710 
1711         /* Only poke fn 0 */
1712         if (PCI_FUNC(pdev->devfn))
1713                 return;
1714 
1715         pci_read_config_dword(pdev, 0x40, &conf1);
1716         pci_read_config_dword(pdev, 0x80, &conf5);
1717 
1718         conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1719         conf5 &= ~(1 << 24);  /* Clear bit 24 */
1720 
1721         switch (pdev->device) {
1722         case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1723         case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1724         case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1725                 /* The controller should be in single function ahci mode */
1726                 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1727                 break;
1728 
1729         case PCI_DEVICE_ID_JMICRON_JMB365:
1730         case PCI_DEVICE_ID_JMICRON_JMB366:
1731                 /* Redirect IDE second PATA port to the right spot */
1732                 conf5 |= (1 << 24);
1733                 /* Fall through */
1734         case PCI_DEVICE_ID_JMICRON_JMB361:
1735         case PCI_DEVICE_ID_JMICRON_JMB363:
1736         case PCI_DEVICE_ID_JMICRON_JMB369:
1737                 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1738                 /* Set the class codes correctly and then direct IDE 0 */
1739                 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1740                 break;
1741 
1742         case PCI_DEVICE_ID_JMICRON_JMB368:
1743                 /* The controller should be in single function IDE mode */
1744                 conf1 |= 0x00C00000; /* Set 22, 23 */
1745                 break;
1746         }
1747 
1748         pci_write_config_dword(pdev, 0x40, conf1);
1749         pci_write_config_dword(pdev, 0x80, conf5);
1750 
1751         /* Update pdev accordingly */
1752         pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1753         pdev->hdr_type = hdr & 0x7f;
1754         pdev->multifunction = !!(hdr & 0x80);
1755 
1756         pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1757         pdev->class = class >> 8;
1758 }
1759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1764 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1773 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1774 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1776 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1777 
1778 #endif
1779 
1780 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1781 {
1782         if (dev->multifunction) {
1783                 device_disable_async_suspend(&dev->dev);
1784                 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1785         }
1786 }
1787 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1788 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1791 
1792 #ifdef CONFIG_X86_IO_APIC
1793 static void quirk_alder_ioapic(struct pci_dev *pdev)
1794 {
1795         int i;
1796 
1797         if ((pdev->class >> 8) != 0xff00)
1798                 return;
1799 
1800         /*
1801          * The first BAR is the location of the IO-APIC... we must
1802          * not touch this (and it's already covered by the fixmap), so
1803          * forcibly insert it into the resource tree.
1804          */
1805         if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1806                 insert_resource(&iomem_resource, &pdev->resource[0]);
1807 
1808         /*
1809          * The next five BARs all seem to be rubbish, so just clean
1810          * them out.
1811          */
1812         for (i = 1; i < 6; i++)
1813                 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1814 }
1815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_EESSC,      quirk_alder_ioapic);
1816 #endif
1817 
1818 static void quirk_pcie_mch(struct pci_dev *pdev)
1819 {
1820         pdev->no_msi = 1;
1821 }
1822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7520_MCH,  quirk_pcie_mch);
1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
1825 
1826 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1827 
1828 /*
1829  * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1830  * together on certain PXH-based systems.
1831  */
1832 static void quirk_pcie_pxh(struct pci_dev *dev)
1833 {
1834         dev->no_msi = 1;
1835         pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1836 }
1837 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_0,     quirk_pcie_pxh);
1838 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_1,     quirk_pcie_pxh);
1839 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_pcie_pxh);
1840 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_pcie_pxh);
1841 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_pcie_pxh);
1842 
1843 /*
1844  * Some Intel PCI Express chipsets have trouble with downstream device
1845  * power management.
1846  */
1847 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1848 {
1849         pci_pm_d3_delay = 120;
1850         dev->no_d1d2 = 1;
1851 }
1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e2, quirk_intel_pcie_pm);
1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e3, quirk_intel_pcie_pm);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e4, quirk_intel_pcie_pm);
1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e5, quirk_intel_pcie_pm);
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e6, quirk_intel_pcie_pm);
1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e7, quirk_intel_pcie_pm);
1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f7, quirk_intel_pcie_pm);
1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f8, quirk_intel_pcie_pm);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f9, quirk_intel_pcie_pm);
1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25fa, quirk_intel_pcie_pm);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2601, quirk_intel_pcie_pm);
1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2602, quirk_intel_pcie_pm);
1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2603, quirk_intel_pcie_pm);
1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2604, quirk_intel_pcie_pm);
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2605, quirk_intel_pcie_pm);
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2606, quirk_intel_pcie_pm);
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2607, quirk_intel_pcie_pm);
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2608, quirk_intel_pcie_pm);
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2609, quirk_intel_pcie_pm);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260a, quirk_intel_pcie_pm);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260b, quirk_intel_pcie_pm);
1873 
1874 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1875 {
1876         if (dev->d3_delay >= delay)
1877                 return;
1878 
1879         dev->d3_delay = delay;
1880         pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1881                  dev->d3_delay);
1882 }
1883 
1884 static void quirk_radeon_pm(struct pci_dev *dev)
1885 {
1886         if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1887             dev->subsystem_device == 0x00e2)
1888                 quirk_d3hot_delay(dev, 20);
1889 }
1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1891 
1892 /*
1893  * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1894  * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1895  *
1896  * The kernel attempts to transition these devices to D3cold, but that seems
1897  * to be ineffective on the platforms in question; the PCI device appears to
1898  * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1899  * extended delay in order to succeed.
1900  */
1901 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1902 {
1903         quirk_d3hot_delay(dev, 20);
1904 }
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1907 
1908 #ifdef CONFIG_X86_IO_APIC
1909 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1910 {
1911         noioapicreroute = 1;
1912         pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1913 
1914         return 0;
1915 }
1916 
1917 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1918         /*
1919          * Systems to exclude from boot interrupt reroute quirks
1920          */
1921         {
1922                 .callback = dmi_disable_ioapicreroute,
1923                 .ident = "ASUSTek Computer INC. M2N-LR",
1924                 .matches = {
1925                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1926                         DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1927                 },
1928         },
1929         {}
1930 };
1931 
1932 /*
1933  * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1934  * remap the original interrupt in the Linux kernel to the boot interrupt, so
1935  * that a PCI device's interrupt handler is installed on the boot interrupt
1936  * line instead.
1937  */
1938 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1939 {
1940         dmi_check_system(boot_interrupt_dmi_table);
1941         if (noioapicquirk || noioapicreroute)
1942                 return;
1943 
1944         dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1945         pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1946                  dev->vendor, dev->device);
1947 }
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
1956 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
1957 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
1958 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
1959 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
1960 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
1961 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
1962 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
1963 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
1964 
1965 /*
1966  * On some chipsets we can disable the generation of legacy INTx boot
1967  * interrupts.
1968  */
1969 
1970 /*
1971  * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1972  * 300641-004US, section 5.7.3.
1973  *
1974  * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1975  * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1976  * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1977  * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1978  * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1979  * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1980  * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1981  * Core IO on Xeon D-1500, see Intel order no 332051-001.
1982  * Core IO on Xeon Scalable, see Intel order no 610950.
1983  */
1984 #define INTEL_6300_IOAPIC_ABAR          0x40    /* Bus 0, Dev 29, Func 5 */
1985 #define INTEL_6300_DISABLE_BOOT_IRQ     (1<<14)
1986 
1987 #define INTEL_CIPINTRC_CFG_OFFSET       0x14C   /* Bus 0, Dev 5, Func 0 */
1988 #define INTEL_CIPINTRC_DIS_INTX_ICH     (1<<25)
1989 
1990 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1991 {
1992         u16 pci_config_word;
1993         u32 pci_config_dword;
1994 
1995         if (noioapicquirk)
1996                 return;
1997 
1998         switch (dev->device) {
1999         case PCI_DEVICE_ID_INTEL_ESB_10:
2000                 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2001                                      &pci_config_word);
2002                 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2003                 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2004                                       pci_config_word);
2005                 break;
2006         case 0x3c28:    /* Xeon E5 1600/2600/4600       */
2007         case 0x0e28:    /* Xeon E5/E7 V2                */
2008         case 0x2f28:    /* Xeon E5/E7 V3,V4             */
2009         case 0x6f28:    /* Xeon D-1500                  */
2010         case 0x2034:    /* Xeon Scalable Family         */
2011                 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2012                                       &pci_config_dword);
2013                 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2014                 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2015                                        pci_config_dword);
2016                 break;
2017         default:
2018                 return;
2019         }
2020         pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2021                  dev->vendor, dev->device);
2022 }
2023 /*
2024  * Device 29 Func 5 Device IDs of IO-APIC
2025  * containing ABAR—APIC1 Alternate Base Address Register
2026  */
2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_10,
2028                 quirk_disable_intel_boot_interrupt);
2029 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,
2030                 quirk_disable_intel_boot_interrupt);
2031 
2032 /*
2033  * Device 5 Func 0 Device IDs of Core IO modules/hubs
2034  * containing Coherent Interface Protocol Interrupt Control
2035  *
2036  * Device IDs obtained from volume 2 datasheets of commented
2037  * families above.
2038  */
2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x3c28,
2040                 quirk_disable_intel_boot_interrupt);
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x0e28,
2042                 quirk_disable_intel_boot_interrupt);
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2f28,
2044                 quirk_disable_intel_boot_interrupt);
2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x6f28,
2046                 quirk_disable_intel_boot_interrupt);
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2034,
2048                 quirk_disable_intel_boot_interrupt);
2049 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   0x3c28,
2050                 quirk_disable_intel_boot_interrupt);
2051 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   0x0e28,
2052                 quirk_disable_intel_boot_interrupt);
2053 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   0x2f28,
2054                 quirk_disable_intel_boot_interrupt);
2055 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   0x6f28,
2056                 quirk_disable_intel_boot_interrupt);
2057 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   0x2034,
2058                 quirk_disable_intel_boot_interrupt);
2059 
2060 /* Disable boot interrupts on HT-1000 */
2061 #define BC_HT1000_FEATURE_REG           0x64
2062 #define BC_HT1000_PIC_REGS_ENABLE       (1<<0)
2063 #define BC_HT1000_MAP_IDX               0xC00
2064 #define BC_HT1000_MAP_DATA              0xC01
2065 
2066 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2067 {
2068         u32 pci_config_dword;
2069         u8 irq;
2070 
2071         if (noioapicquirk)
2072                 return;
2073 
2074         pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2075         pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2076                         BC_HT1000_PIC_REGS_ENABLE);
2077 
2078         for (irq = 0x10; irq < 0x10 + 32; irq++) {
2079                 outb(irq, BC_HT1000_MAP_IDX);
2080                 outb(0x00, BC_HT1000_MAP_DATA);
2081         }
2082 
2083         pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2084 
2085         pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2086                  dev->vendor, dev->device);
2087 }
2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
2089 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,       quirk_disable_broadcom_boot_interrupt);
2090 
2091 /* Disable boot interrupts on AMD and ATI chipsets */
2092 
2093 /*
2094  * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2095  * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2096  * (due to an erratum).
2097  */
2098 #define AMD_813X_MISC                   0x40
2099 #define AMD_813X_NOIOAMODE              (1<<0)
2100 #define AMD_813X_REV_B1                 0x12
2101 #define AMD_813X_REV_B2                 0x13
2102 
2103 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2104 {
2105         u32 pci_config_dword;
2106 
2107         if (noioapicquirk)
2108                 return;
2109         if ((dev->revision == AMD_813X_REV_B1) ||
2110             (dev->revision == AMD_813X_REV_B2))
2111                 return;
2112 
2113         pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2114         pci_config_dword &= ~AMD_813X_NOIOAMODE;
2115         pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2116 
2117         pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2118                  dev->vendor, dev->device);
2119 }
2120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
2121 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
2122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8132_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
2123 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_8132_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
2124 
2125 #define AMD_8111_PCI_IRQ_ROUTING        0x56
2126 
2127 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2128 {
2129         u16 pci_config_word;
2130 
2131         if (noioapicquirk)
2132                 return;
2133 
2134         pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2135         if (!pci_config_word) {
2136                 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2137                          dev->vendor, dev->device);
2138                 return;
2139         }
2140         pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2141         pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2142                  dev->vendor, dev->device);
2143 }
2144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
2145 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,     quirk_disable_amd_8111_boot_interrupt);
2146 #endif /* CONFIG_X86_IO_APIC */
2147 
2148 /*
2149  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2150  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2151  * Re-allocate the region if needed...
2152  */
2153 static void quirk_tc86c001_ide(struct pci_dev *dev)
2154 {
2155         struct resource *r = &dev->resource[0];
2156 
2157         if (r->start & 0x8) {
2158                 r->flags |= IORESOURCE_UNSET;
2159                 r->start = 0;
2160                 r->end = 0xf;
2161         }
2162 }
2163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2164                          PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2165                          quirk_tc86c001_ide);
2166 
2167 /*
2168  * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2169  * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2170  * being read correctly if bit 7 of the base address is set.
2171  * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2172  * Re-allocate the regions to a 256-byte boundary if necessary.
2173  */
2174 static void quirk_plx_pci9050(struct pci_dev *dev)
2175 {
2176         unsigned int bar;
2177 
2178         /* Fixed in revision 2 (PCI 9052). */
2179         if (dev->revision >= 2)
2180                 return;
2181         for (bar = 0; bar <= 1; bar++)
2182                 if (pci_resource_len(dev, bar) == 0x80 &&
2183                     (pci_resource_start(dev, bar) & 0x80)) {
2184                         struct resource *r = &dev->resource[bar];
2185                         pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2186                                  bar);
2187                         r->flags |= IORESOURCE_UNSET;
2188                         r->start = 0;
2189                         r->end = 0xff;
2190                 }
2191 }
2192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2193                          quirk_plx_pci9050);
2194 /*
2195  * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2196  * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2197  * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2198  * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2199  *
2200  * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2201  * driver.
2202  */
2203 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2204 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2205 
2206 static void quirk_netmos(struct pci_dev *dev)
2207 {
2208         unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2209         unsigned int num_serial = dev->subsystem_device & 0xf;
2210 
2211         /*
2212          * These Netmos parts are multiport serial devices with optional
2213          * parallel ports.  Even when parallel ports are present, they
2214          * are identified as class SERIAL, which means the serial driver
2215          * will claim them.  To prevent this, mark them as class OTHER.
2216          * These combo devices should be claimed by parport_serial.
2217          *
2218          * The subdevice ID is of the form 0x00PS, where <P> is the number
2219          * of parallel ports and <S> is the number of serial ports.
2220          */
2221         switch (dev->device) {
2222         case PCI_DEVICE_ID_NETMOS_9835:
2223                 /* Well, this rule doesn't hold for the following 9835 device */
2224                 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2225                                 dev->subsystem_device == 0x0299)
2226                         return;
2227                 /* else, fall through */
2228         case PCI_DEVICE_ID_NETMOS_9735:
2229         case PCI_DEVICE_ID_NETMOS_9745:
2230         case PCI_DEVICE_ID_NETMOS_9845:
2231         case PCI_DEVICE_ID_NETMOS_9855:
2232                 if (num_parallel) {
2233                         pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2234                                 dev->device, num_parallel, num_serial);
2235                         dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2236                             (dev->class & 0xff);
2237                 }
2238         }
2239 }
2240 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2241                          PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2242 
2243 static void quirk_e100_interrupt(struct pci_dev *dev)
2244 {
2245         u16 command, pmcsr;
2246         u8 __iomem *csr;
2247         u8 cmd_hi;
2248 
2249         switch (dev->device) {
2250         /* PCI IDs taken from drivers/net/e100.c */
2251         case 0x1029:
2252         case 0x1030 ... 0x1034:
2253         case 0x1038 ... 0x103E:
2254         case 0x1050 ... 0x1057:
2255         case 0x1059:
2256         case 0x1064 ... 0x106B:
2257         case 0x1091 ... 0x1095:
2258         case 0x1209:
2259         case 0x1229:
2260         case 0x2449:
2261         case 0x2459:
2262         case 0x245D:
2263         case 0x27DC:
2264                 break;
2265         default:
2266                 return;
2267         }
2268 
2269         /*
2270          * Some firmware hands off the e100 with interrupts enabled,
2271          * which can cause a flood of interrupts if packets are
2272          * received before the driver attaches to the device.  So
2273          * disable all e100 interrupts here.  The driver will
2274          * re-enable them when it's ready.
2275          */
2276         pci_read_config_word(dev, PCI_COMMAND, &command);
2277 
2278         if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2279                 return;
2280 
2281         /*
2282          * Check that the device is in the D0 power state. If it's not,
2283          * there is no point to look any further.
2284          */
2285         if (dev->pm_cap) {
2286                 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2287                 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2288                         return;
2289         }
2290 
2291         /* Convert from PCI bus to resource space.  */
2292         csr = ioremap(pci_resource_start(dev, 0), 8);
2293         if (!csr) {
2294                 pci_warn(dev, "Can't map e100 registers\n");
2295                 return;
2296         }
2297 
2298         cmd_hi = readb(csr + 3);
2299         if (cmd_hi == 0) {
2300                 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2301                 writeb(1, csr + 3);
2302         }
2303 
2304         iounmap(csr);
2305 }
2306 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2307                         PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2308 
2309 /*
2310  * The 82575 and 82598 may experience data corruption issues when transitioning
2311  * out of L0S.  To prevent this we need to disable L0S on the PCIe link.
2312  */
2313 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2314 {
2315         pci_info(dev, "Disabling L0s\n");
2316         pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2317 }
2318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2332 
2333 /*
2334  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2335  * Link bit cleared after starting the link retrain process to allow this
2336  * process to finish.
2337  *
2338  * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130.  See also the
2339  * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2340  */
2341 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2342 {
2343         dev->clear_retrain_link = 1;
2344         pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2345 }
2346 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2347 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2348 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2349 
2350 static void fixup_rev1_53c810(struct pci_dev *dev)
2351 {
2352         u32 class = dev->class;
2353 
2354         /*
2355          * rev 1 ncr53c810 chips don't set the class at all which means
2356          * they don't get their resources remapped. Fix that here.
2357          */
2358         if (class)
2359                 return;
2360 
2361         dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2362         pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2363                  class, dev->class);
2364 }
2365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2366 
2367 /* Enable 1k I/O space granularity on the Intel P64H2 */
2368 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2369 {
2370         u16 en1k;
2371 
2372         pci_read_config_word(dev, 0x40, &en1k);
2373 
2374         if (en1k & 0x200) {
2375                 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2376                 dev->io_window_1k = 1;
2377         }
2378 }
2379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2380 
2381 /*
2382  * Under some circumstances, AER is not linked with extended capabilities.
2383  * Force it to be linked by setting the corresponding control bit in the
2384  * config space.
2385  */
2386 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2387 {
2388         uint8_t b;
2389 
2390         if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2391                 if (!(b & 0x20)) {
2392                         pci_write_config_byte(dev, 0xf41, b | 0x20);
2393                         pci_info(dev, "Linking AER extended capability\n");
2394                 }
2395         }
2396 }
2397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2398                         quirk_nvidia_ck804_pcie_aer_ext_cap);
2399 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2400                         quirk_nvidia_ck804_pcie_aer_ext_cap);
2401 
2402 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2403 {
2404         /*
2405          * Disable PCI Bus Parking and PCI Master read caching on CX700
2406          * which causes unspecified timing errors with a VT6212L on the PCI
2407          * bus leading to USB2.0 packet loss.
2408          *
2409          * This quirk is only enabled if a second (on the external PCI bus)
2410          * VT6212L is found -- the CX700 core itself also contains a USB
2411          * host controller with the same PCI ID as the VT6212L.
2412          */
2413 
2414         /* Count VT6212L instances */
2415         struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2416                 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2417         uint8_t b;
2418 
2419         /*
2420          * p should contain the first (internal) VT6212L -- see if we have
2421          * an external one by searching again.
2422          */
2423         p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2424         if (!p)
2425                 return;
2426         pci_dev_put(p);
2427 
2428         if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2429                 if (b & 0x40) {
2430                         /* Turn off PCI Bus Parking */
2431                         pci_write_config_byte(dev, 0x76, b ^ 0x40);
2432 
2433                         pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2434                 }
2435         }
2436 
2437         if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2438                 if (b != 0) {
2439                         /* Turn off PCI Master read caching */
2440                         pci_write_config_byte(dev, 0x72, 0x0);
2441 
2442                         /* Set PCI Master Bus time-out to "1x16 PCLK" */
2443                         pci_write_config_byte(dev, 0x75, 0x1);
2444 
2445                         /* Disable "Read FIFO Timer" */
2446                         pci_write_config_byte(dev, 0x77, 0x0);
2447 
2448                         pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2449                 }
2450         }
2451 }
2452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2453 
2454 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2455 {
2456         u32 rev;
2457 
2458         pci_read_config_dword(dev, 0xf4, &rev);
2459 
2460         /* Only CAP the MRRS if the device is a 5719 A0 */
2461         if (rev == 0x05719000) {
2462                 int readrq = pcie_get_readrq(dev);
2463                 if (readrq > 2048)
2464                         pcie_set_readrq(dev, 2048);
2465         }
2466 }
2467 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2468                          PCI_DEVICE_ID_TIGON3_5719,
2469                          quirk_brcm_5719_limit_mrrs);
2470 
2471 /*
2472  * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2473  * hide device 6 which configures the overflow device access containing the
2474  * DRBs - this is where we expose device 6.
2475  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2476  */
2477 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2478 {
2479         u8 reg;
2480 
2481         if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2482                 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2483                 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2484         }
2485 }
2486 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2487                         quirk_unhide_mch_dev6);
2488 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2489                         quirk_unhide_mch_dev6);
2490 
2491 #ifdef CONFIG_PCI_MSI
2492 /*
2493  * Some chipsets do not support MSI. We cannot easily rely on setting
2494  * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2495  * other buses controlled by the chipset even if Linux is not aware of it.
2496  * Instead of setting the flag on all buses in the machine, simply disable
2497  * MSI globally.
2498  */
2499 static void quirk_disable_all_msi(struct pci_dev *dev)
2500 {
2501         pci_no_msi();
2502         pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2503 }
2504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2507 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2510 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2512 
2513 /* Disable MSI on chipsets that are known to not support it */
2514 static void quirk_disable_msi(struct pci_dev *dev)
2515 {
2516         if (dev->subordinate) {
2517                 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2518                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2519         }
2520 }
2521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2524 
2525 /*
2526  * The APC bridge device in AMD 780 family northbridges has some random
2527  * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2528  * we use the possible vendor/device IDs of the host bridge for the
2529  * declared quirk, and search for the APC bridge by slot number.
2530  */
2531 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2532 {
2533         struct pci_dev *apc_bridge;
2534 
2535         apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2536         if (apc_bridge) {
2537                 if (apc_bridge->device == 0x9602)
2538                         quirk_disable_msi(apc_bridge);
2539                 pci_dev_put(apc_bridge);
2540         }
2541 }
2542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2544 
2545 /*
2546  * Go through the list of HyperTransport capabilities and return 1 if a HT
2547  * MSI capability is found and enabled.
2548  */
2549 static int msi_ht_cap_enabled(struct pci_dev *dev)
2550 {
2551         int pos, ttl = PCI_FIND_CAP_TTL;
2552 
2553         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2554         while (pos && ttl--) {
2555                 u8 flags;
2556 
2557                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2558                                          &flags) == 0) {
2559                         pci_info(dev, "Found %s HT MSI Mapping\n",
2560                                 flags & HT_MSI_FLAGS_ENABLE ?
2561                                 "enabled" : "disabled");
2562                         return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2563                 }
2564 
2565                 pos = pci_find_next_ht_capability(dev, pos,
2566                                                   HT_CAPTYPE_MSI_MAPPING);
2567         }
2568         return 0;
2569 }
2570 
2571 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2572 static void quirk_msi_ht_cap(struct pci_dev *dev)
2573 {
2574         if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2575                 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2576                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2577         }
2578 }
2579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2580                         quirk_msi_ht_cap);
2581 
2582 /*
2583  * The nVidia CK804 chipset may have 2 HT MSI mappings.  MSI is supported
2584  * if the MSI capability is set in any of these mappings.
2585  */
2586 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2587 {
2588         struct pci_dev *pdev;
2589 
2590         if (!dev->subordinate)
2591                 return;
2592 
2593         /*
2594          * Check HT MSI cap on this chipset and the root one.  A single one
2595          * having MSI is enough to be sure that MSI is supported.
2596          */
2597         pdev = pci_get_slot(dev->bus, 0);
2598         if (!pdev)
2599                 return;
2600         if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2601                 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2602                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2603         }
2604         pci_dev_put(pdev);
2605 }
2606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2607                         quirk_nvidia_ck804_msi_ht_cap);
2608 
2609 /* Force enable MSI mapping capability on HT bridges */
2610 static void ht_enable_msi_mapping(struct pci_dev *dev)
2611 {
2612         int pos, ttl = PCI_FIND_CAP_TTL;
2613 
2614         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2615         while (pos && ttl--) {
2616                 u8 flags;
2617 
2618                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2619                                          &flags) == 0) {
2620                         pci_info(dev, "Enabling HT MSI Mapping\n");
2621 
2622                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2623                                               flags | HT_MSI_FLAGS_ENABLE);
2624                 }
2625                 pos = pci_find_next_ht_capability(dev, pos,
2626                                                   HT_CAPTYPE_MSI_MAPPING);
2627         }
2628 }
2629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2630                          PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2631                          ht_enable_msi_mapping);
2632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2633                          ht_enable_msi_mapping);
2634 
2635 /*
2636  * The P5N32-SLI motherboards from Asus have a problem with MSI
2637  * for the MCP55 NIC. It is not yet determined whether the MSI problem
2638  * also affects other devices. As for now, turn off MSI for this device.
2639  */
2640 static void nvenet_msi_disable(struct pci_dev *dev)
2641 {
2642         const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2643 
2644         if (board_name &&
2645             (strstr(board_name, "P5N32-SLI PREMIUM") ||
2646              strstr(board_name, "P5N32-E SLI"))) {
2647                 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2648                 dev->no_msi = 1;
2649         }
2650 }
2651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2652                         PCI_DEVICE_ID_NVIDIA_NVENET_15,
2653                         nvenet_msi_disable);
2654 
2655 /*
2656  * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2657  * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2658  * generate MSI interrupts for PME and AER events instead only INTx interrupts
2659  * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2660  * for other events, since PCIe specificiation doesn't support using a mix of
2661  * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2662  * service drivers registering their respective ISRs for MSIs.
2663  */
2664 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2665 {
2666         dev->no_msi = 1;
2667 }
2668 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2669                               PCI_CLASS_BRIDGE_PCI, 8,
2670                               pci_quirk_nvidia_tegra_disable_rp_msi);
2671 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2672                               PCI_CLASS_BRIDGE_PCI, 8,
2673                               pci_quirk_nvidia_tegra_disable_rp_msi);
2674 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2675                               PCI_CLASS_BRIDGE_PCI, 8,
2676                               pci_quirk_nvidia_tegra_disable_rp_msi);
2677 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2678                               PCI_CLASS_BRIDGE_PCI, 8,
2679                               pci_quirk_nvidia_tegra_disable_rp_msi);
2680 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2681                               PCI_CLASS_BRIDGE_PCI, 8,
2682                               pci_quirk_nvidia_tegra_disable_rp_msi);
2683 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2684                               PCI_CLASS_BRIDGE_PCI, 8,
2685                               pci_quirk_nvidia_tegra_disable_rp_msi);
2686 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2687                               PCI_CLASS_BRIDGE_PCI, 8,
2688                               pci_quirk_nvidia_tegra_disable_rp_msi);
2689 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2690                               PCI_CLASS_BRIDGE_PCI, 8,
2691                               pci_quirk_nvidia_tegra_disable_rp_msi);
2692 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2693                               PCI_CLASS_BRIDGE_PCI, 8,
2694                               pci_quirk_nvidia_tegra_disable_rp_msi);
2695 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2696                               PCI_CLASS_BRIDGE_PCI, 8,
2697                               pci_quirk_nvidia_tegra_disable_rp_msi);
2698 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2699                               PCI_CLASS_BRIDGE_PCI, 8,
2700                               pci_quirk_nvidia_tegra_disable_rp_msi);
2701 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2702                               PCI_CLASS_BRIDGE_PCI, 8,
2703                               pci_quirk_nvidia_tegra_disable_rp_msi);
2704 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2705                               PCI_CLASS_BRIDGE_PCI, 8,
2706                               pci_quirk_nvidia_tegra_disable_rp_msi);
2707 
2708 /*
2709  * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2710  * config register.  This register controls the routing of legacy
2711  * interrupts from devices that route through the MCP55.  If this register
2712  * is misprogrammed, interrupts are only sent to the BSP, unlike
2713  * conventional systems where the IRQ is broadcast to all online CPUs.  Not
2714  * having this register set properly prevents kdump from booting up
2715  * properly, so let's make sure that we have it set correctly.
2716  * Note that this is an undocumented register.
2717  */
2718 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2719 {
2720         u32 cfg;
2721 
2722         if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2723                 return;
2724 
2725         pci_read_config_dword(dev, 0x74, &cfg);
2726 
2727         if (cfg & ((1 << 2) | (1 << 15))) {
2728                 pr_info("Rewriting IRQ routing register on MCP55\n");
2729                 cfg &= ~((1 << 2) | (1 << 15));
2730                 pci_write_config_dword(dev, 0x74, cfg);
2731         }
2732 }
2733 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2734                         PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2735                         nvbridge_check_legacy_irq_routing);
2736 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2737                         PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2738                         nvbridge_check_legacy_irq_routing);
2739 
2740 static int ht_check_msi_mapping(struct pci_dev *dev)
2741 {
2742         int pos, ttl = PCI_FIND_CAP_TTL;
2743         int found = 0;
2744 
2745         /* Check if there is HT MSI cap or enabled on this device */
2746         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2747         while (pos && ttl--) {
2748                 u8 flags;
2749 
2750                 if (found < 1)
2751                         found = 1;
2752                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2753                                          &flags) == 0) {
2754                         if (flags & HT_MSI_FLAGS_ENABLE) {
2755                                 if (found < 2) {
2756                                         found = 2;
2757                                         break;
2758                                 }
2759                         }
2760                 }
2761                 pos = pci_find_next_ht_capability(dev, pos,
2762                                                   HT_CAPTYPE_MSI_MAPPING);
2763         }
2764 
2765         return found;
2766 }
2767 
2768 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2769 {
2770         struct pci_dev *dev;
2771         int pos;
2772         int i, dev_no;
2773         int found = 0;
2774 
2775         dev_no = host_bridge->devfn >> 3;
2776         for (i = dev_no + 1; i < 0x20; i++) {
2777                 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2778                 if (!dev)
2779                         continue;
2780 
2781                 /* found next host bridge? */
2782                 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2783                 if (pos != 0) {
2784                         pci_dev_put(dev);
2785                         break;
2786                 }
2787 
2788                 if (ht_check_msi_mapping(dev)) {
2789                         found = 1;
2790                         pci_dev_put(dev);
2791                         break;
2792                 }
2793                 pci_dev_put(dev);
2794         }
2795 
2796         return found;
2797 }
2798 
2799 #define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
2800 #define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */
2801 
2802 static int is_end_of_ht_chain(struct pci_dev *dev)
2803 {
2804         int pos, ctrl_off;
2805         int end = 0;
2806         u16 flags, ctrl;
2807 
2808         pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2809 
2810         if (!pos)
2811                 goto out;
2812 
2813         pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2814 
2815         ctrl_off = ((flags >> 10) & 1) ?
2816                         PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2817         pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2818 
2819         if (ctrl & (1 << 6))
2820                 end = 1;
2821 
2822 out:
2823         return end;
2824 }
2825 
2826 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2827 {
2828         struct pci_dev *host_bridge;
2829         int pos;
2830         int i, dev_no;
2831         int found = 0;
2832 
2833         dev_no = dev->devfn >> 3;
2834         for (i = dev_no; i >= 0; i--) {
2835                 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2836                 if (!host_bridge)
2837                         continue;
2838 
2839                 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2840                 if (pos != 0) {
2841                         found = 1;
2842                         break;
2843                 }
2844                 pci_dev_put(host_bridge);
2845         }
2846 
2847         if (!found)
2848                 return;
2849 
2850         /* don't enable end_device/host_bridge with leaf directly here */
2851         if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2852             host_bridge_with_leaf(host_bridge))
2853                 goto out;
2854 
2855         /* root did that ! */
2856         if (msi_ht_cap_enabled(host_bridge))
2857                 goto out;
2858 
2859         ht_enable_msi_mapping(dev);
2860 
2861 out:
2862         pci_dev_put(host_bridge);
2863 }
2864 
2865 static void ht_disable_msi_mapping(struct pci_dev *dev)
2866 {
2867         int pos, ttl = PCI_FIND_CAP_TTL;
2868 
2869         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2870         while (pos && ttl--) {
2871                 u8 flags;
2872 
2873                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2874                                          &flags) == 0) {
2875                         pci_info(dev, "Disabling HT MSI Mapping\n");
2876 
2877                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2878                                               flags & ~HT_MSI_FLAGS_ENABLE);
2879                 }
2880                 pos = pci_find_next_ht_capability(dev, pos,
2881                                                   HT_CAPTYPE_MSI_MAPPING);
2882         }
2883 }
2884 
2885 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2886 {
2887         struct pci_dev *host_bridge;
2888         int pos;
2889         int found;
2890 
2891         if (!pci_msi_enabled())
2892                 return;
2893 
2894         /* check if there is HT MSI cap or enabled on this device */
2895         found = ht_check_msi_mapping(dev);
2896 
2897         /* no HT MSI CAP */
2898         if (found == 0)
2899                 return;
2900 
2901         /*
2902          * HT MSI mapping should be disabled on devices that are below
2903          * a non-Hypertransport host bridge. Locate the host bridge...
2904          */
2905         host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2906                                                   PCI_DEVFN(0, 0));
2907         if (host_bridge == NULL) {
2908                 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2909                 return;
2910         }
2911 
2912         pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2913         if (pos != 0) {
2914                 /* Host bridge is to HT */
2915                 if (found == 1) {
2916                         /* it is not enabled, try to enable it */
2917                         if (all)
2918                                 ht_enable_msi_mapping(dev);
2919                         else
2920                                 nv_ht_enable_msi_mapping(dev);
2921                 }
2922                 goto out;
2923         }
2924 
2925         /* HT MSI is not enabled */
2926         if (found == 1)
2927                 goto out;
2928 
2929         /* Host bridge is not to HT, disable HT MSI mapping on this device */
2930         ht_disable_msi_mapping(dev);
2931 
2932 out:
2933         pci_dev_put(host_bridge);
2934 }
2935 
2936 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2937 {
2938         return __nv_msi_ht_cap_quirk(dev, 1);
2939 }
2940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2941 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2942 
2943 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2944 {
2945         return __nv_msi_ht_cap_quirk(dev, 0);
2946 }
2947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2948 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2949 
2950 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2951 {
2952         dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2953 }
2954 
2955 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2956 {
2957         struct pci_dev *p;
2958 
2959         /*
2960          * SB700 MSI issue will be fixed at HW level from revision A21;
2961          * we need check PCI REVISION ID of SMBus controller to get SB700
2962          * revision.
2963          */
2964         p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2965                            NULL);
2966         if (!p)
2967                 return;
2968 
2969         if ((p->revision < 0x3B) && (p->revision >= 0x30))
2970                 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2971         pci_dev_put(p);
2972 }
2973 
2974 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2975 {
2976         /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2977         if (dev->revision < 0x18) {
2978                 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2979                 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2980         }
2981 }
2982 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2983                         PCI_DEVICE_ID_TIGON3_5780,
2984                         quirk_msi_intx_disable_bug);
2985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2986                         PCI_DEVICE_ID_TIGON3_5780S,
2987                         quirk_msi_intx_disable_bug);
2988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2989                         PCI_DEVICE_ID_TIGON3_5714,
2990                         quirk_msi_intx_disable_bug);
2991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2992                         PCI_DEVICE_ID_TIGON3_5714S,
2993                         quirk_msi_intx_disable_bug);
2994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2995                         PCI_DEVICE_ID_TIGON3_5715,
2996                         quirk_msi_intx_disable_bug);
2997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2998                         PCI_DEVICE_ID_TIGON3_5715S,
2999                         quirk_msi_intx_disable_bug);
3000 
3001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3002                         quirk_msi_intx_disable_ati_bug);
3003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3004                         quirk_msi_intx_disable_ati_bug);
3005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3006                         quirk_msi_intx_disable_ati_bug);
3007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3008                         quirk_msi_intx_disable_ati_bug);
3009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3010                         quirk_msi_intx_disable_ati_bug);
3011 
3012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3013                         quirk_msi_intx_disable_bug);
3014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3015                         quirk_msi_intx_disable_bug);
3016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3017                         quirk_msi_intx_disable_bug);
3018 
3019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3020                         quirk_msi_intx_disable_bug);
3021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3022                         quirk_msi_intx_disable_bug);
3023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3024                         quirk_msi_intx_disable_bug);
3025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3026                         quirk_msi_intx_disable_bug);
3027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3028                         quirk_msi_intx_disable_bug);
3029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3030                         quirk_msi_intx_disable_bug);
3031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3032                         quirk_msi_intx_disable_qca_bug);
3033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3034                         quirk_msi_intx_disable_qca_bug);
3035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3036                         quirk_msi_intx_disable_qca_bug);
3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3038                         quirk_msi_intx_disable_qca_bug);
3039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3040                         quirk_msi_intx_disable_qca_bug);
3041 
3042 /*
3043  * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3044  * should be disabled on platforms where the device (mistakenly) advertises it.
3045  *
3046  * Notice that this quirk also disables MSI (which may work, but hasn't been
3047  * tested), since currently there is no standard way to disable only MSI-X.
3048  *
3049  * The 0031 device id is reused for other non Root Port device types,
3050  * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3051  */
3052 static void quirk_al_msi_disable(struct pci_dev *dev)
3053 {
3054         dev->no_msi = 1;
3055         pci_warn(dev, "Disabling MSI/MSI-X\n");
3056 }
3057 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3058                               PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3059 #endif /* CONFIG_PCI_MSI */
3060 
3061 /*
3062  * Allow manual resource allocation for PCI hotplug bridges via
3063  * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3064  * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3065  * allocate resources when hotplug device is inserted and PCI bus is
3066  * rescanned.
3067  */
3068 static void quirk_hotplug_bridge(struct pci_dev *dev)
3069 {
3070         dev->is_hotplug_bridge = 1;
3071 }
3072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3073 
3074 /*
3075  * This is a quirk for the Ricoh MMC controller found as a part of some
3076  * multifunction chips.
3077  *
3078  * This is very similar and based on the ricoh_mmc driver written by
3079  * Philip Langdale. Thank you for these magic sequences.
3080  *
3081  * These chips implement the four main memory card controllers (SD, MMC,
3082  * MS, xD) and one or both of CardBus or FireWire.
3083  *
3084  * It happens that they implement SD and MMC support as separate
3085  * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3086  * cards but the chip detects MMC cards in hardware and directs them to the
3087  * MMC controller - so the SDHCI driver never sees them.
3088  *
3089  * To get around this, we must disable the useless MMC controller.  At that
3090  * point, the SDHCI controller will start seeing them.  It seems to be the
3091  * case that the relevant PCI registers to deactivate the MMC controller
3092  * live on PCI function 0, which might be the CardBus controller or the
3093  * FireWire controller, depending on the particular chip in question
3094  *
3095  * This has to be done early, because as soon as we disable the MMC controller
3096  * other PCI functions shift up one level, e.g. function #2 becomes function
3097  * #1, and this will confuse the PCI core.
3098  */
3099 #ifdef CONFIG_MMC_RICOH_MMC
3100 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3101 {
3102         u8 write_enable;
3103         u8 write_target;
3104         u8 disable;
3105 
3106         /*
3107          * Disable via CardBus interface
3108          *
3109          * This must be done via function #0
3110          */
3111         if (PCI_FUNC(dev->devfn))
3112                 return;
3113 
3114         pci_read_config_byte(dev, 0xB7, &disable);
3115         if (disable & 0x02)
3116                 return;
3117 
3118         pci_read_config_byte(dev, 0x8E, &write_enable);
3119         pci_write_config_byte(dev, 0x8E, 0xAA);
3120         pci_read_config_byte(dev, 0x8D, &write_target);
3121         pci_write_config_byte(dev, 0x8D, 0xB7);
3122         pci_write_config_byte(dev, 0xB7, disable | 0x02);
3123         pci_write_config_byte(dev, 0x8E, write_enable);
3124         pci_write_config_byte(dev, 0x8D, write_target);
3125 
3126         pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3127         pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3128 }
3129 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3130 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3131 
3132 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3133 {
3134         u8 write_enable;
3135         u8 disable;
3136 
3137         /*
3138          * Disable via FireWire interface
3139          *
3140          * This must be done via function #0
3141          */
3142         if (PCI_FUNC(dev->devfn))
3143                 return;
3144         /*
3145          * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3146          * certain types of SD/MMC cards. Lowering the SD base clock
3147          * frequency from 200Mhz to 50Mhz fixes this issue.
3148          *
3149          * 0x150 - SD2.0 mode enable for changing base clock
3150          *         frequency to 50Mhz
3151          * 0xe1  - Base clock frequency
3152          * 0x32  - 50Mhz new clock frequency
3153          * 0xf9  - Key register for 0x150
3154          * 0xfc  - key register for 0xe1
3155          */
3156         if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3157             dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3158                 pci_write_config_byte(dev, 0xf9, 0xfc);
3159                 pci_write_config_byte(dev, 0x150, 0x10);
3160                 pci_write_config_byte(dev, 0xf9, 0x00);
3161                 pci_write_config_byte(dev, 0xfc, 0x01);
3162                 pci_write_config_byte(dev, 0xe1, 0x32);
3163                 pci_write_config_byte(dev, 0xfc, 0x00);
3164 
3165                 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3166         }
3167 
3168         pci_read_config_byte(dev, 0xCB, &disable);
3169 
3170         if (disable & 0x02)
3171                 return;
3172 
3173         pci_read_config_byte(dev, 0xCA, &write_enable);
3174         pci_write_config_byte(dev, 0xCA, 0x57);
3175         pci_write_config_byte(dev, 0xCB, disable | 0x02);
3176         pci_write_config_byte(dev, 0xCA, write_enable);
3177 
3178         pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3179         pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3180 
3181 }
3182 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3183 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3184 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3185 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3186 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3187 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3188 #endif /*CONFIG_MMC_RICOH_MMC*/
3189 
3190 #ifdef CONFIG_DMAR_TABLE
3191 #define VTUNCERRMSK_REG 0x1ac
3192 #define VTD_MSK_SPEC_ERRORS     (1 << 31)
3193 /*
3194  * This is a quirk for masking VT-d spec-defined errors to platform error
3195  * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3196  * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3197  * on the RAS config settings of the platform) when a VT-d fault happens.
3198  * The resulting SMI caused the system to hang.
3199  *
3200  * VT-d spec-related errors are already handled by the VT-d OS code, so no
3201  * need to report the same error through other channels.
3202  */
3203 static void vtd_mask_spec_errors(struct pci_dev *dev)
3204 {
3205         u32 word;
3206 
3207         pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3208         pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3209 }
3210 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3211 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3212 #endif
3213 
3214 static void fixup_ti816x_class(struct pci_dev *dev)
3215 {
3216         u32 class = dev->class;
3217 
3218         /* TI 816x devices do not have class code set when in PCIe boot mode */
3219         dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3220         pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3221                  class, dev->class);
3222 }
3223 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3224                               PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3225 
3226 /*
3227  * Some PCIe devices do not work reliably with the claimed maximum
3228  * payload size supported.
3229  */
3230 static void fixup_mpss_256(struct pci_dev *dev)
3231 {
3232         dev->pcie_mpss = 1; /* 256 bytes */
3233 }
3234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3235                          PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3237                          PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3239                          PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3240 
3241 /*
3242  * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3243  * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3244  * Since there is no way of knowing what the PCIe MPS on each fabric will be
3245  * until all of the devices are discovered and buses walked, read completion
3246  * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
3247  * it is possible to hotplug a device with MPS of 256B.
3248  */
3249 static void quirk_intel_mc_errata(struct pci_dev *dev)
3250 {
3251         int err;
3252         u16 rcc;
3253 
3254         if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3255             pcie_bus_config == PCIE_BUS_DEFAULT)
3256                 return;
3257 
3258         /*
3259          * Intel erratum specifies bits to change but does not say what
3260          * they are.  Keeping them magical until such time as the registers
3261          * and values can be explained.
3262          */
3263         err = pci_read_config_word(dev, 0x48, &rcc);
3264         if (err) {
3265                 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3266                 return;
3267         }
3268 
3269         if (!(rcc & (1 << 10)))
3270                 return;
3271 
3272         rcc &= ~(1 << 10);
3273 
3274         err = pci_write_config_word(dev, 0x48, rcc);
3275         if (err) {
3276                 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3277                 return;
3278         }
3279 
3280         pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3281 }
3282 /* Intel 5000 series memory controllers and ports 2-7 */
3283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3297 /* Intel 5100 series memory controllers and ports 2-7 */
3298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3309 
3310 /*
3311  * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3312  * To work around this, query the size it should be configured to by the
3313  * device and modify the resource end to correspond to this new size.
3314  */
3315 static void quirk_intel_ntb(struct pci_dev *dev)
3316 {
3317         int rc;
3318         u8 val;
3319 
3320         rc = pci_read_config_byte(dev, 0x00D0, &val);
3321         if (rc)
3322                 return;
3323 
3324         dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3325 
3326         rc = pci_read_config_byte(dev, 0x00D1, &val);
3327         if (rc)
3328                 return;
3329 
3330         dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3331 }
3332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3334 
3335 /*
3336  * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3337  * though no one is handling them (e.g., if the i915 driver is never
3338  * loaded).  Additionally the interrupt destination is not set up properly
3339  * and the interrupt ends up -somewhere-.
3340  *
3341  * These spurious interrupts are "sticky" and the kernel disables the
3342  * (shared) interrupt line after 100,000+ generated interrupts.
3343  *
3344  * Fix it by disabling the still enabled interrupts.  This resolves crashes
3345  * often seen on monitor unplug.
3346  */
3347 #define I915_DEIER_REG 0x4400c
3348 static void disable_igfx_irq(struct pci_dev *dev)
3349 {
3350         void __iomem *regs = pci_iomap(dev, 0, 0);
3351         if (regs == NULL) {
3352                 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3353                 return;
3354         }
3355 
3356         /* Check if any interrupt line is still enabled */
3357         if (readl(regs + I915_DEIER_REG) != 0) {
3358                 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3359 
3360                 writel(0, regs + I915_DEIER_REG);
3361         }
3362 
3363         pci_iounmap(dev, regs);
3364 }
3365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3366 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3372 
3373 /*
3374  * PCI devices which are on Intel chips can skip the 10ms delay
3375  * before entering D3 mode.
3376  */
3377 static void quirk_remove_d3_delay(struct pci_dev *dev)
3378 {
3379         dev->d3_delay = 0;
3380 }
3381 /* C600 Series devices do not need 10ms d3_delay */
3382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3385 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3397 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3407 
3408 /*
3409  * Some devices may pass our check in pci_intx_mask_supported() if
3410  * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3411  * support this feature.
3412  */
3413 static void quirk_broken_intx_masking(struct pci_dev *dev)
3414 {
3415         dev->broken_intx_masking = 1;
3416 }
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3418                         quirk_broken_intx_masking);
3419 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3420                         quirk_broken_intx_masking);
3421 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3422                         quirk_broken_intx_masking);
3423 
3424 /*
3425  * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3426  * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3427  *
3428  * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3429  */
3430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3431                         quirk_broken_intx_masking);
3432 
3433 /*
3434  * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3435  * DisINTx can be set but the interrupt status bit is non-functional.
3436  */
3437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3453 
3454 static u16 mellanox_broken_intx_devs[] = {
3455         PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3456         PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3457         PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3458         PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3459         PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3460         PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3461         PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3462         PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3463         PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3464         PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3465         PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3466         PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3467         PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3468         PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3469 };
3470 
3471 #define CONNECTX_4_CURR_MAX_MINOR 99
3472 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3473 
3474 /*
3475  * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3476  * If so, don't mark it as broken.
3477  * FW minor > 99 means older FW version format and no INTx masking support.
3478  * FW minor < 14 means new FW version format and no INTx masking support.
3479  */
3480 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3481 {
3482         __be32 __iomem *fw_ver;
3483         u16 fw_major;
3484         u16 fw_minor;
3485         u16 fw_subminor;
3486         u32 fw_maj_min;
3487         u32 fw_sub_min;
3488         int i;
3489 
3490         for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3491                 if (pdev->device == mellanox_broken_intx_devs[i]) {
3492                         pdev->broken_intx_masking = 1;
3493                         return;
3494                 }
3495         }
3496 
3497         /*
3498          * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3499          * support so shouldn't be checked further
3500          */
3501         if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3502                 return;
3503 
3504         if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3505             pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3506                 return;
3507 
3508         /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3509         if (pci_enable_device_mem(pdev)) {
3510                 pci_warn(pdev, "Can't enable device memory\n");
3511                 return;
3512         }
3513 
3514         fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3515         if (!fw_ver) {
3516                 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3517                 goto out;
3518         }
3519 
3520         /* Reading from resource space should be 32b aligned */
3521         fw_maj_min = ioread32be(fw_ver);
3522         fw_sub_min = ioread32be(fw_ver + 1);
3523         fw_major = fw_maj_min & 0xffff;
3524         fw_minor = fw_maj_min >> 16;
3525         fw_subminor = fw_sub_min & 0xffff;
3526         if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3527             fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3528                 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3529                          fw_major, fw_minor, fw_subminor, pdev->device ==
3530                          PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3531                 pdev->broken_intx_masking = 1;
3532         }
3533 
3534         iounmap(fw_ver);
3535 
3536 out:
3537         pci_disable_device(pdev);
3538 }
3539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3540                         mellanox_check_broken_intx_masking);
3541 
3542 static void quirk_no_bus_reset(struct pci_dev *dev)
3543 {
3544         dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3545 }
3546 
3547 /*
3548  * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3549  * The device will throw a Link Down error on AER-capable systems and
3550  * regardless of AER, config space of the device is never accessible again
3551  * and typically causes the system to hang or reset when access is attempted.
3552  * http://www.spinics.net/lists/linux-pci/msg34797.html
3553  */
3554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3559 
3560 /*
3561  * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3562  * reset when used with certain child devices.  After the reset, config
3563  * accesses to the child may fail.
3564  */
3565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3566 
3567 static void quirk_no_pm_reset(struct pci_dev *dev)
3568 {
3569         /*
3570          * We can't do a bus reset on root bus devices, but an ineffective
3571          * PM reset may be better than nothing.
3572          */
3573         if (!pci_is_root_bus(dev->bus))
3574                 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3575 }
3576 
3577 /*
3578  * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3579  * causes a reset (i.e., they advertise NoSoftRst-).  This transition seems
3580  * to have no effect on the device: it retains the framebuffer contents and
3581  * monitor sync.  Advertising this support makes other layers, like VFIO,
3582  * assume pci_reset_function() is viable for this device.  Mark it as
3583  * unavailable to skip it when testing reset methods.
3584  */
3585 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3586                                PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3587 
3588 /*
3589  * Thunderbolt controllers with broken MSI hotplug signaling:
3590  * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3591  * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3592  */
3593 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3594 {
3595         if (pdev->is_hotplug_bridge &&
3596             (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3597              pdev->revision <= 1))
3598                 pdev->no_msi = 1;
3599 }
3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3601                         quirk_thunderbolt_hotplug_msi);
3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3603                         quirk_thunderbolt_hotplug_msi);
3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3605                         quirk_thunderbolt_hotplug_msi);
3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3607                         quirk_thunderbolt_hotplug_msi);
3608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3609                         quirk_thunderbolt_hotplug_msi);
3610 
3611 #ifdef CONFIG_ACPI
3612 /*
3613  * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3614  *
3615  * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3616  * shutdown before suspend. Otherwise the native host interface (NHI) will not
3617  * be present after resume if a device was plugged in before suspend.
3618  *
3619  * The Thunderbolt controller consists of a PCIe switch with downstream
3620  * bridges leading to the NHI and to the tunnel PCI bridges.
3621  *
3622  * This quirk cuts power to the whole chip. Therefore we have to apply it
3623  * during suspend_noirq of the upstream bridge.
3624  *
3625  * Power is automagically restored before resume. No action is needed.
3626  */
3627 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3628 {
3629         acpi_handle bridge, SXIO, SXFP, SXLV;
3630 
3631         if (!x86_apple_machine)
3632                 return;
3633         if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3634                 return;
3635         bridge = ACPI_HANDLE(&dev->dev);
3636         if (!bridge)
3637                 return;
3638 
3639         /*
3640          * SXIO and SXLV are present only on machines requiring this quirk.
3641          * Thunderbolt bridges in external devices might have the same
3642          * device ID as those on the host, but they will not have the
3643          * associated ACPI methods. This implicitly checks that we are at
3644          * the right bridge.
3645          */
3646         if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3647             || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3648             || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3649                 return;
3650         pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3651 
3652         /* magic sequence */
3653         acpi_execute_simple_method(SXIO, NULL, 1);
3654         acpi_execute_simple_method(SXFP, NULL, 0);
3655         msleep(300);
3656         acpi_execute_simple_method(SXLV, NULL, 0);
3657         acpi_execute_simple_method(SXIO, NULL, 0);
3658         acpi_execute_simple_method(SXLV, NULL, 0);
3659 }
3660 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3661                                PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3662                                quirk_apple_poweroff_thunderbolt);
3663 
3664 /*
3665  * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3666  *
3667  * During suspend the Thunderbolt controller is reset and all PCI
3668  * tunnels are lost. The NHI driver will try to reestablish all tunnels
3669  * during resume. We have to manually wait for the NHI since there is
3670  * no parent child relationship between the NHI and the tunneled
3671  * bridges.
3672  */
3673 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3674 {
3675         struct pci_dev *sibling = NULL;
3676         struct pci_dev *nhi = NULL;
3677 
3678         if (!x86_apple_machine)
3679                 return;
3680         if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3681                 return;
3682 
3683         /*
3684          * Find the NHI and confirm that we are a bridge on the Thunderbolt
3685          * host controller and not on a Thunderbolt endpoint.
3686          */
3687         sibling = pci_get_slot(dev->bus, 0x0);
3688         if (sibling == dev)
3689                 goto out; /* we are the downstream bridge to the NHI */
3690         if (!sibling || !sibling->subordinate)
3691                 goto out;
3692         nhi = pci_get_slot(sibling->subordinate, 0x0);
3693         if (!nhi)
3694                 goto out;
3695         if (nhi->vendor != PCI_VENDOR_ID_INTEL
3696                     || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3697                         nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3698                         nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3699                         nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3700                     || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3701                 goto out;
3702         pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3703         device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3704 out:
3705         pci_dev_put(nhi);
3706         pci_dev_put(sibling);
3707 }
3708 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3709                                PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3710                                quirk_apple_wait_for_thunderbolt);
3711 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3712                                PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3713                                quirk_apple_wait_for_thunderbolt);
3714 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3715                                PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3716                                quirk_apple_wait_for_thunderbolt);
3717 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3718                                PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3719                                quirk_apple_wait_for_thunderbolt);
3720 #endif
3721 
3722 /*
3723  * Following are device-specific reset methods which can be used to
3724  * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3725  * not available.
3726  */
3727 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3728 {
3729         /*
3730          * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3731          *
3732          * The 82599 supports FLR on VFs, but FLR support is reported only
3733          * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3734          * Thus we must call pcie_flr() directly without first checking if it is
3735          * supported.
3736          */
3737         if (!probe)
3738                 pcie_flr(dev);
3739         return 0;
3740 }
3741 
3742 #define SOUTH_CHICKEN2          0xc2004
3743 #define PCH_PP_STATUS           0xc7200
3744 #define PCH_PP_CONTROL          0xc7204
3745 #define MSG_CTL                 0x45010
3746 #define NSDE_PWR_STATE          0xd0100
3747 #define IGD_OPERATION_TIMEOUT   10000     /* set timeout 10 seconds */
3748 
3749 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3750 {
3751         void __iomem *mmio_base;
3752         unsigned long timeout;
3753         u32 val;
3754 
3755         if (probe)
3756                 return 0;
3757 
3758         mmio_base = pci_iomap(dev, 0, 0);
3759         if (!mmio_base)
3760                 return -ENOMEM;
3761 
3762         iowrite32(0x00000002, mmio_base + MSG_CTL);
3763 
3764         /*
3765          * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3766          * driver loaded sets the right bits. However, this's a reset and
3767          * the bits have been set by i915 previously, so we clobber
3768          * SOUTH_CHICKEN2 register directly here.
3769          */
3770         iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3771 
3772         val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3773         iowrite32(val, mmio_base + PCH_PP_CONTROL);
3774 
3775         timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3776         do {
3777                 val = ioread32(mmio_base + PCH_PP_STATUS);
3778                 if ((val & 0xb0000000) == 0)
3779                         goto reset_complete;
3780                 msleep(10);
3781         } while (time_before(jiffies, timeout));
3782         pci_warn(dev, "timeout during reset\n");
3783 
3784 reset_complete:
3785         iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3786 
3787         pci_iounmap(dev, mmio_base);
3788         return 0;
3789 }
3790 
3791 /* Device-specific reset method for Chelsio T4-based adapters */
3792 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3793 {
3794         u16 old_command;
3795         u16 msix_flags;
3796 
3797         /*
3798          * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3799          * that we have no device-specific reset method.
3800          */
3801         if ((dev->device & 0xf000) != 0x4000)
3802                 return -ENOTTY;
3803 
3804         /*
3805          * If this is the "probe" phase, return 0 indicating that we can
3806          * reset this device.
3807          */
3808         if (probe)
3809                 return 0;
3810 
3811         /*
3812          * T4 can wedge if there are DMAs in flight within the chip and Bus
3813          * Master has been disabled.  We need to have it on till the Function
3814          * Level Reset completes.  (BUS_MASTER is disabled in
3815          * pci_reset_function()).
3816          */
3817         pci_read_config_word(dev, PCI_COMMAND, &old_command);
3818         pci_write_config_word(dev, PCI_COMMAND,
3819                               old_command | PCI_COMMAND_MASTER);
3820 
3821         /*
3822          * Perform the actual device function reset, saving and restoring
3823          * configuration information around the reset.
3824          */
3825         pci_save_state(dev);
3826 
3827         /*
3828          * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3829          * are disabled when an MSI-X interrupt message needs to be delivered.
3830          * So we briefly re-enable MSI-X interrupts for the duration of the
3831          * FLR.  The pci_restore_state() below will restore the original
3832          * MSI-X state.
3833          */
3834         pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3835         if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3836                 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3837                                       msix_flags |
3838                                       PCI_MSIX_FLAGS_ENABLE |
3839                                       PCI_MSIX_FLAGS_MASKALL);
3840 
3841         pcie_flr(dev);
3842 
3843         /*
3844          * Restore the configuration information (BAR values, etc.) including
3845          * the original PCI Configuration Space Command word, and return
3846          * success.
3847          */
3848         pci_restore_state(dev);
3849         pci_write_config_word(dev, PCI_COMMAND, old_command);
3850         return 0;
3851 }
3852 
3853 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
3854 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
3855 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166
3856 
3857 /*
3858  * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3859  * FLR where config space reads from the device return -1.  We seem to be
3860  * able to avoid this condition if we disable the NVMe controller prior to
3861  * FLR.  This quirk is generic for any NVMe class device requiring similar
3862  * assistance to quiesce the device prior to FLR.
3863  *
3864  * NVMe specification: https://nvmexpress.org/resources/specifications/
3865  * Revision 1.0e:
3866  *    Chapter 2: Required and optional PCI config registers
3867  *    Chapter 3: NVMe control registers
3868  *    Chapter 7.3: Reset behavior
3869  */
3870 static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3871 {
3872         void __iomem *bar;
3873         u16 cmd;
3874         u32 cfg;
3875 
3876         if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3877             !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3878                 return -ENOTTY;
3879 
3880         if (probe)
3881                 return 0;
3882 
3883         bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3884         if (!bar)
3885                 return -ENOTTY;
3886 
3887         pci_read_config_word(dev, PCI_COMMAND, &cmd);
3888         pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3889 
3890         cfg = readl(bar + NVME_REG_CC);
3891 
3892         /* Disable controller if enabled */
3893         if (cfg & NVME_CC_ENABLE) {
3894                 u32 cap = readl(bar + NVME_REG_CAP);
3895                 unsigned long timeout;
3896 
3897                 /*
3898                  * Per nvme_disable_ctrl() skip shutdown notification as it
3899                  * could complete commands to the admin queue.  We only intend
3900                  * to quiesce the device before reset.
3901                  */
3902                 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3903 
3904                 writel(cfg, bar + NVME_REG_CC);
3905 
3906                 /*
3907                  * Some controllers require an additional delay here, see
3908                  * NVME_QUIRK_DELAY_BEFORE_CHK_RDY.  None of those are yet
3909                  * supported by this quirk.
3910                  */
3911 
3912                 /* Cap register provides max timeout in 500ms increments */
3913                 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3914 
3915                 for (;;) {
3916                         u32 status = readl(bar + NVME_REG_CSTS);
3917 
3918                         /* Ready status becomes zero on disable complete */
3919                         if (!(status & NVME_CSTS_RDY))
3920                                 break;
3921 
3922                         msleep(100);
3923 
3924                         if (time_after(jiffies, timeout)) {
3925                                 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3926                                 break;
3927                         }
3928                 }
3929         }
3930 
3931         pci_iounmap(dev, bar);
3932 
3933         pcie_flr(dev);
3934 
3935         return 0;
3936 }
3937 
3938 /*
3939  * Intel DC P3700 NVMe controller will timeout waiting for ready status
3940  * to change after NVMe enable if the driver starts interacting with the
3941  * device too soon after FLR.  A 250ms delay after FLR has heuristically
3942  * proven to produce reliably working results for device assignment cases.
3943  */
3944 static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3945 {
3946         if (!pcie_has_flr(dev))
3947                 return -ENOTTY;
3948 
3949         if (probe)
3950                 return 0;
3951 
3952         pcie_flr(dev);
3953 
3954         msleep(250);
3955 
3956         return 0;
3957 }
3958 
3959 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3960         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3961                  reset_intel_82599_sfp_virtfn },
3962         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3963                 reset_ivb_igd },
3964         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3965                 reset_ivb_igd },
3966         { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3967         { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3968         { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3969                 reset_chelsio_generic_dev },
3970         { 0 }
3971 };
3972 
3973 /*
3974  * These device-specific reset methods are here rather than in a driver
3975  * because when a host assigns a device to a guest VM, the host may need
3976  * to reset the device but probably doesn't have a driver for it.
3977  */
3978 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3979 {
3980         const struct pci_dev_reset_methods *i;
3981 
3982         for (i = pci_dev_reset_methods; i->reset; i++) {
3983                 if ((i->vendor == dev->vendor ||
3984                      i->vendor == (u16)PCI_ANY_ID) &&
3985                     (i->device == dev->device ||
3986                      i->device == (u16)PCI_ANY_ID))
3987                         return i->reset(dev, probe);
3988         }
3989 
3990         return -ENOTTY;
3991 }
3992 
3993 static void quirk_dma_func0_alias(struct pci_dev *dev)
3994 {
3995         if (PCI_FUNC(dev->devfn) != 0)
3996                 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
3997 }
3998 
3999 /*
4000  * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4001  *
4002  * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4003  */
4004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4006 
4007 static void quirk_dma_func1_alias(struct pci_dev *dev)
4008 {
4009         if (PCI_FUNC(dev->devfn) != 1)
4010                 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4011 }
4012 
4013 /*
4014  * Marvell 88SE9123 uses function 1 as the requester ID for DMA.  In some
4015  * SKUs function 1 is present and is a legacy IDE controller, in other
4016  * SKUs this function is not present, making this a ghost requester.
4017  * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4018  */
4019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4020                          quirk_dma_func1_alias);
4021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4022                          quirk_dma_func1_alias);
4023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4024                          quirk_dma_func1_alias);
4025 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4027                          quirk_dma_func1_alias);
4028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4029                          quirk_dma_func1_alias);
4030 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4032                          quirk_dma_func1_alias);
4033 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4035                          quirk_dma_func1_alias);
4036 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4038                          quirk_dma_func1_alias);
4039 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4040 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4041                          quirk_dma_func1_alias);
4042 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4043 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4044                          quirk_dma_func1_alias);
4045 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4047                          quirk_dma_func1_alias);
4048 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4050                          quirk_dma_func1_alias);
4051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4052                          quirk_dma_func1_alias);
4053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4054                          quirk_dma_func1_alias);
4055 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4057                          PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4058                          quirk_dma_func1_alias);
4059 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4060 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4061                          0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4062                          quirk_dma_func1_alias);
4063 
4064 /*
4065  * Some devices DMA with the wrong devfn, not just the wrong function.
4066  * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4067  * the alias is "fixed" and independent of the device devfn.
4068  *
4069  * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4070  * processor.  To software, this appears as a PCIe-to-PCI/X bridge with a
4071  * single device on the secondary bus.  In reality, the single exposed
4072  * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4073  * that provides a bridge to the internal bus of the I/O processor.  The
4074  * controller supports private devices, which can be hidden from PCI config
4075  * space.  In the case of the Adaptec 3405, a private device at 01.0
4076  * appears to be the DMA engine, which therefore needs to become a DMA
4077  * alias for the device.
4078  */
4079 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4080         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4081                          PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4082           .driver_data = PCI_DEVFN(1, 0) },
4083         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4084                          PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4085           .driver_data = PCI_DEVFN(1, 0) },
4086         { 0 }
4087 };
4088 
4089 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4090 {
4091         const struct pci_device_id *id;
4092 
4093         id = pci_match_id(fixed_dma_alias_tbl, dev);
4094         if (id)
4095                 pci_add_dma_alias(dev, id->driver_data, 1);
4096 }
4097 
4098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4099 
4100 /*
4101  * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4102  * using the wrong DMA alias for the device.  Some of these devices can be
4103  * used as either forward or reverse bridges, so we need to test whether the
4104  * device is operating in the correct mode.  We could probably apply this
4105  * quirk to PCI_ANY_ID, but for now we'll just use known offenders.  The test
4106  * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4107  * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4108  */
4109 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4110 {
4111         if (!pci_is_root_bus(pdev->bus) &&
4112             pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4113             !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4114             pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4115                 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4116 }
4117 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4119                          quirk_use_pcie_bridge_dma_alias);
4120 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4121 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4122 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4123 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4124 /* ITE 8893 has the same problem as the 8892 */
4125 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4126 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4127 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4128 
4129 /*
4130  * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4131  * be added as aliases to the DMA device in order to allow buffer access
4132  * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4133  * programmed in the EEPROM.
4134  */
4135 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4136 {
4137         pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4138         pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4139         pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4140 }
4141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4143 
4144 /*
4145  * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4146  * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4147  *
4148  * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4149  * when IOMMU is enabled.  These aliases allow computational unit access to
4150  * host memory.  These aliases mark the whole VCA device as one IOMMU
4151  * group.
4152  *
4153  * All possible slot numbers (0x20) are used, since we are unable to tell
4154  * what slot is used on other side.  This quirk is intended for both host
4155  * and computational unit sides.  The VCA devices have up to five functions
4156  * (four for DMA channels and one additional).
4157  */
4158 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4159 {
4160         const unsigned int num_pci_slots = 0x20;
4161         unsigned int slot;
4162 
4163         for (slot = 0; slot < num_pci_slots; slot++)
4164                 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4165 }
4166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4172 
4173 /*
4174  * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4175  * associated not at the root bus, but at a bridge below. This quirk avoids
4176  * generating invalid DMA aliases.
4177  */
4178 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4179 {
4180         pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4181 }
4182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4183                                 quirk_bridge_cavm_thrx2_pcie_root);
4184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4185                                 quirk_bridge_cavm_thrx2_pcie_root);
4186 
4187 /*
4188  * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4189  * class code.  Fix it.
4190  */
4191 static void quirk_tw686x_class(struct pci_dev *pdev)
4192 {
4193         u32 class = pdev->class;
4194 
4195         /* Use "Multimedia controller" class */
4196         pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4197         pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4198                  class, pdev->class);
4199 }
4200 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4201                               quirk_tw686x_class);
4202 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4203                               quirk_tw686x_class);
4204 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4205                               quirk_tw686x_class);
4206 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4207                               quirk_tw686x_class);
4208 
4209 /*
4210  * Some devices have problems with Transaction Layer Packets with the Relaxed
4211  * Ordering Attribute set.  Such devices should mark themselves and other
4212  * device drivers should check before sending TLPs with RO set.
4213  */
4214 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4215 {
4216         dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4217         pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4218 }
4219 
4220 /*
4221  * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4222  * Complex have a Flow Control Credit issue which can cause performance
4223  * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4224  */
4225 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4226                               quirk_relaxedordering_disable);
4227 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4228                               quirk_relaxedordering_disable);
4229 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4230                               quirk_relaxedordering_disable);
4231 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4232                               quirk_relaxedordering_disable);
4233 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4234                               quirk_relaxedordering_disable);
4235 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4236                               quirk_relaxedordering_disable);
4237 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4238                               quirk_relaxedordering_disable);
4239 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4240                               quirk_relaxedordering_disable);
4241 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4242                               quirk_relaxedordering_disable);
4243 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4244                               quirk_relaxedordering_disable);
4245 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4246                               quirk_relaxedordering_disable);
4247 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4248                               quirk_relaxedordering_disable);
4249 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4250                               quirk_relaxedordering_disable);
4251 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4252                               quirk_relaxedordering_disable);
4253 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4254                               quirk_relaxedordering_disable);
4255 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4256                               quirk_relaxedordering_disable);
4257 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4258                               quirk_relaxedordering_disable);
4259 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4260                               quirk_relaxedordering_disable);
4261 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4262                               quirk_relaxedordering_disable);
4263 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4264                               quirk_relaxedordering_disable);
4265 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4266                               quirk_relaxedordering_disable);
4267 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4268                               quirk_relaxedordering_disable);
4269 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4270                               quirk_relaxedordering_disable);
4271 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4272                               quirk_relaxedordering_disable);
4273 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4274                               quirk_relaxedordering_disable);
4275 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4276                               quirk_relaxedordering_disable);
4277 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4278                               quirk_relaxedordering_disable);
4279 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4280                               quirk_relaxedordering_disable);
4281 
4282 /*
4283  * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4284  * where Upstream Transaction Layer Packets with the Relaxed Ordering
4285  * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4286  * set.  This is a violation of the PCIe 3.0 Transaction Ordering Rules
4287  * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4288  * November 10, 2010).  As a result, on this platform we can't use Relaxed
4289  * Ordering for Upstream TLPs.
4290  */
4291 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4292                               quirk_relaxedordering_disable);
4293 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4294                               quirk_relaxedordering_disable);
4295 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4296                               quirk_relaxedordering_disable);
4297 
4298 /*
4299  * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4300  * values for the Attribute as were supplied in the header of the
4301  * corresponding Request, except as explicitly allowed when IDO is used."
4302  *
4303  * If a non-compliant device generates a completion with a different
4304  * attribute than the request, the receiver may accept it (which itself
4305  * seems non-compliant based on sec 2.3.2), or it may handle it as a
4306  * Malformed TLP or an Unexpected Completion, which will probably lead to a
4307  * device access timeout.
4308  *
4309  * If the non-compliant device generates completions with zero attributes
4310  * (instead of copying the attributes from the request), we can work around
4311  * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4312  * upstream devices so they always generate requests with zero attributes.
4313  *
4314  * This affects other devices under the same Root Port, but since these
4315  * attributes are performance hints, there should be no functional problem.
4316  *
4317  * Note that Configuration Space accesses are never supposed to have TLP
4318  * Attributes, so we're safe waiting till after any Configuration Space
4319  * accesses to do the Root Port fixup.
4320  */
4321 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4322 {
4323         struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4324 
4325         if (!root_port) {
4326                 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4327                 return;
4328         }
4329 
4330         pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4331                  dev_name(&pdev->dev));
4332         pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4333                                            PCI_EXP_DEVCTL_RELAX_EN |
4334                                            PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4335 }
4336 
4337 /*
4338  * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4339  * Completion it generates.
4340  */
4341 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4342 {
4343         /*
4344          * This mask/compare operation selects for Physical Function 4 on a
4345          * T5.  We only need to fix up the Root Port once for any of the
4346          * PFs.  PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4347          * 0x54xx so we use that one.
4348          */
4349         if ((pdev->device & 0xff00) == 0x5400)
4350                 quirk_disable_root_port_attributes(pdev);
4351 }
4352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4353                          quirk_chelsio_T5_disable_root_port_attributes);
4354 
4355 /*
4356  * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4357  *                        by a device
4358  * @acs_ctrl_req: Bitmask of desired ACS controls
4359  * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4360  *                the hardware design
4361  *
4362  * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4363  * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4364  * caller desires.  Return 0 otherwise.
4365  */
4366 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4367 {
4368         if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4369                 return 1;
4370         return 0;
4371 }
4372 
4373 /*
4374  * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4375  * But the implementation could block peer-to-peer transactions between them
4376  * and provide ACS-like functionality.
4377  */
4378 static int  pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4379 {
4380         if (!pci_is_pcie(dev) ||
4381             ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4382              (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4383                 return -ENOTTY;
4384 
4385         switch (dev->device) {
4386         case 0x0710 ... 0x071e:
4387         case 0x0721:
4388         case 0x0723 ... 0x0732:
4389                 return pci_acs_ctrl_enabled(acs_flags,
4390                         PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4391         }
4392 
4393         return false;
4394 }
4395 
4396 /*
4397  * AMD has indicated that the devices below do not support peer-to-peer
4398  * in any system where they are found in the southbridge with an AMD
4399  * IOMMU in the system.  Multifunction devices that do not support
4400  * peer-to-peer between functions can claim to support a subset of ACS.
4401  * Such devices effectively enable request redirect (RR) and completion
4402  * redirect (CR) since all transactions are redirected to the upstream
4403  * root complex.
4404  *
4405  * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4406  * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4407  * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4408  *
4409  * 1002:4385 SBx00 SMBus Controller
4410  * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4411  * 1002:4383 SBx00 Azalia (Intel HDA)
4412  * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4413  * 1002:4384 SBx00 PCI to PCI Bridge
4414  * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4415  *
4416  * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4417  *
4418  * 1022:780f [AMD] FCH PCI Bridge
4419  * 1022:7809 [AMD] FCH USB OHCI Controller
4420  */
4421 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4422 {
4423 #ifdef CONFIG_ACPI
4424         struct acpi_table_header *header = NULL;
4425         acpi_status status;
4426 
4427         /* Targeting multifunction devices on the SB (appears on root bus) */
4428         if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4429                 return -ENODEV;
4430 
4431         /* The IVRS table describes the AMD IOMMU */
4432         status = acpi_get_table("IVRS", 0, &header);
4433         if (ACPI_FAILURE(status))
4434                 return -ENODEV;
4435 
4436         /* Filter out flags not applicable to multifunction */
4437         acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4438 
4439         return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4440 #else
4441         return -ENODEV;
4442 #endif
4443 }
4444 
4445 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4446 {
4447         if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4448                 return false;
4449 
4450         switch (dev->device) {
4451         /*
4452          * Effectively selects all downstream ports for whole ThunderX1
4453          * (which represents 8 SoCs).
4454          */
4455         case 0xa000 ... 0xa7ff: /* ThunderX1 */
4456         case 0xaf84:  /* ThunderX2 */
4457         case 0xb884:  /* ThunderX3 */
4458                 return true;
4459         default:
4460                 return false;
4461         }
4462 }
4463 
4464 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4465 {
4466         if (!pci_quirk_cavium_acs_match(dev))
4467                 return -ENOTTY;
4468 
4469         /*
4470          * Cavium Root Ports don't advertise an ACS capability.  However,
4471          * the RTL internally implements similar protection as if ACS had
4472          * Source Validation, Request Redirection, Completion Redirection,
4473          * and Upstream Forwarding features enabled.  Assert that the
4474          * hardware implements and enables equivalent ACS functionality for
4475          * these flags.
4476          */
4477         return pci_acs_ctrl_enabled(acs_flags,
4478                 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4479 }
4480 
4481 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4482 {
4483         /*
4484          * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4485          * transactions with others, allowing masking out these bits as if they
4486          * were unimplemented in the ACS capability.
4487          */
4488         return pci_acs_ctrl_enabled(acs_flags,
4489                 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4490 }
4491 
4492 /*
4493  * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4494  * transactions and validate bus numbers in requests, but do not provide an
4495  * actual PCIe ACS capability.  This is the list of device IDs known to fall
4496  * into that category as provided by Intel in Red Hat bugzilla 1037684.
4497  */
4498 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4499         /* Ibexpeak PCH */
4500         0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4501         0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4502         /* Cougarpoint PCH */
4503         0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4504         0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4505         /* Pantherpoint PCH */
4506         0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4507         0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4508         /* Lynxpoint-H PCH */
4509         0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4510         0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4511         /* Lynxpoint-LP PCH */
4512         0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4513         0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4514         /* Wildcat PCH */
4515         0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4516         0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4517         /* Patsburg (X79) PCH */
4518         0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4519         /* Wellsburg (X99) PCH */
4520         0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4521         0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4522         /* Lynx Point (9 series) PCH */
4523         0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4524 };
4525 
4526 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4527 {
4528         int i;
4529 
4530         /* Filter out a few obvious non-matches first */
4531         if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4532                 return false;
4533 
4534         for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4535                 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4536                         return true;
4537 
4538         return false;
4539 }
4540 
4541 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4542 {
4543         if (!pci_quirk_intel_pch_acs_match(dev))
4544                 return -ENOTTY;
4545 
4546         if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4547                 return pci_acs_ctrl_enabled(acs_flags,
4548                         PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4549 
4550         return pci_acs_ctrl_enabled(acs_flags, 0);
4551 }
4552 
4553 /*
4554  * These QCOM Root Ports do provide ACS-like features to disable peer
4555  * transactions and validate bus numbers in requests, but do not provide an
4556  * actual PCIe ACS capability.  Hardware supports source validation but it
4557  * will report the issue as Completer Abort instead of ACS Violation.
4558  * Hardware doesn't support peer-to-peer and each Root Port is a Root
4559  * Complex with unique segment numbers.  It is not possible for one Root
4560  * Port to pass traffic to another Root Port.  All PCIe transactions are
4561  * terminated inside the Root Port.
4562  */
4563 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4564 {
4565         return pci_acs_ctrl_enabled(acs_flags,
4566                 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4567 }
4568 
4569 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4570 {
4571         if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4572                 return -ENOTTY;
4573 
4574         /*
4575          * Amazon's Annapurna Labs root ports don't include an ACS capability,
4576          * but do include ACS-like functionality. The hardware doesn't support
4577          * peer-to-peer transactions via the root port and each has a unique
4578          * segment number.
4579          *
4580          * Additionally, the root ports cannot send traffic to each other.
4581          */
4582         acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4583 
4584         return acs_flags ? 0 : 1;
4585 }
4586 
4587 /*
4588  * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4589  * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4590  * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4591  * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4592  * 7.16 ACS Extended Capability).  The bit definitions are correct, but the
4593  * control register is at offset 8 instead of 6 and we should probably use
4594  * dword accesses to them.  This applies to the following PCI Device IDs, as
4595  * found in volume 1 of the datasheet[2]:
4596  *
4597  * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4598  * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4599  *
4600  * N.B. This doesn't fix what lspci shows.
4601  *
4602  * The 100 series chipset specification update includes this as errata #23[3].
4603  *
4604  * The 200 series chipset (Union Point) has the same bug according to the
4605  * specification update (Intel 200 Series Chipset Family Platform Controller
4606  * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4607  * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
4608  * chipset include:
4609  *
4610  * 0xa290-0xa29f PCI Express Root port #{0-16}
4611  * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4612  *
4613  * Mobile chipsets are also affected, 7th & 8th Generation
4614  * Specification update confirms ACS errata 22, status no fix: (7th Generation
4615  * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4616  * Processor Family I/O for U Quad Core Platforms Specification Update,
4617  * August 2017, Revision 002, Document#: 334660-002)[6]
4618  * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4619  * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4620  * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4621  *
4622  * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4623  *
4624  * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4625  * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4626  * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4627  * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4628  * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4629  * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4630  * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4631  */
4632 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4633 {
4634         if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4635                 return false;
4636 
4637         switch (dev->device) {
4638         case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4639         case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4640         case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4641                 return true;
4642         }
4643 
4644         return false;
4645 }
4646 
4647 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4648 
4649 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4650 {
4651         int pos;
4652         u32 cap, ctrl;
4653 
4654         if (!pci_quirk_intel_spt_pch_acs_match(dev))
4655                 return -ENOTTY;
4656 
4657         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4658         if (!pos)
4659                 return -ENOTTY;
4660 
4661         /* see pci_acs_flags_enabled() */
4662         pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4663         acs_flags &= (cap | PCI_ACS_EC);
4664 
4665         pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4666 
4667         return pci_acs_ctrl_enabled(acs_flags, ctrl);
4668 }
4669 
4670 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4671 {
4672         /*
4673          * SV, TB, and UF are not relevant to multifunction endpoints.
4674          *
4675          * Multifunction devices are only required to implement RR, CR, and DT
4676          * in their ACS capability if they support peer-to-peer transactions.
4677          * Devices matching this quirk have been verified by the vendor to not
4678          * perform peer-to-peer with other functions, allowing us to mask out
4679          * these bits as if they were unimplemented in the ACS capability.
4680          */
4681         return pci_acs_ctrl_enabled(acs_flags,
4682                 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4683                 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4684 }
4685 
4686 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4687 {
4688         /*
4689          * iProc PAXB Root Ports don't advertise an ACS capability, but
4690          * they do not allow peer-to-peer transactions between Root Ports.
4691          * Allow each Root Port to be in a separate IOMMU group by masking
4692          * SV/RR/CR/UF bits.
4693          */
4694         return pci_acs_ctrl_enabled(acs_flags,
4695                 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4696 }
4697 
4698 static const struct pci_dev_acs_enabled {
4699         u16 vendor;
4700         u16 device;
4701         int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4702 } pci_dev_acs_enabled[] = {
4703         { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4704         { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4705         { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4706         { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4707         { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4708         { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4709         { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4710         { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4711         { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4712         { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4713         { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4714         { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4715         { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4716         { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4717         { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4718         { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4719         { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4720         { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4721         { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4722         { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4723         { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4724         { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4725         { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4726         { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4727         { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4728         { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4729         { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4730         { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4731         { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4732         { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4733         { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4734         /* 82580 */
4735         { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4736         { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4737         { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4738         { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4739         { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4740         { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4741         { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4742         /* 82576 */
4743         { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4744         { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4745         { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4746         { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4747         { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4748         { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4749         { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4750         { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4751         /* 82575 */
4752         { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4753         { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4754         { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4755         /* I350 */
4756         { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4757         { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4758         { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4759         { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4760         /* 82571 (Quads omitted due to non-ACS switch) */
4761         { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4762         { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4763         { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4764         { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4765         /* I219 */
4766         { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4767         { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4768         /* QCOM QDF2xxx root ports */
4769         { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4770         { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4771         /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4772         { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4773         /* Intel PCH root ports */
4774         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4775         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4776         { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4777         { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4778         /* Cavium ThunderX */
4779         { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4780         /* APM X-Gene */
4781         { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4782         /* Ampere Computing */
4783         { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4784         { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4785         { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4786         { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4787         { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4788         { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4789         { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4790         { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4791         { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4792         /* Amazon Annapurna Labs */
4793         { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4794         /* Zhaoxin multi-function devices */
4795         { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4796         { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4797         { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4798         /* Zhaoxin Root/Downstream Ports */
4799         { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4800         { 0 }
4801 };
4802 
4803 /*
4804  * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4805  * @dev:        PCI device
4806  * @acs_flags:  Bitmask of desired ACS controls
4807  *
4808  * Returns:
4809  *   -ENOTTY:   No quirk applies to this device; we can't tell whether the
4810  *              device provides the desired controls
4811  *   0:         Device does not provide all the desired controls
4812  *   >0:        Device provides all the controls in @acs_flags
4813  */
4814 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4815 {
4816         const struct pci_dev_acs_enabled *i;
4817         int ret;
4818 
4819         /*
4820          * Allow devices that do not expose standard PCIe ACS capabilities
4821          * or control to indicate their support here.  Multi-function express
4822          * devices which do not allow internal peer-to-peer between functions,
4823          * but do not implement PCIe ACS may wish to return true here.
4824          */
4825         for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4826                 if ((i->vendor == dev->vendor ||
4827                      i->vendor == (u16)PCI_ANY_ID) &&
4828                     (i->device == dev->device ||
4829                      i->device == (u16)PCI_ANY_ID)) {
4830                         ret = i->acs_enabled(dev, acs_flags);
4831                         if (ret >= 0)
4832                                 return ret;
4833                 }
4834         }
4835 
4836         return -ENOTTY;
4837 }
4838 
4839 /* Config space offset of Root Complex Base Address register */
4840 #define INTEL_LPC_RCBA_REG 0xf0
4841 /* 31:14 RCBA address */
4842 #define INTEL_LPC_RCBA_MASK 0xffffc000
4843 /* RCBA Enable */
4844 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4845 
4846 /* Backbone Scratch Pad Register */
4847 #define INTEL_BSPR_REG 0x1104
4848 /* Backbone Peer Non-Posted Disable */
4849 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4850 /* Backbone Peer Posted Disable */
4851 #define INTEL_BSPR_REG_BPPD  (1 << 9)
4852 
4853 /* Upstream Peer Decode Configuration Register */
4854 #define INTEL_UPDCR_REG 0x1014
4855 /* 5:0 Peer Decode Enable bits */
4856 #define INTEL_UPDCR_REG_MASK 0x3f
4857 
4858 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4859 {
4860         u32 rcba, bspr, updcr;
4861         void __iomem *rcba_mem;
4862 
4863         /*
4864          * Read the RCBA register from the LPC (D31:F0).  PCH root ports
4865          * are D28:F* and therefore get probed before LPC, thus we can't
4866          * use pci_get_slot()/pci_read_config_dword() here.
4867          */
4868         pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4869                                   INTEL_LPC_RCBA_REG, &rcba);
4870         if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4871                 return -EINVAL;
4872 
4873         rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4874                                    PAGE_ALIGN(INTEL_UPDCR_REG));
4875         if (!rcba_mem)
4876                 return -ENOMEM;
4877 
4878         /*
4879          * The BSPR can disallow peer cycles, but it's set by soft strap and
4880          * therefore read-only.  If both posted and non-posted peer cycles are
4881          * disallowed, we're ok.  If either are allowed, then we need to use
4882          * the UPDCR to disable peer decodes for each port.  This provides the
4883          * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4884          */
4885         bspr = readl(rcba_mem + INTEL_BSPR_REG);
4886         bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4887         if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4888                 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4889                 if (updcr & INTEL_UPDCR_REG_MASK) {
4890                         pci_info(dev, "Disabling UPDCR peer decodes\n");
4891                         updcr &= ~INTEL_UPDCR_REG_MASK;
4892                         writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4893                 }
4894         }
4895 
4896         iounmap(rcba_mem);
4897         return 0;
4898 }
4899 
4900 /* Miscellaneous Port Configuration register */
4901 #define INTEL_MPC_REG 0xd8
4902 /* MPC: Invalid Receive Bus Number Check Enable */
4903 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4904 
4905 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4906 {
4907         u32 mpc;
4908 
4909         /*
4910          * When enabled, the IRBNCE bit of the MPC register enables the
4911          * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4912          * ensures that requester IDs fall within the bus number range
4913          * of the bridge.  Enable if not already.
4914          */
4915         pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4916         if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4917                 pci_info(dev, "Enabling MPC IRBNCE\n");
4918                 mpc |= INTEL_MPC_REG_IRBNCE;
4919                 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4920         }
4921 }
4922 
4923 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4924 {
4925         if (!pci_quirk_intel_pch_acs_match(dev))
4926                 return -ENOTTY;
4927 
4928         if (pci_quirk_enable_intel_lpc_acs(dev)) {
4929                 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4930                 return 0;
4931         }
4932 
4933         pci_quirk_enable_intel_rp_mpc_acs(dev);
4934 
4935         dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4936 
4937         pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4938 
4939         return 0;
4940 }
4941 
4942 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4943 {
4944         int pos;
4945         u32 cap, ctrl;
4946 
4947         if (!pci_quirk_intel_spt_pch_acs_match(dev))
4948                 return -ENOTTY;
4949 
4950         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4951         if (!pos)
4952                 return -ENOTTY;
4953 
4954         pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4955         pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4956 
4957         ctrl |= (cap & PCI_ACS_SV);
4958         ctrl |= (cap & PCI_ACS_RR);
4959         ctrl |= (cap & PCI_ACS_CR);
4960         ctrl |= (cap & PCI_ACS_UF);
4961 
4962         pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4963 
4964         pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4965 
4966         return 0;
4967 }
4968 
4969 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4970 {
4971         int pos;
4972         u32 cap, ctrl;
4973 
4974         if (!pci_quirk_intel_spt_pch_acs_match(dev))
4975                 return -ENOTTY;
4976 
4977         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4978         if (!pos)
4979                 return -ENOTTY;
4980 
4981         pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4982         pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4983 
4984         ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
4985 
4986         pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4987 
4988         pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4989 
4990         return 0;
4991 }
4992 
4993 static const struct pci_dev_acs_ops {
4994         u16 vendor;
4995         u16 device;
4996         int (*enable_acs)(struct pci_dev *dev);
4997         int (*disable_acs_redir)(struct pci_dev *dev);
4998 } pci_dev_acs_ops[] = {
4999         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5000             .enable_acs = pci_quirk_enable_intel_pch_acs,
5001         },
5002         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5003             .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5004             .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5005         },
5006 };
5007 
5008 int pci_dev_specific_enable_acs(struct pci_dev *dev)
5009 {
5010         const struct pci_dev_acs_ops *p;
5011         int i, ret;
5012 
5013         for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5014                 p = &pci_dev_acs_ops[i];
5015                 if ((p->vendor == dev->vendor ||
5016                      p->vendor == (u16)PCI_ANY_ID) &&
5017                     (p->device == dev->device ||
5018                      p->device == (u16)PCI_ANY_ID) &&
5019                     p->enable_acs) {
5020                         ret = p->enable_acs(dev);
5021                         if (ret >= 0)
5022                                 return ret;
5023                 }
5024         }
5025 
5026         return -ENOTTY;
5027 }
5028 
5029 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5030 {
5031         const struct pci_dev_acs_ops *p;
5032         int i, ret;
5033 
5034         for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5035                 p = &pci_dev_acs_ops[i];
5036                 if ((p->vendor == dev->vendor ||
5037                      p->vendor == (u16)PCI_ANY_ID) &&
5038                     (p->device == dev->device ||
5039                      p->device == (u16)PCI_ANY_ID) &&
5040                     p->disable_acs_redir) {
5041                         ret = p->disable_acs_redir(dev);
5042                         if (ret >= 0)
5043                                 return ret;
5044                 }
5045         }
5046 
5047         return -ENOTTY;
5048 }
5049 
5050 /*
5051  * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5052  * QuickAssist Technology (QAT) is prematurely terminated in hardware.  The
5053  * Next Capability pointer in the MSI Capability Structure should point to
5054  * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5055  * the list.
5056  */
5057 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5058 {
5059         int pos, i = 0;
5060         u8 next_cap;
5061         u16 reg16, *cap;
5062         struct pci_cap_saved_state *state;
5063 
5064         /* Bail if the hardware bug is fixed */
5065         if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5066                 return;
5067 
5068         /* Bail if MSI Capability Structure is not found for some reason */
5069         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5070         if (!pos)
5071                 return;
5072 
5073         /*
5074          * Bail if Next Capability pointer in the MSI Capability Structure
5075          * is not the expected incorrect 0x00.
5076          */
5077         pci_read_config_byte(pdev, pos + 1, &next_cap);
5078         if (next_cap)
5079                 return;
5080 
5081         /*
5082          * PCIe Capability Structure is expected to be at 0x50 and should
5083          * terminate the list (Next Capability pointer is 0x00).  Verify
5084          * Capability Id and Next Capability pointer is as expected.
5085          * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5086          * to correctly set kernel data structures which have already been
5087          * set incorrectly due to the hardware bug.
5088          */
5089         pos = 0x50;
5090         pci_read_config_word(pdev, pos, &reg16);
5091         if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5092                 u32 status;
5093 #ifndef PCI_EXP_SAVE_REGS
5094 #define PCI_EXP_SAVE_REGS     7
5095 #endif
5096                 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5097 
5098                 pdev->pcie_cap = pos;
5099                 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
5100                 pdev->pcie_flags_reg = reg16;
5101                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
5102                 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5103 
5104                 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5105                 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5106                     PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5107                         pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5108 
5109                 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5110                         return;
5111 
5112                 /* Save PCIe cap */
5113                 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5114                 if (!state)
5115                         return;
5116 
5117                 state->cap.cap_nr = PCI_CAP_ID_EXP;
5118                 state->cap.cap_extended = 0;
5119                 state->cap.size = size;
5120                 cap = (u16 *)&state->cap.data[0];
5121                 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5122                 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5123                 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5124                 pcie_capability_read_word(pdev, PCI_EXP_RTCTL,  &cap[i++]);
5125                 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5126                 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5127                 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5128                 hlist_add_head(&state->next, &pdev->saved_cap_space);
5129         }
5130 }
5131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5132 
5133 /* FLR may cause some 82579 devices to hang */
5134 static void quirk_intel_no_flr(struct pci_dev *dev)
5135 {
5136         dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5137 }
5138 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
5139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
5140 
5141 static void quirk_no_ext_tags(struct pci_dev *pdev)
5142 {
5143         struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5144 
5145         if (!bridge)
5146                 return;
5147 
5148         bridge->no_ext_tags = 1;
5149         pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5150 
5151         pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5152 }
5153 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5154 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5155 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5156 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5157 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5158 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5159 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5160 
5161 #ifdef CONFIG_PCI_ATS
5162 /*
5163  * Some devices require additional driver setup to enable ATS.  Don't use
5164  * ATS for those devices as ATS will be enabled before the driver has had a
5165  * chance to load and configure the device.
5166  */
5167 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5168 {
5169         if (pdev->device == 0x7340 && pdev->revision != 0xc5)
5170                 return;
5171 
5172         pci_info(pdev, "disabling ATS\n");
5173         pdev->ats_cap = 0;
5174 }
5175 
5176 /* AMD Stoney platform GPU */
5177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5178 /* AMD Iceland dGPU */
5179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5180 /* AMD Navi14 dGPU */
5181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5182 #endif /* CONFIG_PCI_ATS */
5183 
5184 /* Freescale PCIe doesn't support MSI in RC mode */
5185 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5186 {
5187         if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5188                 pdev->no_msi = 1;
5189 }
5190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5191 
5192 /*
5193  * Although not allowed by the spec, some multi-function devices have
5194  * dependencies of one function (consumer) on another (supplier).  For the
5195  * consumer to work in D0, the supplier must also be in D0.  Create a
5196  * device link from the consumer to the supplier to enforce this
5197  * dependency.  Runtime PM is allowed by default on the consumer to prevent
5198  * it from permanently keeping the supplier awake.
5199  */
5200 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5201                                    unsigned int supplier, unsigned int class,
5202                                    unsigned int class_shift)
5203 {
5204         struct pci_dev *supplier_pdev;
5205 
5206         if (PCI_FUNC(pdev->devfn) != consumer)
5207                 return;
5208 
5209         supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5210                                 pdev->bus->number,
5211                                 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5212         if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5213                 pci_dev_put(supplier_pdev);
5214                 return;
5215         }
5216 
5217         if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5218                             DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5219                 pci_info(pdev, "D0 power state depends on %s\n",
5220                          pci_name(supplier_pdev));
5221         else
5222                 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5223                         pci_name(supplier_pdev));
5224 
5225         pm_runtime_allow(&pdev->dev);
5226         pci_dev_put(supplier_pdev);
5227 }
5228 
5229 /*
5230  * Create device link for GPUs with integrated HDA controller for streaming
5231  * audio to attached displays.
5232  */
5233 static void quirk_gpu_hda(struct pci_dev *hda)
5234 {
5235         pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5236 }
5237 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5238                               PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5239 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5240                               PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5241 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5242                               PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5243 
5244 /*
5245  * Create device link for NVIDIA GPU with integrated USB xHCI Host
5246  * controller to VGA.
5247  */
5248 static void quirk_gpu_usb(struct pci_dev *usb)
5249 {
5250         pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5251 }
5252 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5253                               PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5254 
5255 /*
5256  * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5257  * to VGA. Currently there is no class code defined for UCSI device over PCI
5258  * so using UNKNOWN class for now and it will be updated when UCSI
5259  * over PCI gets a class code.
5260  */
5261 #define PCI_CLASS_SERIAL_UNKNOWN        0x0c80
5262 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5263 {
5264         pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5265 }
5266 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5267                               PCI_CLASS_SERIAL_UNKNOWN, 8,
5268                               quirk_gpu_usb_typec_ucsi);
5269 
5270 /*
5271  * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5272  * disabled.  https://devtalk.nvidia.com/default/topic/1024022
5273  */
5274 static void quirk_nvidia_hda(struct pci_dev *gpu)
5275 {
5276         u8 hdr_type;
5277         u32 val;
5278 
5279         /* There was no integrated HDA controller before MCP89 */
5280         if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5281                 return;
5282 
5283         /* Bit 25 at offset 0x488 enables the HDA controller */
5284         pci_read_config_dword(gpu, 0x488, &val);
5285         if (val & BIT(25))
5286                 return;
5287 
5288         pci_info(gpu, "Enabling HDA controller\n");
5289         pci_write_config_dword(gpu, 0x488, val | BIT(25));
5290 
5291         /* The GPU becomes a multi-function device when the HDA is enabled */
5292         pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5293         gpu->multifunction = !!(hdr_type & 0x80);
5294 }
5295 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5296                                PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5297 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5298                                PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5299 
5300 /*
5301  * Some IDT switches incorrectly flag an ACS Source Validation error on
5302  * completions for config read requests even though PCIe r4.0, sec
5303  * 6.12.1.1, says that completions are never affected by ACS Source
5304  * Validation.  Here's the text of IDT 89H32H8G3-YC, erratum #36:
5305  *
5306  *   Item #36 - Downstream port applies ACS Source Validation to Completions
5307  *   Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5308  *   completions are never affected by ACS Source Validation.  However,
5309  *   completions received by a downstream port of the PCIe switch from a
5310  *   device that has not yet captured a PCIe bus number are incorrectly
5311  *   dropped by ACS Source Validation by the switch downstream port.
5312  *
5313  * The workaround suggested by IDT is to issue a config write to the
5314  * downstream device before issuing the first config read.  This allows the
5315  * downstream device to capture its bus and device numbers (see PCIe r4.0,
5316  * sec 2.2.9), thus avoiding the ACS error on the completion.
5317  *
5318  * However, we don't know when the device is ready to accept the config
5319  * write, so we do config reads until we receive a non-Config Request Retry
5320  * Status, then do the config write.
5321  *
5322  * To avoid hitting the erratum when doing the config reads, we disable ACS
5323  * SV around this process.
5324  */
5325 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5326 {
5327         int pos;
5328         u16 ctrl = 0;
5329         bool found;
5330         struct pci_dev *bridge = bus->self;
5331 
5332         pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
5333 
5334         /* Disable ACS SV before initial config reads */
5335         if (pos) {
5336                 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5337                 if (ctrl & PCI_ACS_SV)
5338                         pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5339                                               ctrl & ~PCI_ACS_SV);
5340         }
5341 
5342         found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5343 
5344         /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5345         if (found)
5346                 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5347 
5348         /* Re-enable ACS_SV if it was previously enabled */
5349         if (ctrl & PCI_ACS_SV)
5350                 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5351 
5352         return found;
5353 }
5354 
5355 /*
5356  * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5357  * NT endpoints via the internal switch fabric. These IDs replace the
5358  * originating requestor ID TLPs which access host memory on peer NTB
5359  * ports. Therefore, all proxy IDs must be aliased to the NTB device
5360  * to permit access when the IOMMU is turned on.
5361  */
5362 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5363 {
5364         void __iomem *mmio;
5365         struct ntb_info_regs __iomem *mmio_ntb;
5366         struct ntb_ctrl_regs __iomem *mmio_ctrl;
5367         u64 partition_map;
5368         u8 partition;
5369         int pp;
5370 
5371         if (pci_enable_device(pdev)) {
5372                 pci_err(pdev, "Cannot enable Switchtec device\n");
5373                 return;
5374         }
5375 
5376         mmio = pci_iomap(pdev, 0, 0);
5377         if (mmio == NULL) {
5378                 pci_disable_device(pdev);
5379                 pci_err(pdev, "Cannot iomap Switchtec device\n");
5380                 return;
5381         }
5382 
5383         pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5384 
5385         mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5386         mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5387 
5388         partition = ioread8(&mmio_ntb->partition_id);
5389 
5390         partition_map = ioread32(&mmio_ntb->ep_map);
5391         partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5392         partition_map &= ~(1ULL << partition);
5393 
5394         for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5395                 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5396                 u32 table_sz = 0;
5397                 int te;
5398 
5399                 if (!(partition_map & (1ULL << pp)))
5400                         continue;
5401 
5402                 pci_dbg(pdev, "Processing partition %d\n", pp);
5403 
5404                 mmio_peer_ctrl = &mmio_ctrl[pp];
5405 
5406                 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5407                 if (!table_sz) {
5408                         pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5409                         continue;
5410                 }
5411 
5412                 if (table_sz > 512) {
5413                         pci_warn(pdev,
5414                                  "Invalid Switchtec partition %d table_sz %d\n",
5415                                  pp, table_sz);
5416                         continue;
5417                 }
5418 
5419                 for (te = 0; te < table_sz; te++) {
5420                         u32 rid_entry;
5421                         u8 devfn;
5422 
5423                         rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5424                         devfn = (rid_entry >> 1) & 0xFF;
5425                         pci_dbg(pdev,
5426                                 "Aliasing Partition %d Proxy ID %02x.%d\n",
5427                                 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5428                         pci_add_dma_alias(pdev, devfn, 1);
5429                 }
5430         }
5431 
5432         pci_iounmap(pdev, mmio);
5433         pci_disable_device(pdev);
5434 }
5435 #define SWITCHTEC_QUIRK(vid) \
5436         DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5437                 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5438 
5439 SWITCHTEC_QUIRK(0x8531);  /* PFX 24xG3 */
5440 SWITCHTEC_QUIRK(0x8532);  /* PFX 32xG3 */
5441 SWITCHTEC_QUIRK(0x8533);  /* PFX 48xG3 */
5442 SWITCHTEC_QUIRK(0x8534);  /* PFX 64xG3 */
5443 SWITCHTEC_QUIRK(0x8535);  /* PFX 80xG3 */
5444 SWITCHTEC_QUIRK(0x8536);  /* PFX 96xG3 */
5445 SWITCHTEC_QUIRK(0x8541);  /* PSX 24xG3 */
5446 SWITCHTEC_QUIRK(0x8542);  /* PSX 32xG3 */
5447 SWITCHTEC_QUIRK(0x8543);  /* PSX 48xG3 */
5448 SWITCHTEC_QUIRK(0x8544);  /* PSX 64xG3 */
5449 SWITCHTEC_QUIRK(0x8545);  /* PSX 80xG3 */
5450 SWITCHTEC_QUIRK(0x8546);  /* PSX 96xG3 */
5451 SWITCHTEC_QUIRK(0x8551);  /* PAX 24XG3 */
5452 SWITCHTEC_QUIRK(0x8552);  /* PAX 32XG3 */
5453 SWITCHTEC_QUIRK(0x8553);  /* PAX 48XG3 */
5454 SWITCHTEC_QUIRK(0x8554);  /* PAX 64XG3 */
5455 SWITCHTEC_QUIRK(0x8555);  /* PAX 80XG3 */
5456 SWITCHTEC_QUIRK(0x8556);  /* PAX 96XG3 */
5457 SWITCHTEC_QUIRK(0x8561);  /* PFXL 24XG3 */
5458 SWITCHTEC_QUIRK(0x8562);  /* PFXL 32XG3 */
5459 SWITCHTEC_QUIRK(0x8563);  /* PFXL 48XG3 */
5460 SWITCHTEC_QUIRK(0x8564);  /* PFXL 64XG3 */
5461 SWITCHTEC_QUIRK(0x8565);  /* PFXL 80XG3 */
5462 SWITCHTEC_QUIRK(0x8566);  /* PFXL 96XG3 */
5463 SWITCHTEC_QUIRK(0x8571);  /* PFXI 24XG3 */
5464 SWITCHTEC_QUIRK(0x8572);  /* PFXI 32XG3 */
5465 SWITCHTEC_QUIRK(0x8573);  /* PFXI 48XG3 */
5466 SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
5467 SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
5468 SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */
5469 
5470 /*
5471  * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5472  * These IDs are used to forward responses to the originator on the other
5473  * side of the NTB.  Alias all possible IDs to the NTB to permit access when
5474  * the IOMMU is turned on.
5475  */
5476 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5477 {
5478         pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5479         /* PLX NTB may use all 256 devfns */
5480         pci_add_dma_alias(pdev, 0, 256);
5481 }
5482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5484 
5485 /*
5486  * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5487  * not always reset the secondary Nvidia GPU between reboots if the system
5488  * is configured to use Hybrid Graphics mode.  This results in the GPU
5489  * being left in whatever state it was in during the *previous* boot, which
5490  * causes spurious interrupts from the GPU, which in turn causes us to
5491  * disable the wrong IRQ and end up breaking the touchpad.  Unsurprisingly,
5492  * this also completely breaks nouveau.
5493  *
5494  * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5495  * clean state and fixes all these issues.
5496  *
5497  * When the machine is configured in Dedicated display mode, the issue
5498  * doesn't occur.  Fortunately the GPU advertises NoReset+ when in this
5499  * mode, so we can detect that and avoid resetting it.
5500  */
5501 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5502 {
5503         void __iomem *map;
5504         int ret;
5505 
5506         if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5507             pdev->subsystem_device != 0x222e ||
5508             !pdev->reset_fn)
5509                 return;
5510 
5511         if (pci_enable_device_mem(pdev))
5512                 return;
5513 
5514         /*
5515          * Based on nvkm_device_ctor() in
5516          * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5517          */
5518         map = pci_iomap(pdev, 0, 0x23000);
5519         if (!map) {
5520                 pci_err(pdev, "Can't map MMIO space\n");
5521                 goto out_disable;
5522         }
5523 
5524         /*
5525          * Make sure the GPU looks like it's been POSTed before resetting
5526          * it.
5527          */
5528         if (ioread32(map + 0x2240c) & 0x2) {
5529                 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5530                 ret = pci_reset_bus(pdev);
5531                 if (ret < 0)
5532                         pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5533         }
5534 
5535         iounmap(map);
5536 out_disable:
5537         pci_disable_device(pdev);
5538 }
5539 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5540                               PCI_CLASS_DISPLAY_VGA, 8,
5541                               quirk_reset_lenovo_thinkpad_p50_nvgpu);
5542 
5543 /*
5544  * Device [1b21:2142]
5545  * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5546  */
5547 static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5548 {
5549         pci_info(dev, "PME# does not work under D0, disabling it\n");
5550         dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5551 }
5552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5553 
5554 static void apex_pci_fixup_class(struct pci_dev *pdev)
5555 {
5556         pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5557 }
5558 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5559                                PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);