drivers/pwm/pwm-stm32.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
to_stm32_pwm_dev
active_channels
write_ccrx
stm32_pwm_raw_capture
stm32_pwm_capture
stm32_pwm_config
stm32_pwm_set_polarity
stm32_pwm_enable
stm32_pwm_disable
stm32_pwm_apply
stm32_pwm_apply_locked
stm32_pwm_set_breakinput
stm32_pwm_apply_breakinputs
stm32_pwm_detect_complementary
stm32_pwm_detect_channels
stm32_pwm_probe
stm32_pwm_remove
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  *
   5  * Author: Gerald Baeza <gerald.baeza@st.com>
   6  *
   7  * Inspired by timer-stm32.c from Maxime Coquelin
   8  *             pwm-atmel.c from Bo Shen
   9  */
  10 
  11 #include <linux/bitfield.h>
  12 #include <linux/mfd/stm32-timers.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pwm.h>
  17 
  18 #define CCMR_CHANNEL_SHIFT 8
  19 #define CCMR_CHANNEL_MASK  0xFF
  20 #define MAX_BREAKINPUT 2
  21 
  22 struct stm32_pwm {
  23         struct pwm_chip chip;
  24         struct mutex lock; /* protect pwm config/enable */
  25         struct clk *clk;
  26         struct regmap *regmap;
  27         u32 max_arr;
  28         bool have_complementary_output;
  29         u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
  30 };
  31 
  32 struct stm32_breakinput {
  33         u32 index;
  34         u32 level;
  35         u32 filter;
  36 };
  37 
  38 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
  39 {
  40         return container_of(chip, struct stm32_pwm, chip);
  41 }
  42 
  43 static u32 active_channels(struct stm32_pwm *dev)
  44 {
  45         u32 ccer;
  46 
  47         regmap_read(dev->regmap, TIM_CCER, &ccer);
  48 
  49         return ccer & TIM_CCER_CCXE;
  50 }
  51 
  52 static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
  53 {
  54         switch (ch) {
  55         case 0:
  56                 return regmap_write(dev->regmap, TIM_CCR1, value);
  57         case 1:
  58                 return regmap_write(dev->regmap, TIM_CCR2, value);
  59         case 2:
  60                 return regmap_write(dev->regmap, TIM_CCR3, value);
  61         case 3:
  62                 return regmap_write(dev->regmap, TIM_CCR4, value);
  63         }
  64         return -EINVAL;
  65 }
  66 
  67 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
  68 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
  69 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
  70 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
  71 
  72 /*
  73  * Capture using PWM input mode:
  74  *                              ___          ___
  75  * TI[1, 2, 3 or 4]: ........._|   |________|
  76  *                             ^0  ^1       ^2
  77  *                              .   .        .
  78  *                              .   .        XXXXX
  79  *                              .   .   XXXXX     |
  80  *                              .  XXXXX     .    |
  81  *                            XXXXX .        .    |
  82  * COUNTER:        ______XXXXX  .   .        .    |_XXX
  83  *                 start^       .   .        .        ^stop
  84  *                      .       .   .        .
  85  *                      v       v   .        v
  86  *                                  v
  87  * CCR1/CCR3:       tx..........t0...........t2
  88  * CCR2/CCR4:       tx..............t1.........
  89  *
  90  * DMA burst transfer:          |            |
  91  *                              v            v
  92  * DMA buffer:                  { t0, tx }   { t2, t1 }
  93  * DMA done:                                 ^
  94  *
  95  * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
  96  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
  97  * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
  98  * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
  99  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
 100  *
 101  * DMA done, compute:
 102  * - Period     = t2 - t0
 103  * - Duty cycle = t1 - t0
 104  */
 105 static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
 106                                  unsigned long tmo_ms, u32 *raw_prd,
 107                                  u32 *raw_dty)
 108 {
 109         struct device *parent = priv->chip.dev->parent;
 110         enum stm32_timers_dmas dma_id;
 111         u32 ccen, ccr;
 112         int ret;
 113 
 114         /* Ensure registers have been updated, enable counter and capture */
 115         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 116         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
 117 
 118         /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
 119         dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
 120         ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
 121         ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
 122         regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
 123 
 124         /*
 125          * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
 126          * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
 127          * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
 128          * or { CCR3, CCR4 }, { CCR3, CCR4 }
 129          */
 130         ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
 131                                           2, tmo_ms);
 132         if (ret)
 133                 goto stop;
 134 
 135         /* Period: t2 - t0 (take care of counter overflow) */
 136         if (priv->capture[0] <= priv->capture[2])
 137                 *raw_prd = priv->capture[2] - priv->capture[0];
 138         else
 139                 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
 140 
 141         /* Duty cycle capture requires at least two capture units */
 142         if (pwm->chip->npwm < 2)
 143                 *raw_dty = 0;
 144         else if (priv->capture[0] <= priv->capture[3])
 145                 *raw_dty = priv->capture[3] - priv->capture[0];
 146         else
 147                 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
 148 
 149         if (*raw_dty > *raw_prd) {
 150                 /*
 151                  * Race beetween PWM input and DMA: it may happen
 152                  * falling edge triggers new capture on TI2/4 before DMA
 153                  * had a chance to read CCR2/4. It means capture[1]
 154                  * contains period + duty_cycle. So, subtract period.
 155                  */
 156                 *raw_dty -= *raw_prd;
 157         }
 158 
 159 stop:
 160         regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
 161         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 162 
 163         return ret;
 164 }
 165 
 166 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
 167                              struct pwm_capture *result, unsigned long tmo_ms)
 168 {
 169         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 170         unsigned long long prd, div, dty;
 171         unsigned long rate;
 172         unsigned int psc = 0, icpsc, scale;
 173         u32 raw_prd = 0, raw_dty = 0;
 174         int ret = 0;
 175 
 176         mutex_lock(&priv->lock);
 177 
 178         if (active_channels(priv)) {
 179                 ret = -EBUSY;
 180                 goto unlock;
 181         }
 182 
 183         ret = clk_enable(priv->clk);
 184         if (ret) {
 185                 dev_err(priv->chip.dev, "failed to enable counter clock\n");
 186                 goto unlock;
 187         }
 188 
 189         rate = clk_get_rate(priv->clk);
 190         if (!rate) {
 191                 ret = -EINVAL;
 192                 goto clk_dis;
 193         }
 194 
 195         /* prescaler: fit timeout window provided by upper layer */
 196         div = (unsigned long long)rate * (unsigned long long)tmo_ms;
 197         do_div(div, MSEC_PER_SEC);
 198         prd = div;
 199         while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
 200                 psc++;
 201                 div = prd;
 202                 do_div(div, psc + 1);
 203         }
 204         regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
 205         regmap_write(priv->regmap, TIM_PSC, psc);
 206 
 207         /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
 208         regmap_update_bits(priv->regmap,
 209                            pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
 210                            TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
 211                            TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
 212                            TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
 213 
 214         /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
 215         regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
 216                            TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
 217                            TIM_CCER_CC2P : TIM_CCER_CC4P);
 218 
 219         ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
 220         if (ret)
 221                 goto stop;
 222 
 223         /*
 224          * Got a capture. Try to improve accuracy at high rates:
 225          * - decrease counter clock prescaler, scale up to max rate.
 226          * - use input prescaler, capture once every /2 /4 or /8 edges.
 227          */
 228         if (raw_prd) {
 229                 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
 230 
 231                 scale = max_arr / min(max_arr, raw_prd);
 232         } else {
 233                 scale = priv->max_arr; /* bellow resolution, use max scale */
 234         }
 235 
 236         if (psc && scale > 1) {
 237                 /* 2nd measure with new scale */
 238                 psc /= scale;
 239                 regmap_write(priv->regmap, TIM_PSC, psc);
 240                 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
 241                                             &raw_dty);
 242                 if (ret)
 243                         goto stop;
 244         }
 245 
 246         /* Compute intermediate period not to exceed timeout at low rates */
 247         prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
 248         do_div(prd, rate);
 249 
 250         for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
 251                 /* input prescaler: also keep arbitrary margin */
 252                 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
 253                         break;
 254                 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
 255                         break;
 256         }
 257 
 258         if (!icpsc)
 259                 goto done;
 260 
 261         /* Last chance to improve period accuracy, using input prescaler */
 262         regmap_update_bits(priv->regmap,
 263                            pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
 264                            TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
 265                            FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
 266                            FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
 267 
 268         ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
 269         if (ret)
 270                 goto stop;
 271 
 272         if (raw_dty >= (raw_prd >> icpsc)) {
 273                 /*
 274                  * We may fall here using input prescaler, when input
 275                  * capture starts on high side (before falling edge).
 276                  * Example with icpsc to capture on each 4 events:
 277                  *
 278                  *       start   1st capture                     2nd capture
 279                  *         v     v                               v
 280                  *         ___   _____   _____   _____   _____   ____
 281                  * TI1..4     |__|    |__|    |__|    |__|    |__|
 282                  *            v  v    .  .    .  .    .       v  v
 283                  * icpsc1/3:  .  0    .  1    .  2    .  3    .  0
 284                  * icpsc2/4:  0       1       2       3       0
 285                  *            v  v                            v  v
 286                  * CCR1/3  ......t0..............................t2
 287                  * CCR2/4  ..t1..............................t1'...
 288                  *               .                            .  .
 289                  * Capture0:     .<----------------------------->.
 290                  * Capture1:     .<-------------------------->.  .
 291                  *               .                            .  .
 292                  * Period:       .<------>                    .  .
 293                  * Low side:                                  .<>.
 294                  *
 295                  * Result:
 296                  * - Period = Capture0 / icpsc
 297                  * - Duty = Period - Low side = Period - (Capture0 - Capture1)
 298                  */
 299                 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
 300         }
 301 
 302 done:
 303         prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
 304         result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
 305         dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
 306         result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
 307 stop:
 308         regmap_write(priv->regmap, TIM_CCER, 0);
 309         regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
 310         regmap_write(priv->regmap, TIM_PSC, 0);
 311 clk_dis:
 312         clk_disable(priv->clk);
 313 unlock:
 314         mutex_unlock(&priv->lock);
 315 
 316         return ret;
 317 }
 318 
 319 static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
 320                             int duty_ns, int period_ns)
 321 {
 322         unsigned long long prd, div, dty;
 323         unsigned int prescaler = 0;
 324         u32 ccmr, mask, shift;
 325 
 326         /* Period and prescaler values depends on clock rate */
 327         div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
 328 
 329         do_div(div, NSEC_PER_SEC);
 330         prd = div;
 331 
 332         while (div > priv->max_arr) {
 333                 prescaler++;
 334                 div = prd;
 335                 do_div(div, prescaler + 1);
 336         }
 337 
 338         prd = div;
 339 
 340         if (prescaler > MAX_TIM_PSC)
 341                 return -EINVAL;
 342 
 343         /*
 344          * All channels share the same prescaler and counter so when two
 345          * channels are active at the same time we can't change them
 346          */
 347         if (active_channels(priv) & ~(1 << ch * 4)) {
 348                 u32 psc, arr;
 349 
 350                 regmap_read(priv->regmap, TIM_PSC, &psc);
 351                 regmap_read(priv->regmap, TIM_ARR, &arr);
 352 
 353                 if ((psc != prescaler) || (arr != prd - 1))
 354                         return -EBUSY;
 355         }
 356 
 357         regmap_write(priv->regmap, TIM_PSC, prescaler);
 358         regmap_write(priv->regmap, TIM_ARR, prd - 1);
 359         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 360 
 361         /* Calculate the duty cycles */
 362         dty = prd * duty_ns;
 363         do_div(dty, period_ns);
 364 
 365         write_ccrx(priv, ch, dty);
 366 
 367         /* Configure output mode */
 368         shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
 369         ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
 370         mask = CCMR_CHANNEL_MASK << shift;
 371 
 372         if (ch < 2)
 373                 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
 374         else
 375                 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
 376 
 377         regmap_update_bits(priv->regmap, TIM_BDTR,
 378                            TIM_BDTR_MOE | TIM_BDTR_AOE,
 379                            TIM_BDTR_MOE | TIM_BDTR_AOE);
 380 
 381         return 0;
 382 }
 383 
 384 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
 385                                   enum pwm_polarity polarity)
 386 {
 387         u32 mask;
 388 
 389         mask = TIM_CCER_CC1P << (ch * 4);
 390         if (priv->have_complementary_output)
 391                 mask |= TIM_CCER_CC1NP << (ch * 4);
 392 
 393         regmap_update_bits(priv->regmap, TIM_CCER, mask,
 394                            polarity == PWM_POLARITY_NORMAL ? 0 : mask);
 395 
 396         return 0;
 397 }
 398 
 399 static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
 400 {
 401         u32 mask;
 402         int ret;
 403 
 404         ret = clk_enable(priv->clk);
 405         if (ret)
 406                 return ret;
 407 
 408         /* Enable channel */
 409         mask = TIM_CCER_CC1E << (ch * 4);
 410         if (priv->have_complementary_output)
 411                 mask |= TIM_CCER_CC1NE << (ch * 4);
 412 
 413         regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
 414 
 415         /* Make sure that registers are updated */
 416         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 417 
 418         /* Enable controller */
 419         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
 420 
 421         return 0;
 422 }
 423 
 424 static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
 425 {
 426         u32 mask;
 427 
 428         /* Disable channel */
 429         mask = TIM_CCER_CC1E << (ch * 4);
 430         if (priv->have_complementary_output)
 431                 mask |= TIM_CCER_CC1NE << (ch * 4);
 432 
 433         regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
 434 
 435         /* When all channels are disabled, we can disable the controller */
 436         if (!active_channels(priv))
 437                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 438 
 439         clk_disable(priv->clk);
 440 }
 441 
 442 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 443                            const struct pwm_state *state)
 444 {
 445         bool enabled;
 446         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 447         int ret;
 448 
 449         enabled = pwm->state.enabled;
 450 
 451         if (enabled && !state->enabled) {
 452                 stm32_pwm_disable(priv, pwm->hwpwm);
 453                 return 0;
 454         }
 455 
 456         if (state->polarity != pwm->state.polarity)
 457                 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
 458 
 459         ret = stm32_pwm_config(priv, pwm->hwpwm,
 460                                state->duty_cycle, state->period);
 461         if (ret)
 462                 return ret;
 463 
 464         if (!enabled && state->enabled)
 465                 ret = stm32_pwm_enable(priv, pwm->hwpwm);
 466 
 467         return ret;
 468 }
 469 
 470 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
 471                                   const struct pwm_state *state)
 472 {
 473         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 474         int ret;
 475 
 476         /* protect common prescaler for all active channels */
 477         mutex_lock(&priv->lock);
 478         ret = stm32_pwm_apply(chip, pwm, state);
 479         mutex_unlock(&priv->lock);
 480 
 481         return ret;
 482 }
 483 
 484 static const struct pwm_ops stm32pwm_ops = {
 485         .owner = THIS_MODULE,
 486         .apply = stm32_pwm_apply_locked,
 487         .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
 488 };
 489 
 490 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
 491                                     int index, int level, int filter)
 492 {
 493         u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;
 494         int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;
 495         u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF
 496                                 : TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F;
 497         u32 bdtr = bke;
 498 
 499         /*
 500          * The both bits could be set since only one will be wrote
 501          * due to mask value.
 502          */
 503         if (level)
 504                 bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P;
 505 
 506         bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift;
 507 
 508         regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
 509 
 510         regmap_read(priv->regmap, TIM_BDTR, &bdtr);
 511 
 512         return (bdtr & bke) ? 0 : -EINVAL;
 513 }
 514 
 515 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
 516                                        struct device_node *np)
 517 {
 518         struct stm32_breakinput breakinput[MAX_BREAKINPUT];
 519         int nb, ret, i, array_size;
 520 
 521         nb = of_property_count_elems_of_size(np, "st,breakinput",
 522                                              sizeof(struct stm32_breakinput));
 523 
 524         /*
 525          * Because "st,breakinput" parameter is optional do not make probe
 526          * failed if it doesn't exist.
 527          */
 528         if (nb <= 0)
 529                 return 0;
 530 
 531         if (nb > MAX_BREAKINPUT)
 532                 return -EINVAL;
 533 
 534         array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
 535         ret = of_property_read_u32_array(np, "st,breakinput",
 536                                          (u32 *)breakinput, array_size);
 537         if (ret)
 538                 return ret;
 539 
 540         for (i = 0; i < nb && !ret; i++) {
 541                 ret = stm32_pwm_set_breakinput(priv,
 542                                                breakinput[i].index,
 543                                                breakinput[i].level,
 544                                                breakinput[i].filter);
 545         }
 546 
 547         return ret;
 548 }
 549 
 550 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
 551 {
 552         u32 ccer;
 553 
 554         /*
 555          * If complementary bit doesn't exist writing 1 will have no
 556          * effect so we can detect it.
 557          */
 558         regmap_update_bits(priv->regmap,
 559                            TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
 560         regmap_read(priv->regmap, TIM_CCER, &ccer);
 561         regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
 562 
 563         priv->have_complementary_output = (ccer != 0);
 564 }
 565 
 566 static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
 567 {
 568         u32 ccer;
 569         int npwm = 0;
 570 
 571         /*
 572          * If channels enable bits don't exist writing 1 will have no
 573          * effect so we can detect and count them.
 574          */
 575         regmap_update_bits(priv->regmap,
 576                            TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
 577         regmap_read(priv->regmap, TIM_CCER, &ccer);
 578         regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
 579 
 580         if (ccer & TIM_CCER_CC1E)
 581                 npwm++;
 582 
 583         if (ccer & TIM_CCER_CC2E)
 584                 npwm++;
 585 
 586         if (ccer & TIM_CCER_CC3E)
 587                 npwm++;
 588 
 589         if (ccer & TIM_CCER_CC4E)
 590                 npwm++;
 591 
 592         return npwm;
 593 }
 594 
 595 static int stm32_pwm_probe(struct platform_device *pdev)
 596 {
 597         struct device *dev = &pdev->dev;
 598         struct device_node *np = dev->of_node;
 599         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 600         struct stm32_pwm *priv;
 601         int ret;
 602 
 603         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 604         if (!priv)
 605                 return -ENOMEM;
 606 
 607         mutex_init(&priv->lock);
 608         priv->regmap = ddata->regmap;
 609         priv->clk = ddata->clk;
 610         priv->max_arr = ddata->max_arr;
 611         priv->chip.of_xlate = of_pwm_xlate_with_flags;
 612         priv->chip.of_pwm_n_cells = 3;
 613 
 614         if (!priv->regmap || !priv->clk)
 615                 return -EINVAL;
 616 
 617         ret = stm32_pwm_apply_breakinputs(priv, np);
 618         if (ret)
 619                 return ret;
 620 
 621         stm32_pwm_detect_complementary(priv);
 622 
 623         priv->chip.base = -1;
 624         priv->chip.dev = dev;
 625         priv->chip.ops = &stm32pwm_ops;
 626         priv->chip.npwm = stm32_pwm_detect_channels(priv);
 627 
 628         ret = pwmchip_add(&priv->chip);
 629         if (ret < 0)
 630                 return ret;
 631 
 632         platform_set_drvdata(pdev, priv);
 633 
 634         return 0;
 635 }
 636 
 637 static int stm32_pwm_remove(struct platform_device *pdev)
 638 {
 639         struct stm32_pwm *priv = platform_get_drvdata(pdev);
 640         unsigned int i;
 641 
 642         for (i = 0; i < priv->chip.npwm; i++)
 643                 pwm_disable(&priv->chip.pwms[i]);
 644 
 645         pwmchip_remove(&priv->chip);
 646 
 647         return 0;
 648 }
 649 
 650 static const struct of_device_id stm32_pwm_of_match[] = {
 651         { .compatible = "st,stm32-pwm", },
 652         { /* end node */ },
 653 };
 654 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
 655 
 656 static struct platform_driver stm32_pwm_driver = {
 657         .probe  = stm32_pwm_probe,
 658         .remove = stm32_pwm_remove,
 659         .driver = {
 660                 .name = "stm32-pwm",
 661                 .of_match_table = stm32_pwm_of_match,
 662         },
 663 };
 664 module_platform_driver(stm32_pwm_driver);
 665 
 666 MODULE_ALIAS("platform:stm32-pwm");
 667 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
 668 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pwm/pwm-stm32.c

DEFINITIONS
