root/drivers/gpu/drm/v3d/v3d_drv.h

INCLUDED FROM

DEFINITIONS

1. to_v3d_dev
2. v3d_has_csd
3. to_v3d_bo
4. to_v3d_fence
5. nsecs_to_jiffies_timeout

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2015-2018 Broadcom */
   3 
   4 #include <linux/delay.h>
   5 #include <linux/mutex.h>
   6 #include <linux/spinlock_types.h>
   7 #include <linux/workqueue.h>
   8 
   9 #include <drm/drm_encoder.h>
  10 #include <drm/drm_gem.h>
  11 #include <drm/drm_gem_shmem_helper.h>
  12 #include <drm/gpu_scheduler.h>
  13 
  14 #include "uapi/drm/v3d_drm.h"
  15 
  16 struct clk;
  17 struct device;
  18 struct platform_device;
  19 struct reset_control;
  20 
  21 #define GMP_GRANULARITY (128 * 1024)
  22 
  23 /* Enum for each of the V3D queues. */
  24 enum v3d_queue {
  25         V3D_BIN,
  26         V3D_RENDER,
  27         V3D_TFU,
  28         V3D_CSD,
  29         V3D_CACHE_CLEAN,
  30 };
  31 
  32 #define V3D_MAX_QUEUES (V3D_CACHE_CLEAN + 1)
  33 
  34 struct v3d_queue_state {
  35         struct drm_gpu_scheduler sched;
  36 
  37         u64 fence_context;
  38         u64 emit_seqno;
  39 };
  40 
  41 struct v3d_dev {
  42         struct drm_device drm;
  43 
  44         /* Short representation (e.g. 33, 41) of the V3D tech version
  45          * and revision.
  46          */
  47         int ver;
  48         bool single_irq_line;
  49 
  50         struct device *dev;
  51         struct platform_device *pdev;
  52         void __iomem *hub_regs;
  53         void __iomem *core_regs[3];
  54         void __iomem *bridge_regs;
  55         void __iomem *gca_regs;
  56         struct clk *clk;
  57         struct reset_control *reset;
  58 
  59         /* Virtual and DMA addresses of the single shared page table. */
  60         volatile u32 *pt;
  61         dma_addr_t pt_paddr;
  62 
  63         /* Virtual and DMA addresses of the MMU's scratch page.  When
  64          * a read or write is invalid in the MMU, it will be
  65          * redirected here.
  66          */
  67         void *mmu_scratch;
  68         dma_addr_t mmu_scratch_paddr;
  69         /* virtual address bits from V3D to the MMU. */
  70         int va_width;
  71 
  72         /* Number of V3D cores. */
  73         u32 cores;
  74 
  75         /* Allocator managing the address space.  All units are in
  76          * number of pages.
  77          */
  78         struct drm_mm mm;
  79         spinlock_t mm_lock;
  80 
  81         struct work_struct overflow_mem_work;
  82 
  83         struct v3d_bin_job *bin_job;
  84         struct v3d_render_job *render_job;
  85         struct v3d_tfu_job *tfu_job;
  86         struct v3d_csd_job *csd_job;
  87 
  88         struct v3d_queue_state queue[V3D_MAX_QUEUES];
  89 
  90         /* Spinlock used to synchronize the overflow memory
  91          * management against bin job submission.
  92          */
  93         spinlock_t job_lock;
  94 
  95         /* Protects bo_stats */
  96         struct mutex bo_lock;
  97 
  98         /* Lock taken when resetting the GPU, to keep multiple
  99          * processes from trying to park the scheduler threads and
 100          * reset at once.
 101          */
 102         struct mutex reset_lock;
 103 
 104         /* Lock taken when creating and pushing the GPU scheduler
 105          * jobs, to keep the sched-fence seqnos in order.
 106          */
 107         struct mutex sched_lock;
 108 
 109         /* Lock taken during a cache clean and when initiating an L2
 110          * flush, to keep L2 flushes from interfering with the
 111          * synchronous L2 cleans.
 112          */
 113         struct mutex cache_clean_lock;
 114 
 115         struct {
 116                 u32 num_allocated;
 117                 u32 pages_allocated;
 118         } bo_stats;
 119 };
 120 
 121 static inline struct v3d_dev *
 122 to_v3d_dev(struct drm_device *dev)
 123 {
 124         return (struct v3d_dev *)dev->dev_private;
 125 }
 126 
 127 static inline bool
 128 v3d_has_csd(struct v3d_dev *v3d)
 129 {
 130         return v3d->ver >= 41;
 131 }
 132 
 133 /* The per-fd struct, which tracks the MMU mappings. */
 134 struct v3d_file_priv {
 135         struct v3d_dev *v3d;
 136 
 137         struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
 138 };
 139 
 140 struct v3d_bo {
 141         struct drm_gem_shmem_object base;
 142 
 143         struct drm_mm_node node;
 144 
 145         /* List entry for the BO's position in
 146          * v3d_render_job->unref_list
 147          */
 148         struct list_head unref_head;
 149 };
 150 
 151 static inline struct v3d_bo *
 152 to_v3d_bo(struct drm_gem_object *bo)
 153 {
 154         return (struct v3d_bo *)bo;
 155 }
 156 
 157 struct v3d_fence {
 158         struct dma_fence base;
 159         struct drm_device *dev;
 160         /* v3d seqno for signaled() test */
 161         u64 seqno;
 162         enum v3d_queue queue;
 163 };
 164 
 165 static inline struct v3d_fence *
 166 to_v3d_fence(struct dma_fence *fence)
 167 {
 168         return (struct v3d_fence *)fence;
 169 }
 170 
 171 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
 172 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
 173 
 174 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
 175 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
 176 
 177 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
 178 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
 179 
 180 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
 181 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
 182 
 183 struct v3d_job {
 184         struct drm_sched_job base;
 185 
 186         struct kref refcount;
 187 
 188         struct v3d_dev *v3d;
 189 
 190         /* This is the array of BOs that were looked up at the start
 191          * of submission.
 192          */
 193         struct drm_gem_object **bo;
 194         u32 bo_count;
 195 
 196         /* Array of struct dma_fence * to block on before submitting this job.
 197          */
 198         struct xarray deps;
 199         unsigned long last_dep;
 200 
 201         /* v3d fence to be signaled by IRQ handler when the job is complete. */
 202         struct dma_fence *irq_fence;
 203 
 204         /* scheduler fence for when the job is considered complete and
 205          * the BO reservations can be released.
 206          */
 207         struct dma_fence *done_fence;
 208 
 209         /* Callback for the freeing of the job on refcount going to 0. */
 210         void (*free)(struct kref *ref);
 211 };
 212 
 213 struct v3d_bin_job {
 214         struct v3d_job base;
 215 
 216         /* GPU virtual addresses of the start/end of the CL job. */
 217         u32 start, end;
 218 
 219         u32 timedout_ctca, timedout_ctra;
 220 
 221         /* Corresponding render job, for attaching our overflow memory. */
 222         struct v3d_render_job *render;
 223 
 224         /* Submitted tile memory allocation start/size, tile state. */
 225         u32 qma, qms, qts;
 226 };
 227 
 228 struct v3d_render_job {
 229         struct v3d_job base;
 230 
 231         /* GPU virtual addresses of the start/end of the CL job. */
 232         u32 start, end;
 233 
 234         u32 timedout_ctca, timedout_ctra;
 235 
 236         /* List of overflow BOs used in the job that need to be
 237          * released once the job is complete.
 238          */
 239         struct list_head unref_list;
 240 };
 241 
 242 struct v3d_tfu_job {
 243         struct v3d_job base;
 244 
 245         struct drm_v3d_submit_tfu args;
 246 };
 247 
 248 struct v3d_csd_job {
 249         struct v3d_job base;
 250 
 251         u32 timedout_batches;
 252 
 253         struct drm_v3d_submit_csd args;
 254 };
 255 
 256 /**
 257  * _wait_for - magic (register) wait macro
 258  *
 259  * Does the right thing for modeset paths when run under kdgb or similar atomic
 260  * contexts. Note that it's important that we check the condition again after
 261  * having timed out, since the timeout could be due to preemption or similar and
 262  * we've never had a chance to check the condition before the timeout.
 263  */
 264 #define wait_for(COND, MS) ({ \
 265         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
 266         int ret__ = 0;                                                  \
 267         while (!(COND)) {                                               \
 268                 if (time_after(jiffies, timeout__)) {                   \
 269                         if (!(COND))                                    \
 270                                 ret__ = -ETIMEDOUT;                     \
 271                         break;                                          \
 272                 }                                                       \
 273                 msleep(1);                                      \
 274         }                                                               \
 275         ret__;                                                          \
 276 })
 277 
 278 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
 279 {
 280         /* nsecs_to_jiffies64() does not guard against overflow */
 281         if (NSEC_PER_SEC % HZ &&
 282             div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
 283                 return MAX_JIFFY_OFFSET;
 284 
 285         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
 286 }
 287 
 288 /* v3d_bo.c */
 289 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
 290 void v3d_free_object(struct drm_gem_object *gem_obj);
 291 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
 292                              size_t size);
 293 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
 294                         struct drm_file *file_priv);
 295 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
 296                       struct drm_file *file_priv);
 297 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
 298                             struct drm_file *file_priv);
 299 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
 300                                                  struct dma_buf_attachment *attach,
 301                                                  struct sg_table *sgt);
 302 
 303 /* v3d_debugfs.c */
 304 int v3d_debugfs_init(struct drm_minor *minor);
 305 
 306 /* v3d_fence.c */
 307 extern const struct dma_fence_ops v3d_fence_ops;
 308 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
 309 
 310 /* v3d_gem.c */
 311 int v3d_gem_init(struct drm_device *dev);
 312 void v3d_gem_destroy(struct drm_device *dev);
 313 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
 314                         struct drm_file *file_priv);
 315 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
 316                          struct drm_file *file_priv);
 317 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
 318                          struct drm_file *file_priv);
 319 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
 320                       struct drm_file *file_priv);
 321 void v3d_job_put(struct v3d_job *job);
 322 void v3d_reset(struct v3d_dev *v3d);
 323 void v3d_invalidate_caches(struct v3d_dev *v3d);
 324 void v3d_clean_caches(struct v3d_dev *v3d);
 325 
 326 /* v3d_irq.c */
 327 int v3d_irq_init(struct v3d_dev *v3d);
 328 void v3d_irq_enable(struct v3d_dev *v3d);
 329 void v3d_irq_disable(struct v3d_dev *v3d);
 330 void v3d_irq_reset(struct v3d_dev *v3d);
 331 
 332 /* v3d_mmu.c */
 333 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
 334                        u32 *offset);
 335 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
 336 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
 337 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
 338 
 339 /* v3d_sched.c */
 340 int v3d_sched_init(struct v3d_dev *v3d);
 341 void v3d_sched_fini(struct v3d_dev *v3d);