drivers/gpu/drm/nouveau/nouveau

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This source file includes following definitions.
nouveau_pci_name
nouveau_platform_name
nouveau_name
nouveau_cli_work_ready
nouveau_cli_work
nouveau_cli_work_fence
nouveau_cli_work_queue
nouveau_cli_fini
nouveau_cli_init
nouveau_accel_ce_fini
nouveau_accel_ce_init
nouveau_accel_gr_fini
nouveau_accel_gr_init
nouveau_accel_fini
nouveau_accel_init
nouveau_drm_device_init
nouveau_drm_device_fini
quirk_broken_nv_runpm
nouveau_drm_probe
nouveau_drm_device_remove
nouveau_drm_remove
nouveau_do_suspend
nouveau_do_resume
nouveau_pmops_suspend
nouveau_pmops_resume
nouveau_pmops_freeze
nouveau_pmops_thaw
nouveau_pmops_runtime
nouveau_pmops_runtime_suspend
nouveau_pmops_runtime_resume
nouveau_pmops_runtime_idle
nouveau_drm_open
nouveau_drm_postclose
nouveau_drm_ioctl
nouveau_display_options
nouveau_platform_device_create
nouveau_drm_init
nouveau_drm_exit
   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vga_switcheroo.h>
  31 #include <linux/mmu_notifier.h>
  32 
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_ioctl.h>
  35 #include <drm/drm_vblank.h>
  36 
  37 #include <core/gpuobj.h>
  38 #include <core/option.h>
  39 #include <core/pci.h>
  40 #include <core/tegra.h>
  41 
  42 #include <nvif/driver.h>
  43 #include <nvif/fifo.h>
  44 #include <nvif/user.h>
  45 
  46 #include <nvif/class.h>
  47 #include <nvif/cl0002.h>
  48 #include <nvif/cla06f.h>
  49 
  50 #include "nouveau_drv.h"
  51 #include "nouveau_dma.h"
  52 #include "nouveau_ttm.h"
  53 #include "nouveau_gem.h"
  54 #include "nouveau_vga.h"
  55 #include "nouveau_led.h"
  56 #include "nouveau_hwmon.h"
  57 #include "nouveau_acpi.h"
  58 #include "nouveau_bios.h"
  59 #include "nouveau_ioctl.h"
  60 #include "nouveau_abi16.h"
  61 #include "nouveau_fbcon.h"
  62 #include "nouveau_fence.h"
  63 #include "nouveau_debugfs.h"
  64 #include "nouveau_usif.h"
  65 #include "nouveau_connector.h"
  66 #include "nouveau_platform.h"
  67 #include "nouveau_svm.h"
  68 #include "nouveau_dmem.h"
  69 
  70 MODULE_PARM_DESC(config, "option string to pass to driver core");
  71 static char *nouveau_config;
  72 module_param_named(config, nouveau_config, charp, 0400);
  73 
  74 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  75 static char *nouveau_debug;
  76 module_param_named(debug, nouveau_debug, charp, 0400);
  77 
  78 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  79 static int nouveau_noaccel = 0;
  80 module_param_named(noaccel, nouveau_noaccel, int, 0400);
  81 
  82 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
  83                           "0 = disabled, 1 = enabled, 2 = headless)");
  84 int nouveau_modeset = -1;
  85 module_param_named(modeset, nouveau_modeset, int, 0400);
  86 
  87 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
  88 static int nouveau_atomic = 0;
  89 module_param_named(atomic, nouveau_atomic, int, 0400);
  90 
  91 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
  92 static int nouveau_runtime_pm = -1;
  93 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
  94 
  95 static struct drm_driver driver_stub;
  96 static struct drm_driver driver_pci;
  97 static struct drm_driver driver_platform;
  98 
  99 static u64
 100 nouveau_pci_name(struct pci_dev *pdev)
 101 {
 102         u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
 103         name |= pdev->bus->number << 16;
 104         name |= PCI_SLOT(pdev->devfn) << 8;
 105         return name | PCI_FUNC(pdev->devfn);
 106 }
 107 
 108 static u64
 109 nouveau_platform_name(struct platform_device *platformdev)
 110 {
 111         return platformdev->id;
 112 }
 113 
 114 static u64
 115 nouveau_name(struct drm_device *dev)
 116 {
 117         if (dev->pdev)
 118                 return nouveau_pci_name(dev->pdev);
 119         else
 120                 return nouveau_platform_name(to_platform_device(dev->dev));
 121 }
 122 
 123 static inline bool
 124 nouveau_cli_work_ready(struct dma_fence *fence)
 125 {
 126         if (!dma_fence_is_signaled(fence))
 127                 return false;
 128         dma_fence_put(fence);
 129         return true;
 130 }
 131 
 132 static void
 133 nouveau_cli_work(struct work_struct *w)
 134 {
 135         struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
 136         struct nouveau_cli_work *work, *wtmp;
 137         mutex_lock(&cli->lock);
 138         list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
 139                 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
 140                         list_del(&work->head);
 141                         work->func(work);
 142                 }
 143         }
 144         mutex_unlock(&cli->lock);
 145 }
 146 
 147 static void
 148 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
 149 {
 150         struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
 151         schedule_work(&work->cli->work);
 152 }
 153 
 154 void
 155 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
 156                        struct nouveau_cli_work *work)
 157 {
 158         work->fence = dma_fence_get(fence);
 159         work->cli = cli;
 160         mutex_lock(&cli->lock);
 161         list_add_tail(&work->head, &cli->worker);
 162         if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
 163                 nouveau_cli_work_fence(fence, &work->cb);
 164         mutex_unlock(&cli->lock);
 165 }
 166 
 167 static void
 168 nouveau_cli_fini(struct nouveau_cli *cli)
 169 {
 170         /* All our channels are dead now, which means all the fences they
 171          * own are signalled, and all callback functions have been called.
 172          *
 173          * So, after flushing the workqueue, there should be nothing left.
 174          */
 175         flush_work(&cli->work);
 176         WARN_ON(!list_empty(&cli->worker));
 177 
 178         usif_client_fini(cli);
 179         nouveau_vmm_fini(&cli->svm);
 180         nouveau_vmm_fini(&cli->vmm);
 181         nvif_mmu_fini(&cli->mmu);
 182         nvif_device_fini(&cli->device);
 183         mutex_lock(&cli->drm->master.lock);
 184         nvif_client_fini(&cli->base);
 185         mutex_unlock(&cli->drm->master.lock);
 186 }
 187 
 188 static int
 189 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
 190                  struct nouveau_cli *cli)
 191 {
 192         static const struct nvif_mclass
 193         mems[] = {
 194                 { NVIF_CLASS_MEM_GF100, -1 },
 195                 { NVIF_CLASS_MEM_NV50 , -1 },
 196                 { NVIF_CLASS_MEM_NV04 , -1 },
 197                 {}
 198         };
 199         static const struct nvif_mclass
 200         mmus[] = {
 201                 { NVIF_CLASS_MMU_GF100, -1 },
 202                 { NVIF_CLASS_MMU_NV50 , -1 },
 203                 { NVIF_CLASS_MMU_NV04 , -1 },
 204                 {}
 205         };
 206         static const struct nvif_mclass
 207         vmms[] = {
 208                 { NVIF_CLASS_VMM_GP100, -1 },
 209                 { NVIF_CLASS_VMM_GM200, -1 },
 210                 { NVIF_CLASS_VMM_GF100, -1 },
 211                 { NVIF_CLASS_VMM_NV50 , -1 },
 212                 { NVIF_CLASS_VMM_NV04 , -1 },
 213                 {}
 214         };
 215         u64 device = nouveau_name(drm->dev);
 216         int ret;
 217 
 218         snprintf(cli->name, sizeof(cli->name), "%s", sname);
 219         cli->drm = drm;
 220         mutex_init(&cli->mutex);
 221         usif_client_init(cli);
 222 
 223         INIT_WORK(&cli->work, nouveau_cli_work);
 224         INIT_LIST_HEAD(&cli->worker);
 225         mutex_init(&cli->lock);
 226 
 227         if (cli == &drm->master) {
 228                 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
 229                                        cli->name, device, &cli->base);
 230         } else {
 231                 mutex_lock(&drm->master.lock);
 232                 ret = nvif_client_init(&drm->master.base, cli->name, device,
 233                                        &cli->base);
 234                 mutex_unlock(&drm->master.lock);
 235         }
 236         if (ret) {
 237                 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
 238                 goto done;
 239         }
 240 
 241         ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
 242                                &(struct nv_device_v0) {
 243                                         .device = ~0,
 244                                }, sizeof(struct nv_device_v0),
 245                                &cli->device);
 246         if (ret) {
 247                 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
 248                 goto done;
 249         }
 250 
 251         ret = nvif_mclass(&cli->device.object, mmus);
 252         if (ret < 0) {
 253                 NV_PRINTK(err, cli, "No supported MMU class\n");
 254                 goto done;
 255         }
 256 
 257         ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
 258         if (ret) {
 259                 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
 260                 goto done;
 261         }
 262 
 263         ret = nvif_mclass(&cli->mmu.object, vmms);
 264         if (ret < 0) {
 265                 NV_PRINTK(err, cli, "No supported VMM class\n");
 266                 goto done;
 267         }
 268 
 269         ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
 270         if (ret) {
 271                 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
 272                 goto done;
 273         }
 274 
 275         ret = nvif_mclass(&cli->mmu.object, mems);
 276         if (ret < 0) {
 277                 NV_PRINTK(err, cli, "No supported MEM class\n");
 278                 goto done;
 279         }
 280 
 281         cli->mem = &mems[ret];
 282         return 0;
 283 done:
 284         if (ret)
 285                 nouveau_cli_fini(cli);
 286         return ret;
 287 }
 288 
 289 static void
 290 nouveau_accel_ce_fini(struct nouveau_drm *drm)
 291 {
 292         nouveau_channel_idle(drm->cechan);
 293         nvif_object_fini(&drm->ttm.copy);
 294         nouveau_channel_del(&drm->cechan);
 295 }
 296 
 297 static void
 298 nouveau_accel_ce_init(struct nouveau_drm *drm)
 299 {
 300         struct nvif_device *device = &drm->client.device;
 301         int ret = 0;
 302 
 303         /* Allocate channel that has access to a (preferably async) copy
 304          * engine, to use for TTM buffer moves.
 305          */
 306         if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
 307                 ret = nouveau_channel_new(drm, device,
 308                                           nvif_fifo_runlist_ce(device), 0,
 309                                           true, &drm->cechan);
 310         } else
 311         if (device->info.chipset >= 0xa3 &&
 312             device->info.chipset != 0xaa &&
 313             device->info.chipset != 0xac) {
 314                 /* Prior to Kepler, there's only a single runlist, so all
 315                  * engines can be accessed from any channel.
 316                  *
 317                  * We still want to use a separate channel though.
 318                  */
 319                 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
 320                                           &drm->cechan);
 321         }
 322 
 323         if (ret)
 324                 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
 325 }
 326 
 327 static void
 328 nouveau_accel_gr_fini(struct nouveau_drm *drm)
 329 {
 330         nouveau_channel_idle(drm->channel);
 331         nvif_object_fini(&drm->ntfy);
 332         nvkm_gpuobj_del(&drm->notify);
 333         nvif_object_fini(&drm->nvsw);
 334         nouveau_channel_del(&drm->channel);
 335 }
 336 
 337 static void
 338 nouveau_accel_gr_init(struct nouveau_drm *drm)
 339 {
 340         struct nvif_device *device = &drm->client.device;
 341         u32 arg0, arg1;
 342         int ret;
 343 
 344         /* Allocate channel that has access to the graphics engine. */
 345         if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
 346                 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
 347                 arg1 = 1;
 348         } else {
 349                 arg0 = NvDmaFB;
 350                 arg1 = NvDmaTT;
 351         }
 352 
 353         ret = nouveau_channel_new(drm, device, arg0, arg1, false,
 354                                   &drm->channel);
 355         if (ret) {
 356                 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
 357                 nouveau_accel_gr_fini(drm);
 358                 return;
 359         }
 360 
 361         /* A SW class is used on pre-NV50 HW to assist with handling the
 362          * synchronisation of page flips, as well as to implement fences
 363          * on TNT/TNT2 HW that lacks any kind of support in host.
 364          */
 365         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 366                 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
 367                                        nouveau_abi16_swclass(drm), NULL, 0,
 368                                        &drm->nvsw);
 369                 if (ret == 0) {
 370                         ret = RING_SPACE(drm->channel, 2);
 371                         if (ret == 0) {
 372                                 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
 373                                 OUT_RING  (drm->channel, drm->nvsw.handle);
 374                         }
 375                 }
 376 
 377                 if (ret) {
 378                         NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
 379                         nouveau_accel_gr_fini(drm);
 380                         return;
 381                 }
 382         }
 383 
 384         /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
 385          * even if notification is never requested, so, allocate a ctxdma on
 386          * any GPU where it's possible we'll end up using M2MF for BO moves.
 387          */
 388         if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
 389                 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
 390                                       &drm->notify);
 391                 if (ret) {
 392                         NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
 393                         nouveau_accel_gr_fini(drm);
 394                         return;
 395                 }
 396 
 397                 ret = nvif_object_init(&drm->channel->user, NvNotify0,
 398                                        NV_DMA_IN_MEMORY,
 399                                        &(struct nv_dma_v0) {
 400                                                 .target = NV_DMA_V0_TARGET_VRAM,
 401                                                 .access = NV_DMA_V0_ACCESS_RDWR,
 402                                                 .start = drm->notify->addr,
 403                                                 .limit = drm->notify->addr + 31
 404                                        }, sizeof(struct nv_dma_v0),
 405                                        &drm->ntfy);
 406                 if (ret) {
 407                         nouveau_accel_gr_fini(drm);
 408                         return;
 409                 }
 410         }
 411 }
 412 
 413 static void
 414 nouveau_accel_fini(struct nouveau_drm *drm)
 415 {
 416         nouveau_accel_ce_fini(drm);
 417         nouveau_accel_gr_fini(drm);
 418         if (drm->fence)
 419                 nouveau_fence(drm)->dtor(drm);
 420 }
 421 
 422 static void
 423 nouveau_accel_init(struct nouveau_drm *drm)
 424 {
 425         struct nvif_device *device = &drm->client.device;
 426         struct nvif_sclass *sclass;
 427         int ret, i, n;
 428 
 429         if (nouveau_noaccel)
 430                 return;
 431 
 432         /* Initialise global support for channels, and synchronisation. */
 433         ret = nouveau_channels_init(drm);
 434         if (ret)
 435                 return;
 436 
 437         /*XXX: this is crap, but the fence/channel stuff is a little
 438          *     backwards in some places.  this will be fixed.
 439          */
 440         ret = n = nvif_object_sclass_get(&device->object, &sclass);
 441         if (ret < 0)
 442                 return;
 443 
 444         for (ret = -ENOSYS, i = 0; i < n; i++) {
 445                 switch (sclass[i].oclass) {
 446                 case NV03_CHANNEL_DMA:
 447                         ret = nv04_fence_create(drm);
 448                         break;
 449                 case NV10_CHANNEL_DMA:
 450                         ret = nv10_fence_create(drm);
 451                         break;
 452                 case NV17_CHANNEL_DMA:
 453                 case NV40_CHANNEL_DMA:
 454                         ret = nv17_fence_create(drm);
 455                         break;
 456                 case NV50_CHANNEL_GPFIFO:
 457                         ret = nv50_fence_create(drm);
 458                         break;
 459                 case G82_CHANNEL_GPFIFO:
 460                         ret = nv84_fence_create(drm);
 461                         break;
 462                 case FERMI_CHANNEL_GPFIFO:
 463                 case KEPLER_CHANNEL_GPFIFO_A:
 464                 case KEPLER_CHANNEL_GPFIFO_B:
 465                 case MAXWELL_CHANNEL_GPFIFO_A:
 466                 case PASCAL_CHANNEL_GPFIFO_A:
 467                 case VOLTA_CHANNEL_GPFIFO_A:
 468                 case TURING_CHANNEL_GPFIFO_A:
 469                         ret = nvc0_fence_create(drm);
 470                         break;
 471                 default:
 472                         break;
 473                 }
 474         }
 475 
 476         nvif_object_sclass_put(&sclass);
 477         if (ret) {
 478                 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
 479                 nouveau_accel_fini(drm);
 480                 return;
 481         }
 482 
 483         /* Volta requires access to a doorbell register for kickoff. */
 484         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
 485                 ret = nvif_user_init(device);
 486                 if (ret)
 487                         return;
 488         }
 489 
 490         /* Allocate channels we need to support various functions. */
 491         nouveau_accel_gr_init(drm);
 492         nouveau_accel_ce_init(drm);
 493 
 494         /* Initialise accelerated TTM buffer moves. */
 495         nouveau_bo_move_init(drm);
 496 }
 497 
 498 static int
 499 nouveau_drm_device_init(struct drm_device *dev)
 500 {
 501         struct nouveau_drm *drm;
 502         int ret;
 503 
 504         if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
 505                 return -ENOMEM;
 506         dev->dev_private = drm;
 507         drm->dev = dev;
 508 
 509         ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
 510         if (ret)
 511                 goto fail_alloc;
 512 
 513         ret = nouveau_cli_init(drm, "DRM", &drm->client);
 514         if (ret)
 515                 goto fail_master;
 516 
 517         dev->irq_enabled = true;
 518 
 519         nvxx_client(&drm->client.base)->debug =
 520                 nvkm_dbgopt(nouveau_debug, "DRM");
 521 
 522         INIT_LIST_HEAD(&drm->clients);
 523         spin_lock_init(&drm->tile.lock);
 524 
 525         /* workaround an odd issue on nvc1 by disabling the device's
 526          * nosnoop capability.  hopefully won't cause issues until a
 527          * better fix is found - assuming there is one...
 528          */
 529         if (drm->client.device.info.chipset == 0xc1)
 530                 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
 531 
 532         nouveau_vga_init(drm);
 533 
 534         ret = nouveau_ttm_init(drm);
 535         if (ret)
 536                 goto fail_ttm;
 537 
 538         ret = nouveau_bios_init(dev);
 539         if (ret)
 540                 goto fail_bios;
 541 
 542         nouveau_accel_init(drm);
 543 
 544         ret = nouveau_display_create(dev);
 545         if (ret)
 546                 goto fail_dispctor;
 547 
 548         if (dev->mode_config.num_crtc) {
 549                 ret = nouveau_display_init(dev, false, false);
 550                 if (ret)
 551                         goto fail_dispinit;
 552         }
 553 
 554         nouveau_debugfs_init(drm);
 555         nouveau_hwmon_init(dev);
 556         nouveau_svm_init(drm);
 557         nouveau_dmem_init(drm);
 558         nouveau_fbcon_init(dev);
 559         nouveau_led_init(dev);
 560 
 561         if (nouveau_pmops_runtime()) {
 562                 pm_runtime_use_autosuspend(dev->dev);
 563                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 564                 pm_runtime_set_active(dev->dev);
 565                 pm_runtime_allow(dev->dev);
 566                 pm_runtime_mark_last_busy(dev->dev);
 567                 pm_runtime_put(dev->dev);
 568         }
 569 
 570         return 0;
 571 
 572 fail_dispinit:
 573         nouveau_display_destroy(dev);
 574 fail_dispctor:
 575         nouveau_accel_fini(drm);
 576         nouveau_bios_takedown(dev);
 577 fail_bios:
 578         nouveau_ttm_fini(drm);
 579 fail_ttm:
 580         nouveau_vga_fini(drm);
 581         nouveau_cli_fini(&drm->client);
 582 fail_master:
 583         nouveau_cli_fini(&drm->master);
 584 fail_alloc:
 585         kfree(drm);
 586         return ret;
 587 }
 588 
 589 static void
 590 nouveau_drm_device_fini(struct drm_device *dev)
 591 {
 592         struct nouveau_drm *drm = nouveau_drm(dev);
 593 
 594         if (nouveau_pmops_runtime()) {
 595                 pm_runtime_get_sync(dev->dev);
 596                 pm_runtime_forbid(dev->dev);
 597         }
 598 
 599         nouveau_led_fini(dev);
 600         nouveau_fbcon_fini(dev);
 601         nouveau_dmem_fini(drm);
 602         nouveau_svm_fini(drm);
 603         nouveau_hwmon_fini(dev);
 604         nouveau_debugfs_fini(drm);
 605 
 606         if (dev->mode_config.num_crtc)
 607                 nouveau_display_fini(dev, false, false);
 608         nouveau_display_destroy(dev);
 609 
 610         nouveau_accel_fini(drm);
 611         nouveau_bios_takedown(dev);
 612 
 613         nouveau_ttm_fini(drm);
 614         nouveau_vga_fini(drm);
 615 
 616         nouveau_cli_fini(&drm->client);
 617         nouveau_cli_fini(&drm->master);
 618         kfree(drm);
 619 }
 620 
 621 /*
 622  * On some Intel PCIe bridge controllers doing a
 623  * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
 624  * Skipping the intermediate D3hot step seems to make it work again. This is
 625  * probably caused by not meeting the expectation the involved AML code has
 626  * when the GPU is put into D3hot state before invoking it.
 627  *
 628  * This leads to various manifestations of this issue:
 629  *  - AML code execution to power on the GPU hits an infinite loop (as the
 630  *    code waits on device memory to change).
 631  *  - kernel crashes, as all PCI reads return -1, which most code isn't able
 632  *    to handle well enough.
 633  *
 634  * In all cases dmesg will contain at least one line like this:
 635  * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
 636  * followed by a lot of nouveau timeouts.
 637  *
 638  * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
 639  * documented PCI config space register 0x248 of the Intel PCIe bridge
 640  * controller (0x1901) in order to change the state of the PCIe link between
 641  * the PCIe port and the GPU. There are alternative code paths using other
 642  * registers, which seem to work fine (executed pre Windows 8):
 643  *  - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
 644  *  - 0xb0 bit 0x10 (link disable)
 645  * Changing the conditions inside the firmware by poking into the relevant
 646  * addresses does resolve the issue, but it seemed to be ACPI private memory
 647  * and not any device accessible memory at all, so there is no portable way of
 648  * changing the conditions.
 649  * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
 650  *
 651  * The only systems where this behavior can be seen are hybrid graphics laptops
 652  * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
 653  * this issue only occurs in combination with listed Intel PCIe bridge
 654  * controllers and the mentioned GPUs or other devices as well.
 655  *
 656  * documentation on the PCIe bridge controller can be found in the
 657  * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
 658  * Section "12 PCI Express* Controller (x16) Registers"
 659  */
 660 
 661 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
 662 {
 663         struct drm_device *dev = pci_get_drvdata(pdev);
 664         struct nouveau_drm *drm = nouveau_drm(dev);
 665         struct pci_dev *bridge = pci_upstream_bridge(pdev);
 666 
 667         if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
 668                 return;
 669 
 670         switch (bridge->device) {
 671         case 0x1901:
 672                 drm->old_pm_cap = pdev->pm_cap;
 673                 pdev->pm_cap = 0;
 674                 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
 675                 break;
 676         }
 677 }
 678 
 679 static int nouveau_drm_probe(struct pci_dev *pdev,
 680                              const struct pci_device_id *pent)
 681 {
 682         struct nvkm_device *device;
 683         struct drm_device *drm_dev;
 684         struct apertures_struct *aper;
 685         bool boot = false;
 686         int ret;
 687 
 688         if (vga_switcheroo_client_probe_defer(pdev))
 689                 return -EPROBE_DEFER;
 690 
 691         /* We need to check that the chipset is supported before booting
 692          * fbdev off the hardware, as there's no way to put it back.
 693          */
 694         ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
 695                                   true, false, 0, &device);
 696         if (ret)
 697                 return ret;
 698 
 699         nvkm_device_del(&device);
 700 
 701         /* Remove conflicting drivers (vesafb, efifb etc). */
 702         aper = alloc_apertures(3);
 703         if (!aper)
 704                 return -ENOMEM;
 705 
 706         aper->ranges[0].base = pci_resource_start(pdev, 1);
 707         aper->ranges[0].size = pci_resource_len(pdev, 1);
 708         aper->count = 1;
 709 
 710         if (pci_resource_len(pdev, 2)) {
 711                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 712                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 713                 aper->count++;
 714         }
 715 
 716         if (pci_resource_len(pdev, 3)) {
 717                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 718                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 719                 aper->count++;
 720         }
 721 
 722 #ifdef CONFIG_X86
 723         boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 724 #endif
 725         if (nouveau_modeset != 2)
 726                 drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
 727         kfree(aper);
 728 
 729         ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
 730                                   true, true, ~0ULL, &device);
 731         if (ret)
 732                 return ret;
 733 
 734         pci_set_master(pdev);
 735 
 736         if (nouveau_atomic)
 737                 driver_pci.driver_features |= DRIVER_ATOMIC;
 738 
 739         drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
 740         if (IS_ERR(drm_dev)) {
 741                 ret = PTR_ERR(drm_dev);
 742                 goto fail_nvkm;
 743         }
 744 
 745         ret = pci_enable_device(pdev);
 746         if (ret)
 747                 goto fail_drm;
 748 
 749         drm_dev->pdev = pdev;
 750         pci_set_drvdata(pdev, drm_dev);
 751 
 752         ret = nouveau_drm_device_init(drm_dev);
 753         if (ret)
 754                 goto fail_pci;
 755 
 756         ret = drm_dev_register(drm_dev, pent->driver_data);
 757         if (ret)
 758                 goto fail_drm_dev_init;
 759 
 760         quirk_broken_nv_runpm(pdev);
 761         return 0;
 762 
 763 fail_drm_dev_init:
 764         nouveau_drm_device_fini(drm_dev);
 765 fail_pci:
 766         pci_disable_device(pdev);
 767 fail_drm:
 768         drm_dev_put(drm_dev);
 769 fail_nvkm:
 770         nvkm_device_del(&device);
 771         return ret;
 772 }
 773 
 774 void
 775 nouveau_drm_device_remove(struct drm_device *dev)
 776 {
 777         struct pci_dev *pdev = dev->pdev;
 778         struct nouveau_drm *drm = nouveau_drm(dev);
 779         struct nvkm_client *client;
 780         struct nvkm_device *device;
 781 
 782         drm_dev_unregister(dev);
 783 
 784         dev->irq_enabled = false;
 785         client = nvxx_client(&drm->client.base);
 786         device = nvkm_device_find(client->device);
 787 
 788         nouveau_drm_device_fini(dev);
 789         pci_disable_device(pdev);
 790         drm_dev_put(dev);
 791         nvkm_device_del(&device);
 792 }
 793 
 794 static void
 795 nouveau_drm_remove(struct pci_dev *pdev)
 796 {
 797         struct drm_device *dev = pci_get_drvdata(pdev);
 798         struct nouveau_drm *drm = nouveau_drm(dev);
 799 
 800         /* revert our workaround */
 801         if (drm->old_pm_cap)
 802                 pdev->pm_cap = drm->old_pm_cap;
 803         nouveau_drm_device_remove(dev);
 804 }
 805 
 806 static int
 807 nouveau_do_suspend(struct drm_device *dev, bool runtime)
 808 {
 809         struct nouveau_drm *drm = nouveau_drm(dev);
 810         int ret;
 811 
 812         nouveau_svm_suspend(drm);
 813         nouveau_dmem_suspend(drm);
 814         nouveau_led_suspend(dev);
 815 
 816         if (dev->mode_config.num_crtc) {
 817                 NV_DEBUG(drm, "suspending console...\n");
 818                 nouveau_fbcon_set_suspend(dev, 1);
 819                 NV_DEBUG(drm, "suspending display...\n");
 820                 ret = nouveau_display_suspend(dev, runtime);
 821                 if (ret)
 822                         return ret;
 823         }
 824 
 825         NV_DEBUG(drm, "evicting buffers...\n");
 826         ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
 827 
 828         NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
 829         if (drm->cechan) {
 830                 ret = nouveau_channel_idle(drm->cechan);
 831                 if (ret)
 832                         goto fail_display;
 833         }
 834 
 835         if (drm->channel) {
 836                 ret = nouveau_channel_idle(drm->channel);
 837                 if (ret)
 838                         goto fail_display;
 839         }
 840 
 841         NV_DEBUG(drm, "suspending fence...\n");
 842         if (drm->fence && nouveau_fence(drm)->suspend) {
 843                 if (!nouveau_fence(drm)->suspend(drm)) {
 844                         ret = -ENOMEM;
 845                         goto fail_display;
 846                 }
 847         }
 848 
 849         NV_DEBUG(drm, "suspending object tree...\n");
 850         ret = nvif_client_suspend(&drm->master.base);
 851         if (ret)
 852                 goto fail_client;
 853 
 854         return 0;
 855 
 856 fail_client:
 857         if (drm->fence && nouveau_fence(drm)->resume)
 858                 nouveau_fence(drm)->resume(drm);
 859 
 860 fail_display:
 861         if (dev->mode_config.num_crtc) {
 862                 NV_DEBUG(drm, "resuming display...\n");
 863                 nouveau_display_resume(dev, runtime);
 864         }
 865         return ret;
 866 }
 867 
 868 static int
 869 nouveau_do_resume(struct drm_device *dev, bool runtime)
 870 {
 871         int ret = 0;
 872         struct nouveau_drm *drm = nouveau_drm(dev);
 873 
 874         NV_DEBUG(drm, "resuming object tree...\n");
 875         ret = nvif_client_resume(&drm->master.base);
 876         if (ret) {
 877                 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
 878                 return ret;
 879         }
 880 
 881         NV_DEBUG(drm, "resuming fence...\n");
 882         if (drm->fence && nouveau_fence(drm)->resume)
 883                 nouveau_fence(drm)->resume(drm);
 884 
 885         nouveau_run_vbios_init(dev);
 886 
 887         if (dev->mode_config.num_crtc) {
 888                 NV_DEBUG(drm, "resuming display...\n");
 889                 nouveau_display_resume(dev, runtime);
 890                 NV_DEBUG(drm, "resuming console...\n");
 891                 nouveau_fbcon_set_suspend(dev, 0);
 892         }
 893 
 894         nouveau_led_resume(dev);
 895         nouveau_dmem_resume(drm);
 896         nouveau_svm_resume(drm);
 897         return 0;
 898 }
 899 
 900 int
 901 nouveau_pmops_suspend(struct device *dev)
 902 {
 903         struct pci_dev *pdev = to_pci_dev(dev);
 904         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 905         int ret;
 906 
 907         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
 908             drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
 909                 return 0;
 910 
 911         ret = nouveau_do_suspend(drm_dev, false);
 912         if (ret)
 913                 return ret;
 914 
 915         pci_save_state(pdev);
 916         pci_disable_device(pdev);
 917         pci_set_power_state(pdev, PCI_D3hot);
 918         udelay(200);
 919         return 0;
 920 }
 921 
 922 int
 923 nouveau_pmops_resume(struct device *dev)
 924 {
 925         struct pci_dev *pdev = to_pci_dev(dev);
 926         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 927         int ret;
 928 
 929         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
 930             drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
 931                 return 0;
 932 
 933         pci_set_power_state(pdev, PCI_D0);
 934         pci_restore_state(pdev);
 935         ret = pci_enable_device(pdev);
 936         if (ret)
 937                 return ret;
 938         pci_set_master(pdev);
 939 
 940         ret = nouveau_do_resume(drm_dev, false);
 941 
 942         /* Monitors may have been connected / disconnected during suspend */
 943         schedule_work(&nouveau_drm(drm_dev)->hpd_work);
 944 
 945         return ret;
 946 }
 947 
 948 static int
 949 nouveau_pmops_freeze(struct device *dev)
 950 {
 951         struct pci_dev *pdev = to_pci_dev(dev);
 952         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 953         return nouveau_do_suspend(drm_dev, false);
 954 }
 955 
 956 static int
 957 nouveau_pmops_thaw(struct device *dev)
 958 {
 959         struct pci_dev *pdev = to_pci_dev(dev);
 960         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 961         return nouveau_do_resume(drm_dev, false);
 962 }
 963 
 964 bool
 965 nouveau_pmops_runtime(void)
 966 {
 967         if (nouveau_runtime_pm == -1)
 968                 return nouveau_is_optimus() || nouveau_is_v1_dsm();
 969         return nouveau_runtime_pm == 1;
 970 }
 971 
 972 static int
 973 nouveau_pmops_runtime_suspend(struct device *dev)
 974 {
 975         struct pci_dev *pdev = to_pci_dev(dev);
 976         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 977         int ret;
 978 
 979         if (!nouveau_pmops_runtime()) {
 980                 pm_runtime_forbid(dev);
 981                 return -EBUSY;
 982         }
 983 
 984         nouveau_switcheroo_optimus_dsm();
 985         ret = nouveau_do_suspend(drm_dev, true);
 986         pci_save_state(pdev);
 987         pci_disable_device(pdev);
 988         pci_ignore_hotplug(pdev);
 989         pci_set_power_state(pdev, PCI_D3cold);
 990         drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
 991         return ret;
 992 }
 993 
 994 static int
 995 nouveau_pmops_runtime_resume(struct device *dev)
 996 {
 997         struct pci_dev *pdev = to_pci_dev(dev);
 998         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 999         struct nouveau_drm *drm = nouveau_drm(drm_dev);
1000         struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1001         int ret;
1002 
1003         if (!nouveau_pmops_runtime()) {
1004                 pm_runtime_forbid(dev);
1005                 return -EBUSY;
1006         }
1007 
1008         pci_set_power_state(pdev, PCI_D0);
1009         pci_restore_state(pdev);
1010         ret = pci_enable_device(pdev);
1011         if (ret)
1012                 return ret;
1013         pci_set_master(pdev);
1014 
1015         ret = nouveau_do_resume(drm_dev, true);
1016         if (ret) {
1017                 NV_ERROR(drm, "resume failed with: %d\n", ret);
1018                 return ret;
1019         }
1020 
1021         /* do magic */
1022         nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1023         drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1024 
1025         /* Monitors may have been connected / disconnected during suspend */
1026         schedule_work(&nouveau_drm(drm_dev)->hpd_work);
1027 
1028         return ret;
1029 }
1030 
1031 static int
1032 nouveau_pmops_runtime_idle(struct device *dev)
1033 {
1034         if (!nouveau_pmops_runtime()) {
1035                 pm_runtime_forbid(dev);
1036                 return -EBUSY;
1037         }
1038 
1039         pm_runtime_mark_last_busy(dev);
1040         pm_runtime_autosuspend(dev);
1041         /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1042         return 1;
1043 }
1044 
1045 static int
1046 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1047 {
1048         struct nouveau_drm *drm = nouveau_drm(dev);
1049         struct nouveau_cli *cli;
1050         char name[32], tmpname[TASK_COMM_LEN];
1051         int ret;
1052 
1053         /* need to bring up power immediately if opening device */
1054         ret = pm_runtime_get_sync(dev->dev);
1055         if (ret < 0 && ret != -EACCES)
1056                 return ret;
1057 
1058         get_task_comm(tmpname, current);
1059         snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1060 
1061         if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1062                 ret = -ENOMEM;
1063                 goto done;
1064         }
1065 
1066         ret = nouveau_cli_init(drm, name, cli);
1067         if (ret)
1068                 goto done;
1069 
1070         cli->base.super = false;
1071 
1072         fpriv->driver_priv = cli;
1073 
1074         mutex_lock(&drm->client.mutex);
1075         list_add(&cli->head, &drm->clients);
1076         mutex_unlock(&drm->client.mutex);
1077 
1078 done:
1079         if (ret && cli) {
1080                 nouveau_cli_fini(cli);
1081                 kfree(cli);
1082         }
1083 
1084         pm_runtime_mark_last_busy(dev->dev);
1085         pm_runtime_put_autosuspend(dev->dev);
1086         return ret;
1087 }
1088 
1089 static void
1090 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1091 {
1092         struct nouveau_cli *cli = nouveau_cli(fpriv);
1093         struct nouveau_drm *drm = nouveau_drm(dev);
1094 
1095         pm_runtime_get_sync(dev->dev);
1096 
1097         mutex_lock(&cli->mutex);
1098         if (cli->abi16)
1099                 nouveau_abi16_fini(cli->abi16);
1100         mutex_unlock(&cli->mutex);
1101 
1102         mutex_lock(&drm->client.mutex);
1103         list_del(&cli->head);
1104         mutex_unlock(&drm->client.mutex);
1105 
1106         nouveau_cli_fini(cli);
1107         kfree(cli);
1108         pm_runtime_mark_last_busy(dev->dev);
1109         pm_runtime_put_autosuspend(dev->dev);
1110 }
1111 
1112 static const struct drm_ioctl_desc
1113 nouveau_ioctls[] = {
1114         DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1115         DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1116         DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1117         DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1118         DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1119         DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1120         DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1121         DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1122         DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1123         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1124         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1125         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1126         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1127         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1128 };
1129 
1130 long
1131 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1132 {
1133         struct drm_file *filp = file->private_data;
1134         struct drm_device *dev = filp->minor->dev;
1135         long ret;
1136 
1137         ret = pm_runtime_get_sync(dev->dev);
1138         if (ret < 0 && ret != -EACCES)
1139                 return ret;
1140 
1141         switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1142         case DRM_NOUVEAU_NVIF:
1143                 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1144                 break;
1145         default:
1146                 ret = drm_ioctl(file, cmd, arg);
1147                 break;
1148         }
1149 
1150         pm_runtime_mark_last_busy(dev->dev);
1151         pm_runtime_put_autosuspend(dev->dev);
1152         return ret;
1153 }
1154 
1155 static const struct file_operations
1156 nouveau_driver_fops = {
1157         .owner = THIS_MODULE,
1158         .open = drm_open,
1159         .release = drm_release,
1160         .unlocked_ioctl = nouveau_drm_ioctl,
1161         .mmap = nouveau_ttm_mmap,
1162         .poll = drm_poll,
1163         .read = drm_read,
1164 #if defined(CONFIG_COMPAT)
1165         .compat_ioctl = nouveau_compat_ioctl,
1166 #endif
1167         .llseek = noop_llseek,
1168 };
1169 
1170 static struct drm_driver
1171 driver_stub = {
1172         .driver_features =
1173                 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1174 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1175                 | DRIVER_KMS_LEGACY_CONTEXT
1176 #endif
1177                 ,
1178 
1179         .open = nouveau_drm_open,
1180         .postclose = nouveau_drm_postclose,
1181         .lastclose = nouveau_vga_lastclose,
1182 
1183 #if defined(CONFIG_DEBUG_FS)
1184         .debugfs_init = nouveau_drm_debugfs_init,
1185 #endif
1186 
1187         .enable_vblank = nouveau_display_vblank_enable,
1188         .disable_vblank = nouveau_display_vblank_disable,
1189         .get_scanout_position = nouveau_display_scanoutpos,
1190         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1191 
1192         .ioctls = nouveau_ioctls,
1193         .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1194         .fops = &nouveau_driver_fops,
1195 
1196         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1197         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1198         .gem_prime_pin = nouveau_gem_prime_pin,
1199         .gem_prime_unpin = nouveau_gem_prime_unpin,
1200         .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1201         .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1202         .gem_prime_vmap = nouveau_gem_prime_vmap,
1203         .gem_prime_vunmap = nouveau_gem_prime_vunmap,
1204 
1205         .gem_free_object_unlocked = nouveau_gem_object_del,
1206         .gem_open_object = nouveau_gem_object_open,
1207         .gem_close_object = nouveau_gem_object_close,
1208 
1209         .dumb_create = nouveau_display_dumb_create,
1210         .dumb_map_offset = nouveau_display_dumb_map_offset,
1211 
1212         .name = DRIVER_NAME,
1213         .desc = DRIVER_DESC,
1214 #ifdef GIT_REVISION
1215         .date = GIT_REVISION,
1216 #else
1217         .date = DRIVER_DATE,
1218 #endif
1219         .major = DRIVER_MAJOR,
1220         .minor = DRIVER_MINOR,
1221         .patchlevel = DRIVER_PATCHLEVEL,
1222 };
1223 
1224 static struct pci_device_id
1225 nouveau_drm_pci_table[] = {
1226         {
1227                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1228                 .class = PCI_BASE_CLASS_DISPLAY << 16,
1229                 .class_mask  = 0xff << 16,
1230         },
1231         {
1232                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1233                 .class = PCI_BASE_CLASS_DISPLAY << 16,
1234                 .class_mask  = 0xff << 16,
1235         },
1236         {}
1237 };
1238 
1239 static void nouveau_display_options(void)
1240 {
1241         DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1242 
1243         DRM_DEBUG_DRIVER("... tv_disable   : %d\n", nouveau_tv_disable);
1244         DRM_DEBUG_DRIVER("... ignorelid    : %d\n", nouveau_ignorelid);
1245         DRM_DEBUG_DRIVER("... duallink     : %d\n", nouveau_duallink);
1246         DRM_DEBUG_DRIVER("... nofbaccel    : %d\n", nouveau_nofbaccel);
1247         DRM_DEBUG_DRIVER("... config       : %s\n", nouveau_config);
1248         DRM_DEBUG_DRIVER("... debug        : %s\n", nouveau_debug);
1249         DRM_DEBUG_DRIVER("... noaccel      : %d\n", nouveau_noaccel);
1250         DRM_DEBUG_DRIVER("... modeset      : %d\n", nouveau_modeset);
1251         DRM_DEBUG_DRIVER("... runpm        : %d\n", nouveau_runtime_pm);
1252         DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1253         DRM_DEBUG_DRIVER("... hdmimhz      : %d\n", nouveau_hdmimhz);
1254 }
1255 
1256 static const struct dev_pm_ops nouveau_pm_ops = {
1257         .suspend = nouveau_pmops_suspend,
1258         .resume = nouveau_pmops_resume,
1259         .freeze = nouveau_pmops_freeze,
1260         .thaw = nouveau_pmops_thaw,
1261         .poweroff = nouveau_pmops_freeze,
1262         .restore = nouveau_pmops_resume,
1263         .runtime_suspend = nouveau_pmops_runtime_suspend,
1264         .runtime_resume = nouveau_pmops_runtime_resume,
1265         .runtime_idle = nouveau_pmops_runtime_idle,
1266 };
1267 
1268 static struct pci_driver
1269 nouveau_drm_pci_driver = {
1270         .name = "nouveau",
1271         .id_table = nouveau_drm_pci_table,
1272         .probe = nouveau_drm_probe,
1273         .remove = nouveau_drm_remove,
1274         .driver.pm = &nouveau_pm_ops,
1275 };
1276 
1277 struct drm_device *
1278 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1279                                struct platform_device *pdev,
1280                                struct nvkm_device **pdevice)
1281 {
1282         struct drm_device *drm;
1283         int err;
1284 
1285         err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1286                                     true, true, ~0ULL, pdevice);
1287         if (err)
1288                 goto err_free;
1289 
1290         drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1291         if (IS_ERR(drm)) {
1292                 err = PTR_ERR(drm);
1293                 goto err_free;
1294         }
1295 
1296         err = nouveau_drm_device_init(drm);
1297         if (err)
1298                 goto err_put;
1299 
1300         platform_set_drvdata(pdev, drm);
1301 
1302         return drm;
1303 
1304 err_put:
1305         drm_dev_put(drm);
1306 err_free:
1307         nvkm_device_del(pdevice);
1308 
1309         return ERR_PTR(err);
1310 }
1311 
1312 static int __init
1313 nouveau_drm_init(void)
1314 {
1315         driver_pci = driver_stub;
1316         driver_platform = driver_stub;
1317 
1318         nouveau_display_options();
1319 
1320         if (nouveau_modeset == -1) {
1321                 if (vgacon_text_force())
1322                         nouveau_modeset = 0;
1323         }
1324 
1325         if (!nouveau_modeset)
1326                 return 0;
1327 
1328 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1329         platform_driver_register(&nouveau_platform_driver);
1330 #endif
1331 
1332         nouveau_register_dsm_handler();
1333         nouveau_backlight_ctor();
1334 
1335 #ifdef CONFIG_PCI
1336         return pci_register_driver(&nouveau_drm_pci_driver);
1337 #else
1338         return 0;
1339 #endif
1340 }
1341 
1342 static void __exit
1343 nouveau_drm_exit(void)
1344 {
1345         if (!nouveau_modeset)
1346                 return;
1347 
1348 #ifdef CONFIG_PCI
1349         pci_unregister_driver(&nouveau_drm_pci_driver);
1350 #endif
1351         nouveau_backlight_dtor();
1352         nouveau_unregister_dsm_handler();
1353 
1354 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1355         platform_driver_unregister(&nouveau_platform_driver);
1356 #endif
1357         if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1358                 mmu_notifier_synchronize();
1359 }
1360 
1361 module_init(nouveau_drm_init);
1362 module_exit(nouveau_drm_exit);
1363 
1364 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1365 MODULE_AUTHOR(DRIVER_AUTHOR);
1366 MODULE_DESCRIPTION(DRIVER_DESC);
1367 MODULE_LICENSE("GPL and additional rights");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/nouveau/nouveau_drm.c

DEFINITIONS
