root/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c

DEFINITIONS

1. acr_r370_generate_flcn_bl_desc
2. acr_r370_generate_sec2_bl_desc
3. acr_r370_generate_hs_bl_desc
4. acr_r370_new

   1 /*
   2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #include "acr_r370.h"
  24 #include "acr_r367.h"
  25 
  26 #include <core/msgqueue.h>
  27 #include <engine/falcon.h>
  28 #include <engine/sec2.h>
  29 
  30 static void
  31 acr_r370_generate_flcn_bl_desc(const struct nvkm_acr *acr,
  32                                const struct ls_ucode_img *img, u64 wpr_addr,
  33                                void *_desc)
  34 {
  35         struct acr_r370_flcn_bl_desc *desc = _desc;
  36         const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
  37         u64 base, addr_code, addr_data;
  38 
  39         base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
  40         addr_code = base + pdesc->app_resident_code_offset;
  41         addr_data = base + pdesc->app_resident_data_offset;
  42 
  43         desc->ctx_dma = FALCON_DMAIDX_UCODE;
  44         desc->code_dma_base = u64_to_flcn64(addr_code);
  45         desc->non_sec_code_off = pdesc->app_resident_code_offset;
  46         desc->non_sec_code_size = pdesc->app_resident_code_size;
  47         desc->code_entry_point = pdesc->app_imem_entry;
  48         desc->data_dma_base = u64_to_flcn64(addr_data);
  49         desc->data_size = pdesc->app_resident_data_size;
  50 }
  51 
  52 static const struct acr_r352_lsf_func
  53 acr_r370_ls_fecs_func_0 = {
  54         .generate_bl_desc = acr_r370_generate_flcn_bl_desc,
  55         .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
  56 };
  57 
  58 const struct acr_r352_ls_func
  59 acr_r370_ls_fecs_func = {
  60         .load = acr_ls_ucode_load_fecs,
  61         .version_max = 0,
  62         .version = {
  63                 &acr_r370_ls_fecs_func_0,
  64         }
  65 };
  66 
  67 static const struct acr_r352_lsf_func
  68 acr_r370_ls_gpccs_func_0 = {
  69         .generate_bl_desc = acr_r370_generate_flcn_bl_desc,
  70         .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
  71         /* GPCCS will be loaded using PRI */
  72         .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD,
  73 };
  74 
  75 const struct acr_r352_ls_func
  76 acr_r370_ls_gpccs_func = {
  77         .load = acr_ls_ucode_load_gpccs,
  78         .version_max = 0,
  79         .version = {
  80                 &acr_r370_ls_gpccs_func_0,
  81         }
  82 };
  83 
  84 static void
  85 acr_r370_generate_sec2_bl_desc(const struct nvkm_acr *acr,
  86                                const struct ls_ucode_img *img, u64 wpr_addr,
  87                                void *_desc)
  88 {
  89         const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
  90         const struct nvkm_sec2 *sec = acr->subdev->device->sec2;
  91         struct acr_r370_flcn_bl_desc *desc = _desc;
  92         u64 base, addr_code, addr_data;
  93         u32 addr_args;
  94 
  95         base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
  96         /* For some reason we should not add app_resident_code_offset here */
  97         addr_code = base;
  98         addr_data = base + pdesc->app_resident_data_offset;
  99         addr_args = sec->falcon->data.limit;
 100         addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
 101 
 102         desc->ctx_dma = FALCON_SEC2_DMAIDX_UCODE;
 103         desc->code_dma_base = u64_to_flcn64(addr_code);
 104         desc->non_sec_code_off = pdesc->app_resident_code_offset;
 105         desc->non_sec_code_size = pdesc->app_resident_code_size;
 106         desc->code_entry_point = pdesc->app_imem_entry;
 107         desc->data_dma_base = u64_to_flcn64(addr_data);
 108         desc->data_size = pdesc->app_resident_data_size;
 109         desc->argc = 1;
 110         /* args are stored at the beginning of EMEM */
 111         desc->argv = 0x01000000;
 112 }
 113 
 114 const struct acr_r352_lsf_func
 115 acr_r370_ls_sec2_func_0 = {
 116         .generate_bl_desc = acr_r370_generate_sec2_bl_desc,
 117         .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
 118 };
 119 
 120 const struct acr_r352_ls_func
 121 acr_r370_ls_sec2_func = {
 122         .load = acr_ls_ucode_load_sec2,
 123         .post_run = acr_ls_sec2_post_run,
 124         .version_max = 0,
 125         .version = {
 126                 &acr_r370_ls_sec2_func_0,
 127         }
 128 };
 129 
 130 void
 131 acr_r370_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
 132                              u64 offset)
 133 {
 134         struct acr_r370_flcn_bl_desc *bl_desc = _bl_desc;
 135 
 136         bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
 137         bl_desc->non_sec_code_off = hdr->non_sec_code_off;
 138         bl_desc->non_sec_code_size = hdr->non_sec_code_size;
 139         bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
 140         bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
 141         bl_desc->code_entry_point = 0;
 142         bl_desc->code_dma_base = u64_to_flcn64(offset);
 143         bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base);
 144         bl_desc->data_size = hdr->data_size;
 145 }
 146 
 147 const struct acr_r352_func
 148 acr_r370_func = {
 149         .fixup_hs_desc = acr_r367_fixup_hs_desc,
 150         .generate_hs_bl_desc = acr_r370_generate_hs_bl_desc,
 151         .hs_bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
 152         .shadow_blob = true,
 153         .ls_ucode_img_load = acr_r367_ls_ucode_img_load,
 154         .ls_fill_headers = acr_r367_ls_fill_headers,
 155         .ls_write_wpr = acr_r367_ls_write_wpr,
 156         .ls_func = {
 157                 [NVKM_SECBOOT_FALCON_SEC2] = &acr_r370_ls_sec2_func,
 158                 [NVKM_SECBOOT_FALCON_FECS] = &acr_r370_ls_fecs_func,
 159                 [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r370_ls_gpccs_func,
 160         },
 161 };
 162 
 163 struct nvkm_acr *
 164 acr_r370_new(enum nvkm_secboot_falcon boot_falcon,
 165              unsigned long managed_falcons)
 166 {
 167         return acr_r352_new_(&acr_r370_func, boot_falcon, managed_falcons);
 168 }