root/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c

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DEFINITIONS

This source file includes following definitions.
  1. gm200_fifo_pbdma_nr
  2. gm200_fifo_new

   1 /*
   2  * Copyright 2015 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "gk104.h"
  25 #include "changk104.h"
  26 
  27 #include <nvif/class.h>
  28 
  29 int
  30 gm200_fifo_pbdma_nr(struct gk104_fifo *fifo)
  31 {
  32         struct nvkm_device *device = fifo->base.engine.subdev.device;
  33         return nvkm_rd32(device, 0x002004) & 0x000000ff;
  34 }
  35 
  36 const struct gk104_fifo_pbdma_func
  37 gm200_fifo_pbdma = {
  38         .nr = gm200_fifo_pbdma_nr,
  39         .init = gk104_fifo_pbdma_init,
  40         .init_timeout = gk208_fifo_pbdma_init_timeout,
  41 };
  42 
  43 static const struct gk104_fifo_func
  44 gm200_fifo = {
  45         .intr.fault = gm107_fifo_intr_fault,
  46         .pbdma = &gm200_fifo_pbdma,
  47         .fault.access = gk104_fifo_fault_access,
  48         .fault.engine = gm107_fifo_fault_engine,
  49         .fault.reason = gk104_fifo_fault_reason,
  50         .fault.hubclient = gk104_fifo_fault_hubclient,
  51         .fault.gpcclient = gk104_fifo_fault_gpcclient,
  52         .runlist = &gm107_fifo_runlist,
  53         .chan = {{0,0,MAXWELL_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new },
  54 };
  55 
  56 int
  57 gm200_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
  58 {
  59         return gk104_fifo_new_(&gm200_fifo, device, index, 4096, pfifo);
  60 }

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