This source file includes following definitions.
- mtk_mipi_tx_from_clk_hw
- mtk_mipi_tx_clear_bits
- mtk_mipi_tx_set_bits
- mtk_mipi_tx_update_bits
- mtk_mipi_tx_pll_prepare
- mtk_mipi_tx_pll_unprepare
- mtk_mipi_tx_pll_round_rate
- mtk_mipi_tx_pll_set_rate
- mtk_mipi_tx_pll_recalc_rate
- mtk_mipi_tx_power_on_signal
- mtk_mipi_tx_power_on
- mtk_mipi_tx_power_off_signal
- mtk_mipi_tx_power_off
- mtk_mipi_tx_probe
- mtk_mipi_tx_remove
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6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy/phy.h>
14
15 #define MIPITX_DSI_CON 0x00
16 #define RG_DSI_LDOCORE_EN BIT(0)
17 #define RG_DSI_CKG_LDOOUT_EN BIT(1)
18 #define RG_DSI_BCLK_SEL (3 << 2)
19 #define RG_DSI_LD_IDX_SEL (7 << 4)
20 #define RG_DSI_PHYCLK_SEL (2 << 8)
21 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
22 #define RG_DSI_LPTX_CLMP_EN BIT(11)
23
24 #define MIPITX_DSI_CLOCK_LANE 0x04
25 #define MIPITX_DSI_DATA_LANE0 0x08
26 #define MIPITX_DSI_DATA_LANE1 0x0c
27 #define MIPITX_DSI_DATA_LANE2 0x10
28 #define MIPITX_DSI_DATA_LANE3 0x14
29 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)
30 #define RG_DSI_LNTx_CKLANE_EN BIT(1)
31 #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
32 #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
33 #define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
34 #define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
35 #define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
36 #define RG_DSI_LNTx_RT_CODE (0xf << 8)
37
38 #define MIPITX_DSI_TOP_CON 0x40
39 #define RG_DSI_LNT_INTR_EN BIT(0)
40 #define RG_DSI_LNT_HS_BIAS_EN BIT(1)
41 #define RG_DSI_LNT_IMP_CAL_EN BIT(2)
42 #define RG_DSI_LNT_TESTMODE_EN BIT(3)
43 #define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
44 #define RG_DSI_LNT_AIO_SEL (7 << 8)
45 #define RG_DSI_PAD_TIE_LOW_EN BIT(11)
46 #define RG_DSI_DEBUG_INPUT_EN BIT(12)
47 #define RG_DSI_PRESERVE (7 << 13)
48
49 #define MIPITX_DSI_BG_CON 0x44
50 #define RG_DSI_BG_CORE_EN BIT(0)
51 #define RG_DSI_BG_CKEN BIT(1)
52 #define RG_DSI_BG_DIV (0x3 << 2)
53 #define RG_DSI_BG_FAST_CHARGE BIT(4)
54 #define RG_DSI_VOUT_MSK (0x3ffff << 5)
55 #define RG_DSI_V12_SEL (7 << 5)
56 #define RG_DSI_V10_SEL (7 << 8)
57 #define RG_DSI_V072_SEL (7 << 11)
58 #define RG_DSI_V04_SEL (7 << 14)
59 #define RG_DSI_V032_SEL (7 << 17)
60 #define RG_DSI_V02_SEL (7 << 20)
61 #define RG_DSI_BG_R1_TRIM (0xf << 24)
62 #define RG_DSI_BG_R2_TRIM (0xf << 28)
63
64 #define MIPITX_DSI_PLL_CON0 0x50
65 #define RG_DSI_MPPLL_PLL_EN BIT(0)
66 #define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
67 #define RG_DSI_MPPLL_PREDIV (3 << 1)
68 #define RG_DSI_MPPLL_TXDIV0 (3 << 3)
69 #define RG_DSI_MPPLL_TXDIV1 (3 << 5)
70 #define RG_DSI_MPPLL_POSDIV (7 << 7)
71 #define RG_DSI_MPPLL_MONVC_EN BIT(10)
72 #define RG_DSI_MPPLL_MONREF_EN BIT(11)
73 #define RG_DSI_MPPLL_VOD_EN BIT(12)
74
75 #define MIPITX_DSI_PLL_CON1 0x54
76 #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
77 #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
78 #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
79 #define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
80
81 #define MIPITX_DSI_PLL_CON2 0x58
82
83 #define MIPITX_DSI_PLL_TOP 0x64
84 #define RG_DSI_MPPLL_PRESERVE (0xff << 8)
85
86 #define MIPITX_DSI_PLL_PWR 0x68
87 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
88 #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
89 #define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
90
91 #define MIPITX_DSI_SW_CTRL 0x80
92 #define SW_CTRL_EN BIT(0)
93
94 #define MIPITX_DSI_SW_CTRL_CON0 0x84
95 #define SW_LNTC_LPTX_PRE_OE BIT(0)
96 #define SW_LNTC_LPTX_OE BIT(1)
97 #define SW_LNTC_LPTX_P BIT(2)
98 #define SW_LNTC_LPTX_N BIT(3)
99 #define SW_LNTC_HSTX_PRE_OE BIT(4)
100 #define SW_LNTC_HSTX_OE BIT(5)
101 #define SW_LNTC_HSTX_ZEROCLK BIT(6)
102 #define SW_LNT0_LPTX_PRE_OE BIT(7)
103 #define SW_LNT0_LPTX_OE BIT(8)
104 #define SW_LNT0_LPTX_P BIT(9)
105 #define SW_LNT0_LPTX_N BIT(10)
106 #define SW_LNT0_HSTX_PRE_OE BIT(11)
107 #define SW_LNT0_HSTX_OE BIT(12)
108 #define SW_LNT0_LPRX_EN BIT(13)
109 #define SW_LNT1_LPTX_PRE_OE BIT(14)
110 #define SW_LNT1_LPTX_OE BIT(15)
111 #define SW_LNT1_LPTX_P BIT(16)
112 #define SW_LNT1_LPTX_N BIT(17)
113 #define SW_LNT1_HSTX_PRE_OE BIT(18)
114 #define SW_LNT1_HSTX_OE BIT(19)
115 #define SW_LNT2_LPTX_PRE_OE BIT(20)
116 #define SW_LNT2_LPTX_OE BIT(21)
117 #define SW_LNT2_LPTX_P BIT(22)
118 #define SW_LNT2_LPTX_N BIT(23)
119 #define SW_LNT2_HSTX_PRE_OE BIT(24)
120 #define SW_LNT2_HSTX_OE BIT(25)
121
122 struct mtk_mipitx_data {
123 const u32 mppll_preserve;
124 };
125
126 struct mtk_mipi_tx {
127 struct device *dev;
128 void __iomem *regs;
129 u32 data_rate;
130 const struct mtk_mipitx_data *driver_data;
131 struct clk_hw pll_hw;
132 struct clk *pll;
133 };
134
135 static inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
136 {
137 return container_of(hw, struct mtk_mipi_tx, pll_hw);
138 }
139
140 static void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
141 u32 bits)
142 {
143 u32 temp = readl(mipi_tx->regs + offset);
144
145 writel(temp & ~bits, mipi_tx->regs + offset);
146 }
147
148 static void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
149 u32 bits)
150 {
151 u32 temp = readl(mipi_tx->regs + offset);
152
153 writel(temp | bits, mipi_tx->regs + offset);
154 }
155
156 static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
157 u32 mask, u32 data)
158 {
159 u32 temp = readl(mipi_tx->regs + offset);
160
161 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
162 }
163
164 static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
165 {
166 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
167 u8 txdiv, txdiv0, txdiv1;
168 u64 pcw;
169
170 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
171
172 if (mipi_tx->data_rate >= 500000000) {
173 txdiv = 1;
174 txdiv0 = 0;
175 txdiv1 = 0;
176 } else if (mipi_tx->data_rate >= 250000000) {
177 txdiv = 2;
178 txdiv0 = 1;
179 txdiv1 = 0;
180 } else if (mipi_tx->data_rate >= 125000000) {
181 txdiv = 4;
182 txdiv0 = 2;
183 txdiv1 = 0;
184 } else if (mipi_tx->data_rate > 62000000) {
185 txdiv = 8;
186 txdiv0 = 2;
187 txdiv1 = 1;
188 } else if (mipi_tx->data_rate >= 50000000) {
189 txdiv = 16;
190 txdiv0 = 2;
191 txdiv1 = 2;
192 } else {
193 return -EINVAL;
194 }
195
196 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
197 RG_DSI_VOUT_MSK |
198 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
199 (4 << 20) | (4 << 17) | (4 << 14) |
200 (4 << 11) | (4 << 8) | (4 << 5) |
201 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
202
203 usleep_range(30, 100);
204
205 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
206 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
207 (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
208
209 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
210 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
211
212 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
213 RG_DSI_MPPLL_SDM_PWR_ON |
214 RG_DSI_MPPLL_SDM_ISO_EN,
215 RG_DSI_MPPLL_SDM_PWR_ON);
216
217 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
218 RG_DSI_MPPLL_PLL_EN);
219
220 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
221 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
222 RG_DSI_MPPLL_PREDIV,
223 (txdiv0 << 3) | (txdiv1 << 5));
224
225
226
227
228
229
230
231
232
233 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
234 26000000);
235 writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
236
237 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
238 RG_DSI_MPPLL_SDM_FRA_EN);
239
240 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
241
242 usleep_range(20, 100);
243
244 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
245 RG_DSI_MPPLL_SDM_SSC_EN);
246
247 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
248 RG_DSI_MPPLL_PRESERVE,
249 mipi_tx->driver_data->mppll_preserve);
250
251 return 0;
252 }
253
254 static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
255 {
256 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
257
258 dev_dbg(mipi_tx->dev, "unprepare\n");
259
260 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
261 RG_DSI_MPPLL_PLL_EN);
262
263 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
264 RG_DSI_MPPLL_PRESERVE, 0);
265
266 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
267 RG_DSI_MPPLL_SDM_ISO_EN |
268 RG_DSI_MPPLL_SDM_PWR_ON,
269 RG_DSI_MPPLL_SDM_ISO_EN);
270
271 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
272 RG_DSI_LNT_HS_BIAS_EN);
273
274 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
275 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
276
277 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
278 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
279
280 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
281 RG_DSI_MPPLL_DIV_MSK);
282 }
283
284 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
285 unsigned long *prate)
286 {
287 return clamp_val(rate, 50000000, 1250000000);
288 }
289
290 static int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
291 unsigned long parent_rate)
292 {
293 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
294
295 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
296
297 mipi_tx->data_rate = rate;
298
299 return 0;
300 }
301
302 static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
303 unsigned long parent_rate)
304 {
305 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
306
307 return mipi_tx->data_rate;
308 }
309
310 static const struct clk_ops mtk_mipi_tx_pll_ops = {
311 .prepare = mtk_mipi_tx_pll_prepare,
312 .unprepare = mtk_mipi_tx_pll_unprepare,
313 .round_rate = mtk_mipi_tx_pll_round_rate,
314 .set_rate = mtk_mipi_tx_pll_set_rate,
315 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
316 };
317
318 static int mtk_mipi_tx_power_on_signal(struct phy *phy)
319 {
320 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
321 u32 reg;
322
323 for (reg = MIPITX_DSI_CLOCK_LANE;
324 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
325 mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
326
327 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
328 RG_DSI_PAD_TIE_LOW_EN);
329
330 return 0;
331 }
332
333 static int mtk_mipi_tx_power_on(struct phy *phy)
334 {
335 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
336 int ret;
337
338
339 ret = clk_prepare_enable(mipi_tx->pll);
340 if (ret < 0)
341 return ret;
342
343
344 mtk_mipi_tx_power_on_signal(phy);
345
346 return 0;
347 }
348
349 static void mtk_mipi_tx_power_off_signal(struct phy *phy)
350 {
351 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
352 u32 reg;
353
354 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
355 RG_DSI_PAD_TIE_LOW_EN);
356
357 for (reg = MIPITX_DSI_CLOCK_LANE;
358 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
359 mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
360 }
361
362 static int mtk_mipi_tx_power_off(struct phy *phy)
363 {
364 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
365
366
367 mtk_mipi_tx_power_off_signal(phy);
368
369
370 clk_disable_unprepare(mipi_tx->pll);
371
372 return 0;
373 }
374
375 static const struct phy_ops mtk_mipi_tx_ops = {
376 .power_on = mtk_mipi_tx_power_on,
377 .power_off = mtk_mipi_tx_power_off,
378 .owner = THIS_MODULE,
379 };
380
381 static int mtk_mipi_tx_probe(struct platform_device *pdev)
382 {
383 struct device *dev = &pdev->dev;
384 struct mtk_mipi_tx *mipi_tx;
385 struct resource *mem;
386 struct clk *ref_clk;
387 const char *ref_clk_name;
388 struct clk_init_data clk_init = {
389 .ops = &mtk_mipi_tx_pll_ops,
390 .num_parents = 1,
391 .parent_names = (const char * const *)&ref_clk_name,
392 .flags = CLK_SET_RATE_GATE,
393 };
394 struct phy *phy;
395 struct phy_provider *phy_provider;
396 int ret;
397
398 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
399 if (!mipi_tx)
400 return -ENOMEM;
401
402 mipi_tx->driver_data = of_device_get_match_data(dev);
403 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
404 mipi_tx->regs = devm_ioremap_resource(dev, mem);
405 if (IS_ERR(mipi_tx->regs)) {
406 ret = PTR_ERR(mipi_tx->regs);
407 dev_err(dev, "Failed to get memory resource: %d\n", ret);
408 return ret;
409 }
410
411 ref_clk = devm_clk_get(dev, NULL);
412 if (IS_ERR(ref_clk)) {
413 ret = PTR_ERR(ref_clk);
414 dev_err(dev, "Failed to get reference clock: %d\n", ret);
415 return ret;
416 }
417 ref_clk_name = __clk_get_name(ref_clk);
418
419 ret = of_property_read_string(dev->of_node, "clock-output-names",
420 &clk_init.name);
421 if (ret < 0) {
422 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
423 return ret;
424 }
425
426 mipi_tx->pll_hw.init = &clk_init;
427 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
428 if (IS_ERR(mipi_tx->pll)) {
429 ret = PTR_ERR(mipi_tx->pll);
430 dev_err(dev, "Failed to register PLL: %d\n", ret);
431 return ret;
432 }
433
434 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
435 if (IS_ERR(phy)) {
436 ret = PTR_ERR(phy);
437 dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
438 return ret;
439 }
440 phy_set_drvdata(phy, mipi_tx);
441
442 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
443 if (IS_ERR(phy_provider)) {
444 ret = PTR_ERR(phy_provider);
445 return ret;
446 }
447
448 mipi_tx->dev = dev;
449
450 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
451 mipi_tx->pll);
452 }
453
454 static int mtk_mipi_tx_remove(struct platform_device *pdev)
455 {
456 of_clk_del_provider(pdev->dev.of_node);
457 return 0;
458 }
459
460 static const struct mtk_mipitx_data mt2701_mipitx_data = {
461 .mppll_preserve = (3 << 8)
462 };
463
464 static const struct mtk_mipitx_data mt8173_mipitx_data = {
465 .mppll_preserve = (0 << 8)
466 };
467
468 static const struct of_device_id mtk_mipi_tx_match[] = {
469 { .compatible = "mediatek,mt2701-mipi-tx",
470 .data = &mt2701_mipitx_data },
471 { .compatible = "mediatek,mt8173-mipi-tx",
472 .data = &mt8173_mipitx_data },
473 {},
474 };
475
476 struct platform_driver mtk_mipi_tx_driver = {
477 .probe = mtk_mipi_tx_probe,
478 .remove = mtk_mipi_tx_remove,
479 .driver = {
480 .name = "mediatek-mipi-tx",
481 .of_match_table = mtk_mipi_tx_match,
482 },
483 };