This source file includes following definitions.
- decon_set_bits
- decon_enable_vblank
- decon_disable_vblank
- decon_get_frame_count
- decon_setup_trigger
- decon_commit
- decon_win_set_bldeq
- decon_win_set_bldmod
- decon_win_set_pixfmt
- decon_shadow_protect
- decon_atomic_begin
- decon_update_plane
- decon_disable_plane
- decon_atomic_flush
- decon_swreset
- decon_enable
- decon_disable
- decon_te_irq_handler
- decon_clear_channels
- decon_mode_valid
- decon_bind
- decon_unbind
- decon_handle_vblank
- decon_irq_handler
- exynos5433_decon_suspend
- exynos5433_decon_resume
- decon_conf_irq
- exynos5433_decon_probe
- exynos5433_decon_remove
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9
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of_device.h>
16 #include <linux/of_gpio.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_vblank.h>
23
24 #include "exynos_drm_crtc.h"
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_fb.h"
27 #include "exynos_drm_plane.h"
28 #include "regs-decon5433.h"
29
30 #define DSD_CFG_MUX 0x1004
31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
32
33 #define WINDOWS_NR 5
34 #define PRIMARY_WIN 2
35 #define CURSON_WIN 4
36
37 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
38
39 #define I80_HW_TRG (1 << 0)
40 #define IFTYPE_HDMI (1 << 1)
41
42 static const char * const decon_clks_name[] = {
43 "pclk",
44 "aclk_decon",
45 "aclk_smmu_decon0x",
46 "aclk_xiu_decon0x",
47 "pclk_smmu_decon0x",
48 "aclk_smmu_decon1x",
49 "aclk_xiu_decon1x",
50 "pclk_smmu_decon1x",
51 "sclk_decon_vclk",
52 "sclk_decon_eclk",
53 };
54
55 struct decon_context {
56 struct device *dev;
57 struct drm_device *drm_dev;
58 void *dma_priv;
59 struct exynos_drm_crtc *crtc;
60 struct exynos_drm_plane planes[WINDOWS_NR];
61 struct exynos_drm_plane_config configs[WINDOWS_NR];
62 void __iomem *addr;
63 struct regmap *sysreg;
64 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
65 unsigned int irq;
66 unsigned int irq_vsync;
67 unsigned int irq_lcd_sys;
68 unsigned int te_irq;
69 unsigned long out_type;
70 int first_win;
71 spinlock_t vblank_lock;
72 u32 frame_id;
73 };
74
75 static const uint32_t decon_formats[] = {
76 DRM_FORMAT_XRGB1555,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
83 [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
84 [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
85 };
86
87 static const unsigned int capabilities[WINDOWS_NR] = {
88 0,
89 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
90 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
91 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
92 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
93 };
94
95 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
96 u32 val)
97 {
98 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
99 writel(val, ctx->addr + reg);
100 }
101
102 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
103 {
104 struct decon_context *ctx = crtc->ctx;
105 u32 val;
106
107 val = VIDINTCON0_INTEN;
108 if (crtc->i80_mode)
109 val |= VIDINTCON0_FRAMEDONE;
110 else
111 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
112
113 writel(val, ctx->addr + DECON_VIDINTCON0);
114
115 enable_irq(ctx->irq);
116 if (!(ctx->out_type & I80_HW_TRG))
117 enable_irq(ctx->te_irq);
118
119 return 0;
120 }
121
122 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
123 {
124 struct decon_context *ctx = crtc->ctx;
125
126 if (!(ctx->out_type & I80_HW_TRG))
127 disable_irq_nosync(ctx->te_irq);
128 disable_irq_nosync(ctx->irq);
129
130 writel(0, ctx->addr + DECON_VIDINTCON0);
131 }
132
133
134 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
135 {
136 u32 frm, pfrm, status, cnt = 2;
137
138
139
140
141
142 frm = readl(ctx->addr + DECON_CRFMID);
143 do {
144 status = readl(ctx->addr + DECON_VIDCON1);
145 pfrm = frm;
146 frm = readl(ctx->addr + DECON_CRFMID);
147 } while (frm != pfrm && --cnt);
148
149
150
151
152 if (!frm)
153 return 0;
154
155 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
156 case VIDCON1_VSTATUS_VS:
157 if (!(ctx->crtc->i80_mode))
158 --frm;
159 break;
160 case VIDCON1_VSTATUS_BP:
161 --frm;
162 break;
163 case VIDCON1_I80_ACTIVE:
164 case VIDCON1_VSTATUS_AC:
165 if (end)
166 --frm;
167 break;
168 default:
169 break;
170 }
171
172 return frm;
173 }
174
175 static void decon_setup_trigger(struct decon_context *ctx)
176 {
177 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
178 return;
179
180 if (!(ctx->out_type & I80_HW_TRG)) {
181 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
182 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
183 ctx->addr + DECON_TRIGCON);
184 return;
185 }
186
187 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
188 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
189
190 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
191 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
192 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
193 }
194
195 static void decon_commit(struct exynos_drm_crtc *crtc)
196 {
197 struct decon_context *ctx = crtc->ctx;
198 struct drm_display_mode *m = &crtc->base.mode;
199 bool interlaced = false;
200 u32 val;
201
202 if (ctx->out_type & IFTYPE_HDMI) {
203 m->crtc_hsync_start = m->crtc_hdisplay + 10;
204 m->crtc_hsync_end = m->crtc_htotal - 92;
205 m->crtc_vsync_start = m->crtc_vdisplay + 1;
206 m->crtc_vsync_end = m->crtc_vsync_start + 1;
207 if (m->flags & DRM_MODE_FLAG_INTERLACE)
208 interlaced = true;
209 }
210
211 decon_setup_trigger(ctx);
212
213
214 val = VIDOUT_LCD_ON;
215 if (interlaced)
216 val |= VIDOUT_INTERLACE_EN_F;
217 if (crtc->i80_mode) {
218 val |= VIDOUT_COMMAND_IF;
219 } else {
220 val |= VIDOUT_RGB_IF;
221 }
222
223 writel(val, ctx->addr + DECON_VIDOUTCON0);
224
225 if (interlaced)
226 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
227 VIDTCON2_HOZVAL(m->hdisplay - 1);
228 else
229 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
230 VIDTCON2_HOZVAL(m->hdisplay - 1);
231 writel(val, ctx->addr + DECON_VIDTCON2);
232
233 if (!crtc->i80_mode) {
234 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
235 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
236
237 if (interlaced)
238 vbp = vbp / 2 - 1;
239 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
240 writel(val, ctx->addr + DECON_VIDTCON00);
241
242 val = VIDTCON01_VSPW_F(
243 m->crtc_vsync_end - m->crtc_vsync_start - 1);
244 writel(val, ctx->addr + DECON_VIDTCON01);
245
246 val = VIDTCON10_HBPD_F(
247 m->crtc_htotal - m->crtc_hsync_end - 1) |
248 VIDTCON10_HFPD_F(
249 m->crtc_hsync_start - m->crtc_hdisplay - 1);
250 writel(val, ctx->addr + DECON_VIDTCON10);
251
252 val = VIDTCON11_HSPW_F(
253 m->crtc_hsync_end - m->crtc_hsync_start - 1);
254 writel(val, ctx->addr + DECON_VIDTCON11);
255 }
256
257
258 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
259
260 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
261 }
262
263 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
264 unsigned int alpha, unsigned int pixel_alpha)
265 {
266 u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
267 u32 val = 0;
268
269 switch (pixel_alpha) {
270 case DRM_MODE_BLEND_PIXEL_NONE:
271 case DRM_MODE_BLEND_COVERAGE:
272 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
273 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
274 break;
275 case DRM_MODE_BLEND_PREMULTI:
276 default:
277 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
278 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
279 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
280 } else {
281 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
282 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
283 }
284 break;
285 }
286 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
287 }
288
289 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
290 unsigned int alpha, unsigned int pixel_alpha)
291 {
292 u32 win_alpha = alpha >> 8;
293 u32 val = 0;
294
295 switch (pixel_alpha) {
296 case DRM_MODE_BLEND_PIXEL_NONE:
297 break;
298 case DRM_MODE_BLEND_COVERAGE:
299 case DRM_MODE_BLEND_PREMULTI:
300 default:
301 val |= WINCONx_ALPHA_SEL_F;
302 val |= WINCONx_BLD_PIX_F;
303 val |= WINCONx_ALPHA_MUL_F;
304 break;
305 }
306 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
307
308 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
309 val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
310 VIDOSD_Wx_ALPHA_G_F(win_alpha) |
311 VIDOSD_Wx_ALPHA_B_F(win_alpha);
312 decon_set_bits(ctx, DECON_VIDOSDxC(win),
313 VIDOSDxC_ALPHA0_RGB_MASK, val);
314 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
315 }
316 }
317
318 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
319 struct drm_framebuffer *fb)
320 {
321 struct exynos_drm_plane plane = ctx->planes[win];
322 struct exynos_drm_plane_state *state =
323 to_exynos_plane_state(plane.base.state);
324 unsigned int alpha = state->base.alpha;
325 unsigned int pixel_alpha;
326 unsigned long val;
327
328 if (fb->format->has_alpha)
329 pixel_alpha = state->base.pixel_blend_mode;
330 else
331 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
332
333 val = readl(ctx->addr + DECON_WINCONx(win));
334 val &= WINCONx_ENWIN_F;
335
336 switch (fb->format->format) {
337 case DRM_FORMAT_XRGB1555:
338 val |= WINCONx_BPPMODE_16BPP_I1555;
339 val |= WINCONx_HAWSWP_F;
340 val |= WINCONx_BURSTLEN_16WORD;
341 break;
342 case DRM_FORMAT_RGB565:
343 val |= WINCONx_BPPMODE_16BPP_565;
344 val |= WINCONx_HAWSWP_F;
345 val |= WINCONx_BURSTLEN_16WORD;
346 break;
347 case DRM_FORMAT_XRGB8888:
348 val |= WINCONx_BPPMODE_24BPP_888;
349 val |= WINCONx_WSWP_F;
350 val |= WINCONx_BURSTLEN_16WORD;
351 break;
352 case DRM_FORMAT_ARGB8888:
353 default:
354 val |= WINCONx_BPPMODE_32BPP_A8888;
355 val |= WINCONx_WSWP_F;
356 val |= WINCONx_BURSTLEN_16WORD;
357 break;
358 }
359
360 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
361
362
363
364
365
366
367
368
369
370 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
371 val &= ~WINCONx_BURSTLEN_MASK;
372 val |= WINCONx_BURSTLEN_8WORD;
373 }
374 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
375
376 if (win > 0) {
377 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
378 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
379 }
380 }
381
382 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
383 {
384 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
385 protect ? ~0 : 0);
386 }
387
388 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
389 {
390 struct decon_context *ctx = crtc->ctx;
391
392 decon_shadow_protect(ctx, true);
393 }
394
395 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
396 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
397 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
398
399 static void decon_update_plane(struct exynos_drm_crtc *crtc,
400 struct exynos_drm_plane *plane)
401 {
402 struct exynos_drm_plane_state *state =
403 to_exynos_plane_state(plane->base.state);
404 struct decon_context *ctx = crtc->ctx;
405 struct drm_framebuffer *fb = state->base.fb;
406 unsigned int win = plane->index;
407 unsigned int cpp = fb->format->cpp[0];
408 unsigned int pitch = fb->pitches[0];
409 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
410 u32 val;
411
412 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
413 val = COORDINATE_X(state->crtc.x) |
414 COORDINATE_Y(state->crtc.y / 2);
415 writel(val, ctx->addr + DECON_VIDOSDxA(win));
416
417 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
418 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
419 writel(val, ctx->addr + DECON_VIDOSDxB(win));
420 } else {
421 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
422 writel(val, ctx->addr + DECON_VIDOSDxA(win));
423
424 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
425 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
426 writel(val, ctx->addr + DECON_VIDOSDxB(win));
427 }
428
429 val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
430 VIDOSD_Wx_ALPHA_B_F(0xff);
431 writel(val, ctx->addr + DECON_VIDOSDxC(win));
432
433 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
434 VIDOSD_Wx_ALPHA_B_F(0x0);
435 writel(val, ctx->addr + DECON_VIDOSDxD(win));
436
437 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
438
439 val = dma_addr + pitch * state->src.h;
440 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
441
442 if (!(ctx->out_type & IFTYPE_HDMI))
443 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
444 | BIT_VAL(state->crtc.w * cpp, 13, 0);
445 else
446 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
447 | BIT_VAL(state->crtc.w * cpp, 14, 0);
448 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
449
450 decon_win_set_pixfmt(ctx, win, fb);
451
452
453 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
454 }
455
456 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
457 struct exynos_drm_plane *plane)
458 {
459 struct decon_context *ctx = crtc->ctx;
460 unsigned int win = plane->index;
461
462 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
463 }
464
465 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
466 {
467 struct decon_context *ctx = crtc->ctx;
468 unsigned long flags;
469
470 spin_lock_irqsave(&ctx->vblank_lock, flags);
471
472 decon_shadow_protect(ctx, false);
473
474 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
475
476 ctx->frame_id = decon_get_frame_count(ctx, true);
477
478 exynos_crtc_handle_event(crtc);
479
480 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
481 }
482
483 static void decon_swreset(struct decon_context *ctx)
484 {
485 unsigned long flags;
486 u32 val;
487 int ret;
488
489 writel(0, ctx->addr + DECON_VIDCON0);
490 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
491 ~val & VIDCON0_STOP_STATUS, 12, 20000);
492
493 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
494 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
495 ~val & VIDCON0_SWRESET, 12, 20000);
496
497 WARN(ret < 0, "failed to software reset DECON\n");
498
499 spin_lock_irqsave(&ctx->vblank_lock, flags);
500 ctx->frame_id = 0;
501 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
502
503 if (!(ctx->out_type & IFTYPE_HDMI))
504 return;
505
506 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
507 decon_set_bits(ctx, DECON_CMU,
508 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
509 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
510 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
511 ctx->addr + DECON_CRCCTRL);
512 }
513
514 static void decon_enable(struct exynos_drm_crtc *crtc)
515 {
516 struct decon_context *ctx = crtc->ctx;
517
518 pm_runtime_get_sync(ctx->dev);
519
520 exynos_drm_pipe_clk_enable(crtc, true);
521
522 decon_swreset(ctx);
523
524 decon_commit(ctx->crtc);
525 }
526
527 static void decon_disable(struct exynos_drm_crtc *crtc)
528 {
529 struct decon_context *ctx = crtc->ctx;
530 int i;
531
532 if (!(ctx->out_type & I80_HW_TRG))
533 synchronize_irq(ctx->te_irq);
534 synchronize_irq(ctx->irq);
535
536
537
538
539
540
541 for (i = ctx->first_win; i < WINDOWS_NR; i++)
542 decon_disable_plane(crtc, &ctx->planes[i]);
543
544 decon_swreset(ctx);
545
546 exynos_drm_pipe_clk_enable(crtc, false);
547
548 pm_runtime_put_sync(ctx->dev);
549 }
550
551 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
552 {
553 struct decon_context *ctx = dev_id;
554
555 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
556
557 return IRQ_HANDLED;
558 }
559
560 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
561 {
562 struct decon_context *ctx = crtc->ctx;
563 int win, i, ret;
564
565 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
566 ret = clk_prepare_enable(ctx->clks[i]);
567 if (ret < 0)
568 goto err;
569 }
570
571 decon_shadow_protect(ctx, true);
572 for (win = 0; win < WINDOWS_NR; win++)
573 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
574 decon_shadow_protect(ctx, false);
575
576 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
577
578
579 msleep(50);
580
581 err:
582 while (--i >= 0)
583 clk_disable_unprepare(ctx->clks[i]);
584 }
585
586 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
587 const struct drm_display_mode *mode)
588 {
589 struct decon_context *ctx = crtc->ctx;
590
591 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
592
593 if (ctx->irq)
594 return MODE_OK;
595
596 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
597 crtc->i80_mode ? "command" : "video");
598
599 return MODE_BAD;
600 }
601
602 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
603 .enable = decon_enable,
604 .disable = decon_disable,
605 .enable_vblank = decon_enable_vblank,
606 .disable_vblank = decon_disable_vblank,
607 .atomic_begin = decon_atomic_begin,
608 .update_plane = decon_update_plane,
609 .disable_plane = decon_disable_plane,
610 .mode_valid = decon_mode_valid,
611 .atomic_flush = decon_atomic_flush,
612 };
613
614 static int decon_bind(struct device *dev, struct device *master, void *data)
615 {
616 struct decon_context *ctx = dev_get_drvdata(dev);
617 struct drm_device *drm_dev = data;
618 struct exynos_drm_plane *exynos_plane;
619 enum exynos_drm_output_type out_type;
620 unsigned int win;
621 int ret;
622
623 ctx->drm_dev = drm_dev;
624
625 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
626 ctx->configs[win].pixel_formats = decon_formats;
627 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
628 ctx->configs[win].zpos = win - ctx->first_win;
629 ctx->configs[win].type = decon_win_types[win];
630 ctx->configs[win].capabilities = capabilities[win];
631
632 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
633 &ctx->configs[win]);
634 if (ret)
635 return ret;
636 }
637
638 exynos_plane = &ctx->planes[PRIMARY_WIN];
639 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
640 : EXYNOS_DISPLAY_TYPE_LCD;
641 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
642 out_type, &decon_crtc_ops, ctx);
643 if (IS_ERR(ctx->crtc))
644 return PTR_ERR(ctx->crtc);
645
646 decon_clear_channels(ctx->crtc);
647
648 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
649 }
650
651 static void decon_unbind(struct device *dev, struct device *master, void *data)
652 {
653 struct decon_context *ctx = dev_get_drvdata(dev);
654
655 decon_disable(ctx->crtc);
656
657
658 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
659 }
660
661 static const struct component_ops decon_component_ops = {
662 .bind = decon_bind,
663 .unbind = decon_unbind,
664 };
665
666 static void decon_handle_vblank(struct decon_context *ctx)
667 {
668 u32 frm;
669
670 spin_lock(&ctx->vblank_lock);
671
672 frm = decon_get_frame_count(ctx, true);
673
674 if (frm != ctx->frame_id) {
675
676 if ((s32)(frm - ctx->frame_id) > 0)
677 drm_crtc_handle_vblank(&ctx->crtc->base);
678 ctx->frame_id = frm;
679 }
680
681 spin_unlock(&ctx->vblank_lock);
682 }
683
684 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
685 {
686 struct decon_context *ctx = dev_id;
687 u32 val;
688
689 val = readl(ctx->addr + DECON_VIDINTCON1);
690 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
691
692 if (val) {
693 writel(val, ctx->addr + DECON_VIDINTCON1);
694 if (ctx->out_type & IFTYPE_HDMI) {
695 val = readl(ctx->addr + DECON_VIDOUTCON0);
696 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
697 if (val ==
698 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
699 return IRQ_HANDLED;
700 }
701 decon_handle_vblank(ctx);
702 }
703
704 return IRQ_HANDLED;
705 }
706
707 #ifdef CONFIG_PM
708 static int exynos5433_decon_suspend(struct device *dev)
709 {
710 struct decon_context *ctx = dev_get_drvdata(dev);
711 int i = ARRAY_SIZE(decon_clks_name);
712
713 while (--i >= 0)
714 clk_disable_unprepare(ctx->clks[i]);
715
716 return 0;
717 }
718
719 static int exynos5433_decon_resume(struct device *dev)
720 {
721 struct decon_context *ctx = dev_get_drvdata(dev);
722 int i, ret;
723
724 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
725 ret = clk_prepare_enable(ctx->clks[i]);
726 if (ret < 0)
727 goto err;
728 }
729
730 return 0;
731
732 err:
733 while (--i >= 0)
734 clk_disable_unprepare(ctx->clks[i]);
735
736 return ret;
737 }
738 #endif
739
740 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
741 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
742 NULL)
743 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
744 pm_runtime_force_resume)
745 };
746
747 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
748 {
749 .compatible = "samsung,exynos5433-decon",
750 .data = (void *)I80_HW_TRG
751 },
752 {
753 .compatible = "samsung,exynos5433-decon-tv",
754 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
755 },
756 {},
757 };
758 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
759
760 static int decon_conf_irq(struct decon_context *ctx, const char *name,
761 irq_handler_t handler, unsigned long int flags)
762 {
763 struct platform_device *pdev = to_platform_device(ctx->dev);
764 int ret, irq = platform_get_irq_byname(pdev, name);
765
766 if (irq < 0) {
767 switch (irq) {
768 case -EPROBE_DEFER:
769 return irq;
770 case -ENODATA:
771 case -ENXIO:
772 return 0;
773 default:
774 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
775 return irq;
776 }
777 }
778 irq_set_status_flags(irq, IRQ_NOAUTOEN);
779 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
780 if (ret < 0) {
781 dev_err(ctx->dev, "IRQ %s request failed\n", name);
782 return ret;
783 }
784
785 return irq;
786 }
787
788 static int exynos5433_decon_probe(struct platform_device *pdev)
789 {
790 struct device *dev = &pdev->dev;
791 struct decon_context *ctx;
792 struct resource *res;
793 int ret;
794 int i;
795
796 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
797 if (!ctx)
798 return -ENOMEM;
799
800 ctx->dev = dev;
801 ctx->out_type = (unsigned long)of_device_get_match_data(dev);
802 spin_lock_init(&ctx->vblank_lock);
803
804 if (ctx->out_type & IFTYPE_HDMI)
805 ctx->first_win = 1;
806
807 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
808 struct clk *clk;
809
810 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
811 if (IS_ERR(clk))
812 return PTR_ERR(clk);
813
814 ctx->clks[i] = clk;
815 }
816
817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 ctx->addr = devm_ioremap_resource(dev, res);
819 if (IS_ERR(ctx->addr)) {
820 dev_err(dev, "ioremap failed\n");
821 return PTR_ERR(ctx->addr);
822 }
823
824 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
825 if (ret < 0)
826 return ret;
827 ctx->irq_vsync = ret;
828
829 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
830 if (ret < 0)
831 return ret;
832 ctx->irq_lcd_sys = ret;
833
834 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
835 IRQF_TRIGGER_RISING);
836 if (ret < 0)
837 return ret;
838 if (ret) {
839 ctx->te_irq = ret;
840 ctx->out_type &= ~I80_HW_TRG;
841 }
842
843 if (ctx->out_type & I80_HW_TRG) {
844 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
845 "samsung,disp-sysreg");
846 if (IS_ERR(ctx->sysreg)) {
847 dev_err(dev, "failed to get system register\n");
848 return PTR_ERR(ctx->sysreg);
849 }
850 }
851
852 platform_set_drvdata(pdev, ctx);
853
854 pm_runtime_enable(dev);
855
856 ret = component_add(dev, &decon_component_ops);
857 if (ret)
858 goto err_disable_pm_runtime;
859
860 return 0;
861
862 err_disable_pm_runtime:
863 pm_runtime_disable(dev);
864
865 return ret;
866 }
867
868 static int exynos5433_decon_remove(struct platform_device *pdev)
869 {
870 pm_runtime_disable(&pdev->dev);
871
872 component_del(&pdev->dev, &decon_component_ops);
873
874 return 0;
875 }
876
877 struct platform_driver exynos5433_decon_driver = {
878 .probe = exynos5433_decon_probe,
879 .remove = exynos5433_decon_remove,
880 .driver = {
881 .name = "exynos5433-decon",
882 .pm = &exynos5433_decon_pm_ops,
883 .of_match_table = exynos5433_decon_driver_dt_match,
884 },
885 };