root/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

DEFINITIONS

1. write_indirect_azalia_reg
2. read_indirect_azalia_reg
3. is_audio_format_supported
4. check_audio_bandwidth_hdmi
5. check_audio_bandwidth_dpsst
6. check_audio_bandwidth_dpmst
7. check_audio_bandwidth
8. set_high_bit_rate_capable
9. set_video_latency
10. set_audio_latency
11. dce_aud_az_enable
12. dce_aud_az_disable
13. dce_aud_az_configure
14. get_azalia_clock_info_hdmi
15. get_azalia_clock_info_dp
16. dce_aud_wall_dto_setup
17. dce_aud_endpoint_valid
18. dce_aud_hw_init
19. dce_aud_destroy
20. dce_audio_create

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include <linux/slab.h>
  27 
  28 #include "reg_helper.h"
  29 #include "dce_audio.h"
  30 #include "dce/dce_11_0_d.h"
  31 #include "dce/dce_11_0_sh_mask.h"
  32 
  33 #define DCE_AUD(audio)\
  34         container_of(audio, struct dce_audio, base)
  35 
  36 #define CTX \
  37         aud->base.ctx
  38 
  39 #define DC_LOGGER_INIT()
  40 
  41 #define REG(reg)\
  42         (aud->regs->reg)
  43 
  44 #undef FN
  45 #define FN(reg_name, field_name) \
  46         aud->shifts->field_name, aud->masks->field_name
  47 
  48 #define IX_REG(reg)\
  49         ix ## reg
  50 
  51 #define AZ_REG_READ(reg_name) \
  52                 read_indirect_azalia_reg(audio, IX_REG(reg_name))
  53 
  54 #define AZ_REG_WRITE(reg_name, value) \
  55                 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
  56 
  57 static void write_indirect_azalia_reg(struct audio *audio,
  58         uint32_t reg_index,
  59         uint32_t reg_data)
  60 {
  61         struct dce_audio *aud = DCE_AUD(audio);
  62 
  63         /* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
  64         REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
  65                         AZALIA_ENDPOINT_REG_INDEX, reg_index);
  66 
  67         /* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
  68         REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
  69                         AZALIA_ENDPOINT_REG_DATA, reg_data);
  70 
  71         DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u  data: %u\n",
  72                 reg_index, reg_data);
  73 }
  74 
  75 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
  76 {
  77         struct dce_audio *aud = DCE_AUD(audio);
  78 
  79         uint32_t value = 0;
  80 
  81         /* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
  82         REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
  83                         AZALIA_ENDPOINT_REG_INDEX, reg_index);
  84 
  85         /* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
  86         value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
  87 
  88         DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u  data: %u\n",
  89                 reg_index, value);
  90 
  91         return value;
  92 }
  93 
  94 static bool is_audio_format_supported(
  95         const struct audio_info *audio_info,
  96         enum audio_format_code audio_format_code,
  97         uint32_t *format_index)
  98 {
  99         uint32_t index;
 100         uint32_t max_channe_index = 0;
 101         bool found = false;
 102 
 103         if (audio_info == NULL)
 104                 return found;
 105 
 106         /* pass through whole array */
 107         for (index = 0; index < audio_info->mode_count; index++) {
 108                 if (audio_info->modes[index].format_code == audio_format_code) {
 109                         if (found) {
 110                                 /* format has multiply entries, choose one with
 111                                  *  highst number of channels */
 112                                 if (audio_info->modes[index].channel_count >
 113                 audio_info->modes[max_channe_index].channel_count) {
 114                                         max_channe_index = index;
 115                                 }
 116                         } else {
 117                                 /* format found, save it's index */
 118                                 found = true;
 119                                 max_channe_index = index;
 120                         }
 121                 }
 122         }
 123 
 124         /* return index */
 125         if (found && format_index != NULL)
 126                 *format_index = max_channe_index;
 127 
 128         return found;
 129 }
 130 
 131 /*For HDMI, calculate if specified sample rates can fit into a given timing */
 132 static void check_audio_bandwidth_hdmi(
 133         const struct audio_crtc_info *crtc_info,
 134         uint32_t channel_count,
 135         union audio_sample_rates *sample_rates)
 136 {
 137         uint32_t samples;
 138         uint32_t  h_blank;
 139         bool limit_freq_to_48_khz = false;
 140         bool limit_freq_to_88_2_khz = false;
 141         bool limit_freq_to_96_khz = false;
 142         bool limit_freq_to_174_4_khz = false;
 143 
 144         /* For two channels supported return whatever sink support,unmodified*/
 145         if (channel_count > 2) {
 146 
 147                 /* Based on HDMI spec 1.3 Table 7.5 */
 148                 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
 149                 (crtc_info->v_active <= 576) &&
 150                 !(crtc_info->interlaced) &&
 151                 !(crtc_info->pixel_repetition == 2 ||
 152                 crtc_info->pixel_repetition == 4)) {
 153                         limit_freq_to_48_khz = true;
 154 
 155                 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
 156                                 (crtc_info->v_active <= 576) &&
 157                                 (crtc_info->interlaced) &&
 158                                 (crtc_info->pixel_repetition == 2)) {
 159                         limit_freq_to_88_2_khz = true;
 160 
 161                 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
 162                                 (crtc_info->v_active <= 576) &&
 163                                 !(crtc_info->interlaced)) {
 164                         limit_freq_to_174_4_khz = true;
 165                 }
 166         }
 167 
 168         /* Also do some calculation for the available Audio Bandwidth for the
 169          * 8 ch (i.e. for the Layout 1 => ch > 2)
 170          */
 171         h_blank = crtc_info->h_total - crtc_info->h_active;
 172 
 173         if (crtc_info->pixel_repetition)
 174                 h_blank *= crtc_info->pixel_repetition;
 175 
 176         /*based on HDMI spec 1.3 Table 7.5 */
 177         h_blank -= 58;
 178         /*for Control Period */
 179         h_blank -= 16;
 180 
 181         samples = h_blank * 10;
 182         /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
 183          * of Audio samples per line multiplied by 10 - Layout 1)
 184          */
 185         samples /= 32;
 186         samples *= crtc_info->v_active;
 187         /*Number of samples multiplied by 10, per second */
 188         samples *= crtc_info->refresh_rate;
 189         /*Number of Audio samples per second */
 190         samples /= 10;
 191 
 192         /* @todo do it after deep color is implemented
 193          * 8xx - deep color bandwidth scaling
 194          * Extra bandwidth is avaliable in deep color b/c link runs faster than
 195          * pixel rate. This has the effect of allowing more tmds characters to
 196          * be transmitted during blank
 197          */
 198 
 199         switch (crtc_info->color_depth) {
 200         case COLOR_DEPTH_888:
 201                 samples *= 4;
 202                 break;
 203         case COLOR_DEPTH_101010:
 204                 samples *= 5;
 205                 break;
 206         case COLOR_DEPTH_121212:
 207                 samples *= 6;
 208                 break;
 209         default:
 210                 samples *= 4;
 211                 break;
 212         }
 213 
 214         samples /= 4;
 215 
 216         /*check limitation*/
 217         if (samples < 88200)
 218                 limit_freq_to_48_khz = true;
 219         else if (samples < 96000)
 220                 limit_freq_to_88_2_khz = true;
 221         else if (samples < 176400)
 222                 limit_freq_to_96_khz = true;
 223         else if (samples < 192000)
 224                 limit_freq_to_174_4_khz = true;
 225 
 226         if (sample_rates != NULL) {
 227                 /* limit frequencies */
 228                 if (limit_freq_to_174_4_khz)
 229                         sample_rates->rate.RATE_192 = 0;
 230 
 231                 if (limit_freq_to_96_khz) {
 232                         sample_rates->rate.RATE_192 = 0;
 233                         sample_rates->rate.RATE_176_4 = 0;
 234                 }
 235                 if (limit_freq_to_88_2_khz) {
 236                         sample_rates->rate.RATE_192 = 0;
 237                         sample_rates->rate.RATE_176_4 = 0;
 238                         sample_rates->rate.RATE_96 = 0;
 239                 }
 240                 if (limit_freq_to_48_khz) {
 241                         sample_rates->rate.RATE_192 = 0;
 242                         sample_rates->rate.RATE_176_4 = 0;
 243                         sample_rates->rate.RATE_96 = 0;
 244                         sample_rates->rate.RATE_88_2 = 0;
 245                 }
 246         }
 247 }
 248 
 249 /*For DP SST, calculate if specified sample rates can fit into a given timing */
 250 static void check_audio_bandwidth_dpsst(
 251         const struct audio_crtc_info *crtc_info,
 252         uint32_t channel_count,
 253         union audio_sample_rates *sample_rates)
 254 {
 255         /* do nothing */
 256 }
 257 
 258 /*For DP MST, calculate if specified sample rates can fit into a given timing */
 259 static void check_audio_bandwidth_dpmst(
 260         const struct audio_crtc_info *crtc_info,
 261         uint32_t channel_count,
 262         union audio_sample_rates *sample_rates)
 263 {
 264         /* do nothing  */
 265 }
 266 
 267 static void check_audio_bandwidth(
 268         const struct audio_crtc_info *crtc_info,
 269         uint32_t channel_count,
 270         enum signal_type signal,
 271         union audio_sample_rates *sample_rates)
 272 {
 273         switch (signal) {
 274         case SIGNAL_TYPE_HDMI_TYPE_A:
 275                 check_audio_bandwidth_hdmi(
 276                         crtc_info, channel_count, sample_rates);
 277                 break;
 278         case SIGNAL_TYPE_EDP:
 279         case SIGNAL_TYPE_DISPLAY_PORT:
 280                 check_audio_bandwidth_dpsst(
 281                         crtc_info, channel_count, sample_rates);
 282                 break;
 283         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 284                 check_audio_bandwidth_dpmst(
 285                         crtc_info, channel_count, sample_rates);
 286                 break;
 287         default:
 288                 break;
 289         }
 290 }
 291 
 292 /* expose/not expose HBR capability to Audio driver */
 293 static void set_high_bit_rate_capable(
 294         struct audio *audio,
 295         bool capable)
 296 {
 297         uint32_t value = 0;
 298 
 299         /* set high bit rate audio capable*/
 300         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
 301 
 302         set_reg_field_value(value, capable,
 303                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
 304                 HBR_CAPABLE);
 305 
 306         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
 307 }
 308 
 309 /* set video latency in in ms/2+1 */
 310 static void set_video_latency(
 311         struct audio *audio,
 312         int latency_in_ms)
 313 {
 314         uint32_t value = 0;
 315 
 316         if ((latency_in_ms < 0) || (latency_in_ms > 255))
 317                 return;
 318 
 319         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
 320 
 321         set_reg_field_value(value, latency_in_ms,
 322                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 323                 VIDEO_LIPSYNC);
 324 
 325         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 326                 value);
 327 }
 328 
 329 /* set audio latency in in ms/2+1 */
 330 static void set_audio_latency(
 331         struct audio *audio,
 332         int latency_in_ms)
 333 {
 334         uint32_t value = 0;
 335 
 336         if (latency_in_ms < 0)
 337                 latency_in_ms = 0;
 338 
 339         if (latency_in_ms > 255)
 340                 latency_in_ms = 255;
 341 
 342         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
 343 
 344         set_reg_field_value(value, latency_in_ms,
 345                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 346                 AUDIO_LIPSYNC);
 347 
 348         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 349                 value);
 350 }
 351 
 352 void dce_aud_az_enable(struct audio *audio)
 353 {
 354         uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 355         DC_LOGGER_INIT();
 356 
 357         set_reg_field_value(value, 1,
 358                             AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 359                             CLOCK_GATING_DISABLE);
 360         set_reg_field_value(value, 1,
 361                             AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 362                             AUDIO_ENABLED);
 363 
 364         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 365         set_reg_field_value(value, 0,
 366                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 367                         CLOCK_GATING_DISABLE);
 368         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 369 
 370         DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u  data: 0x%x\n",
 371                         audio->inst, value);
 372 }
 373 
 374 void dce_aud_az_disable(struct audio *audio)
 375 {
 376         uint32_t value;
 377         DC_LOGGER_INIT();
 378 
 379         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 380         set_reg_field_value(value, 1,
 381                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 382                         CLOCK_GATING_DISABLE);
 383         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 384 
 385         set_reg_field_value(value, 0,
 386                 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 387                 AUDIO_ENABLED);
 388         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 389 
 390         set_reg_field_value(value, 0,
 391                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 392                         CLOCK_GATING_DISABLE);
 393         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 394         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 395         DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u  data: 0x%x\n",
 396                         audio->inst, value);
 397 }
 398 
 399 void dce_aud_az_configure(
 400         struct audio *audio,
 401         enum signal_type signal,
 402         const struct audio_crtc_info *crtc_info,
 403         const struct audio_info *audio_info)
 404 {
 405         struct dce_audio *aud = DCE_AUD(audio);
 406 
 407         uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
 408         uint32_t value;
 409         uint32_t field = 0;
 410         enum audio_format_code audio_format_code;
 411         uint32_t format_index;
 412         uint32_t index;
 413         bool is_ac3_supported = false;
 414         union audio_sample_rates sample_rate;
 415         uint32_t strlen = 0;
 416         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 417         set_reg_field_value(value, 1,
 418                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 419                         CLOCK_GATING_DISABLE);
 420         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 421 
 422         /* Speaker Allocation */
 423         /*
 424         uint32_t value;
 425         uint32_t field = 0;*/
 426         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 427 
 428         set_reg_field_value(value,
 429                 speakers,
 430                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 431                 SPEAKER_ALLOCATION);
 432 
 433         /* LFE_PLAYBACK_LEVEL = LFEPBL
 434          * LFEPBL = 0 : Unknown or refer to other information
 435          * LFEPBL = 1 : 0dB playback
 436          * LFEPBL = 2 : +10dB playback
 437          * LFE_BL = 3 : Reserved
 438          */
 439         set_reg_field_value(value,
 440                 0,
 441                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 442                 LFE_PLAYBACK_LEVEL);
 443         /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
 444          *  why are we writing to it?  DCE8 does not write this */
 445 
 446 
 447         set_reg_field_value(value,
 448                 0,
 449                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 450                 HDMI_CONNECTION);
 451 
 452         set_reg_field_value(value,
 453                 0,
 454                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 455                 DP_CONNECTION);
 456 
 457         field = get_reg_field_value(value,
 458                         AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 459                         EXTRA_CONNECTION_INFO);
 460 
 461         field &= ~0x1;
 462 
 463         set_reg_field_value(value,
 464                 field,
 465                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 466                 EXTRA_CONNECTION_INFO);
 467 
 468         /* set audio for output signal */
 469         switch (signal) {
 470         case SIGNAL_TYPE_HDMI_TYPE_A:
 471                 set_reg_field_value(value,
 472                         1,
 473                         AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 474                         HDMI_CONNECTION);
 475 
 476                 break;
 477 
 478         case SIGNAL_TYPE_EDP:
 479         case SIGNAL_TYPE_DISPLAY_PORT:
 480         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 481                 set_reg_field_value(value,
 482                         1,
 483                         AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 484                         DP_CONNECTION);
 485                 break;
 486         default:
 487                 BREAK_TO_DEBUGGER();
 488                 break;
 489         }
 490 
 491         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
 492 
 493         /*  Audio Descriptors   */
 494         /* pass through all formats */
 495         for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
 496                         format_index++) {
 497                 audio_format_code =
 498                         (AUDIO_FORMAT_CODE_FIRST + format_index);
 499 
 500                 /* those are unsupported, skip programming */
 501                 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
 502                         audio_format_code == AUDIO_FORMAT_CODE_DST)
 503                         continue;
 504 
 505                 value = 0;
 506 
 507                 /* check if supported */
 508                 if (is_audio_format_supported(
 509                                 audio_info, audio_format_code, &index)) {
 510                         const struct audio_mode *audio_mode =
 511                                         &audio_info->modes[index];
 512                         union audio_sample_rates sample_rates =
 513                                         audio_mode->sample_rates;
 514                         uint8_t byte2 = audio_mode->max_bit_rate;
 515 
 516                         /* adjust specific properties */
 517                         switch (audio_format_code) {
 518                         case AUDIO_FORMAT_CODE_LINEARPCM: {
 519                                 check_audio_bandwidth(
 520                                         crtc_info,
 521                                         audio_mode->channel_count,
 522                                         signal,
 523                                         &sample_rates);
 524 
 525                                 byte2 = audio_mode->sample_size;
 526 
 527                                 set_reg_field_value(value,
 528                                                 sample_rates.all,
 529                                                 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 530                                                 SUPPORTED_FREQUENCIES_STEREO);
 531                                 }
 532                                 break;
 533                         case AUDIO_FORMAT_CODE_AC3:
 534                                 is_ac3_supported = true;
 535                                 break;
 536                         case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
 537                         case AUDIO_FORMAT_CODE_DTS_HD:
 538                         case AUDIO_FORMAT_CODE_MAT_MLP:
 539                         case AUDIO_FORMAT_CODE_DST:
 540                         case AUDIO_FORMAT_CODE_WMAPRO:
 541                                 byte2 = audio_mode->vendor_specific;
 542                                 break;
 543                         default:
 544                                 break;
 545                         }
 546 
 547                         /* fill audio format data */
 548                         set_reg_field_value(value,
 549                                         audio_mode->channel_count - 1,
 550                                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 551                                         MAX_CHANNELS);
 552 
 553                         set_reg_field_value(value,
 554                                         sample_rates.all,
 555                                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 556                                         SUPPORTED_FREQUENCIES);
 557 
 558                         set_reg_field_value(value,
 559                                         byte2,
 560                                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 561                                         DESCRIPTOR_BYTE_2);
 562                 } /* if */
 563 
 564                 AZ_REG_WRITE(
 565                                 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
 566                                 value);
 567         } /* for */
 568 
 569         if (is_ac3_supported)
 570                 /* todo: this reg global.  why program global register? */
 571                 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
 572                                 0x05);
 573 
 574         /* check for 192khz/8-Ch support for HBR requirements */
 575         sample_rate.all = 0;
 576         sample_rate.rate.RATE_192 = 1;
 577 
 578         check_audio_bandwidth(
 579                 crtc_info,
 580                 8,
 581                 signal,
 582                 &sample_rate);
 583 
 584         set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
 585 
 586         /* Audio and Video Lipsync */
 587         set_video_latency(audio, audio_info->video_latency);
 588         set_audio_latency(audio, audio_info->audio_latency);
 589 
 590         value = 0;
 591         set_reg_field_value(value, audio_info->manufacture_id,
 592                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 593                 MANUFACTURER_ID);
 594 
 595         set_reg_field_value(value, audio_info->product_id,
 596                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 597                 PRODUCT_ID);
 598 
 599         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 600                 value);
 601 
 602         value = 0;
 603 
 604         /*get display name string length */
 605         while (audio_info->display_name[strlen++] != '\0') {
 606                 if (strlen >=
 607                 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
 608                         break;
 609                 }
 610         set_reg_field_value(value, strlen,
 611                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
 612                 SINK_DESCRIPTION_LEN);
 613 
 614         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
 615                 value);
 616         DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
 617                 audio->inst, value, audio_info->display_name);
 618 
 619         /*
 620         *write the port ID:
 621         *PORT_ID0 = display index
 622         *PORT_ID1 = 16bit BDF
 623         *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
 624         */
 625 
 626         value = 0;
 627 
 628         set_reg_field_value(value, audio_info->port_id[0],
 629                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
 630                 PORT_ID0);
 631 
 632         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
 633 
 634         value = 0;
 635         set_reg_field_value(value, audio_info->port_id[1],
 636                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
 637                 PORT_ID1);
 638 
 639         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
 640 
 641         /*write the 18 char monitor string */
 642 
 643         value = 0;
 644         set_reg_field_value(value, audio_info->display_name[0],
 645                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 646                 DESCRIPTION0);
 647 
 648         set_reg_field_value(value, audio_info->display_name[1],
 649                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 650                 DESCRIPTION1);
 651 
 652         set_reg_field_value(value, audio_info->display_name[2],
 653                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 654                 DESCRIPTION2);
 655 
 656         set_reg_field_value(value, audio_info->display_name[3],
 657                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 658                 DESCRIPTION3);
 659 
 660         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
 661 
 662         value = 0;
 663         set_reg_field_value(value, audio_info->display_name[4],
 664                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 665                 DESCRIPTION4);
 666 
 667         set_reg_field_value(value, audio_info->display_name[5],
 668                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 669                 DESCRIPTION5);
 670 
 671         set_reg_field_value(value, audio_info->display_name[6],
 672                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 673                 DESCRIPTION6);
 674 
 675         set_reg_field_value(value, audio_info->display_name[7],
 676                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 677                 DESCRIPTION7);
 678 
 679         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
 680 
 681         value = 0;
 682         set_reg_field_value(value, audio_info->display_name[8],
 683                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 684                 DESCRIPTION8);
 685 
 686         set_reg_field_value(value, audio_info->display_name[9],
 687                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 688                 DESCRIPTION9);
 689 
 690         set_reg_field_value(value, audio_info->display_name[10],
 691                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 692                 DESCRIPTION10);
 693 
 694         set_reg_field_value(value, audio_info->display_name[11],
 695                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 696                 DESCRIPTION11);
 697 
 698         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
 699 
 700         value = 0;
 701         set_reg_field_value(value, audio_info->display_name[12],
 702                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 703                 DESCRIPTION12);
 704 
 705         set_reg_field_value(value, audio_info->display_name[13],
 706                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 707                 DESCRIPTION13);
 708 
 709         set_reg_field_value(value, audio_info->display_name[14],
 710                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 711                 DESCRIPTION14);
 712 
 713         set_reg_field_value(value, audio_info->display_name[15],
 714                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 715                 DESCRIPTION15);
 716 
 717         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
 718 
 719         value = 0;
 720         set_reg_field_value(value, audio_info->display_name[16],
 721                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
 722                 DESCRIPTION16);
 723 
 724         set_reg_field_value(value, audio_info->display_name[17],
 725                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
 726                 DESCRIPTION17);
 727 
 728         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
 729         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 730         set_reg_field_value(value, 0,
 731                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 732                         CLOCK_GATING_DISABLE);
 733         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 734 }
 735 
 736 /*
 737 * todo: wall clk related functionality probably belong to clock_src.
 738 */
 739 
 740 /* search pixel clock value for Azalia HDMI Audio */
 741 static void get_azalia_clock_info_hdmi(
 742         uint32_t crtc_pixel_clock_100hz,
 743         uint32_t actual_pixel_clock_100Hz,
 744         struct azalia_clock_info *azalia_clock_info)
 745 {
 746         /* audio_dto_phase= 24 * 10,000;
 747          *   24MHz in [100Hz] units */
 748         azalia_clock_info->audio_dto_phase =
 749                         24 * 10000;
 750 
 751         /* audio_dto_module = PCLKFrequency * 10,000;
 752          *  [khz] -> [100Hz] */
 753         azalia_clock_info->audio_dto_module =
 754                         actual_pixel_clock_100Hz;
 755 }
 756 
 757 static void get_azalia_clock_info_dp(
 758         uint32_t requested_pixel_clock_100Hz,
 759         const struct audio_pll_info *pll_info,
 760         struct azalia_clock_info *azalia_clock_info)
 761 {
 762         /* Reported dpDtoSourceClockInkhz value for
 763          * DCE8 already adjusted for SS, do not need any
 764          * adjustment here anymore
 765          */
 766 
 767         /*audio_dto_phase = 24 * 10,000;
 768          * 24MHz in [100Hz] units */
 769         azalia_clock_info->audio_dto_phase = 24 * 10000;
 770 
 771         /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
 772          *  [khz] ->[100Hz] */
 773         azalia_clock_info->audio_dto_module =
 774                 pll_info->dp_dto_source_clock_in_khz * 10;
 775 }
 776 
 777 void dce_aud_wall_dto_setup(
 778         struct audio *audio,
 779         enum signal_type signal,
 780         const struct audio_crtc_info *crtc_info,
 781         const struct audio_pll_info *pll_info)
 782 {
 783         struct dce_audio *aud = DCE_AUD(audio);
 784 
 785         struct azalia_clock_info clock_info = { 0 };
 786 
 787         if (dc_is_hdmi_signal(signal)) {
 788                 uint32_t src_sel;
 789 
 790                 /*DTO0 Programming goal:
 791                 -generate 24MHz, 128*Fs from 24MHz
 792                 -use DTO0 when an active HDMI port is connected
 793                 (optionally a DP is connected) */
 794 
 795                 /* calculate DTO settings */
 796                 get_azalia_clock_info_hdmi(
 797                         crtc_info->requested_pixel_clock_100Hz,
 798                         crtc_info->calculated_pixel_clock_100Hz,
 799                         &clock_info);
 800 
 801                 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
 802                                 "calculated_pixel_clock_100Hz =%d\n"\
 803                                 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
 804                                 crtc_info->requested_pixel_clock_100Hz,\
 805                                 crtc_info->calculated_pixel_clock_100Hz,\
 806                                 clock_info.audio_dto_module,\
 807                                 clock_info.audio_dto_phase);
 808 
 809                 /* On TN/SI, Program DTO source select and DTO select before
 810                 programming DTO modulo and DTO phase. These bits must be
 811                 programmed first, otherwise there will be no HDMI audio at boot
 812                 up. This is a HW sequence change (different from old ASICs).
 813                 Caution when changing this programming sequence.
 814 
 815                 HDMI enabled, using DTO0
 816                 program master CRTC for DTO0 */
 817                 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
 818                 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
 819                         DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
 820                         DCCG_AUDIO_DTO_SEL, 0);
 821 
 822                 /* module */
 823                 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
 824                         DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
 825 
 826                 /* phase */
 827                 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
 828                         DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
 829         } else {
 830                 /*DTO1 Programming goal:
 831                 -generate 24MHz, 512*Fs, 128*Fs from 24MHz
 832                 -default is to used DTO1, and switch to DTO0 when an audio
 833                 master HDMI port is connected
 834                 -use as default for DP
 835 
 836                 calculate DTO settings */
 837                 get_azalia_clock_info_dp(
 838                         crtc_info->requested_pixel_clock_100Hz,
 839                         pll_info,
 840                         &clock_info);
 841 
 842                 /* Program DTO select before programming DTO modulo and DTO
 843                 phase. default to use DTO1 */
 844 
 845                 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
 846                                 DCCG_AUDIO_DTO_SEL, 1);
 847 
 848                         /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
 849                          * Select 512fs for DP TODO: web register definition
 850                          * does not match register header file
 851                          * DCE11 version it's commented out while DCE8 it's set to 1
 852                         */
 853 
 854                 /* module */
 855                 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
 856                                 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
 857 
 858                 /* phase */
 859                 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
 860                                 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
 861 
 862                 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
 863                                 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
 864 
 865         }
 866 }
 867 
 868 static bool dce_aud_endpoint_valid(struct audio *audio)
 869 {
 870         uint32_t value;
 871         uint32_t port_connectivity;
 872 
 873         value = AZ_REG_READ(
 874                         AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
 875 
 876         port_connectivity = get_reg_field_value(value,
 877                         AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
 878                         PORT_CONNECTIVITY);
 879 
 880         return !(port_connectivity == 1);
 881 }
 882 
 883 /* initialize HW state */
 884 void dce_aud_hw_init(
 885                 struct audio *audio)
 886 {
 887         uint32_t value;
 888         struct dce_audio *aud = DCE_AUD(audio);
 889 
 890         /* we only need to program the following registers once, so we only do
 891         it for the inst 0*/
 892         if (audio->inst != 0)
 893                 return;
 894 
 895         /* Suport R5 - 32khz
 896          * Suport R6 - 44.1khz
 897          * Suport R7 - 48khz
 898          */
 899         /*disable clock gating before write to endpoint register*/
 900         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 901         set_reg_field_value(value, 1,
 902                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 903                         CLOCK_GATING_DISABLE);
 904         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 905         REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
 906                         AUDIO_RATE_CAPABILITIES, 0x70);
 907 
 908         /*Keep alive bit to verify HW block in BU. */
 909         REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
 910                         CLKSTOP, 1,
 911                         EPSS, 1);
 912         set_reg_field_value(value, 0,
 913                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 914                         CLOCK_GATING_DISABLE);
 915         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 916 }
 917 
 918 static const struct audio_funcs funcs = {
 919         .endpoint_valid = dce_aud_endpoint_valid,
 920         .hw_init = dce_aud_hw_init,
 921         .wall_dto_setup = dce_aud_wall_dto_setup,
 922         .az_enable = dce_aud_az_enable,
 923         .az_disable = dce_aud_az_disable,
 924         .az_configure = dce_aud_az_configure,
 925         .destroy = dce_aud_destroy,
 926 };
 927 void dce_aud_destroy(struct audio **audio)
 928 {
 929         struct dce_audio *aud = DCE_AUD(*audio);
 930 
 931         kfree(aud);
 932         *audio = NULL;
 933 }
 934 
 935 struct audio *dce_audio_create(
 936                 struct dc_context *ctx,
 937                 unsigned int inst,
 938                 const struct dce_audio_registers *reg,
 939                 const struct dce_audio_shift *shifts,
 940                 const struct dce_audio_mask *masks
 941                 )
 942 {
 943         struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
 944 
 945         if (audio == NULL) {
 946                 ASSERT_CRITICAL(audio);
 947                 return NULL;
 948         }
 949 
 950         audio->base.ctx = ctx;
 951         audio->base.inst = inst;
 952         audio->base.funcs = &funcs;
 953 
 954         audio->regs = reg;
 955         audio->shifts = shifts;
 956         audio->masks = masks;
 957         return &audio->base;
 958 }
 959