drivers/gpu/drm/amd/display/dc/dcn20/dcn20

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This source file includes following definitions.
dsc2_construct
dsc2_get_enc_caps
dsc2_read_state
dsc2_validate_stream
dsc_config_log
dsc2_set_config
dsc2_get_packed_pps
dsc2_enable
dsc2_disable
dsc_log_pps
dsc_prepare_config
dsc_dc_pixel_encoding_to_dsc_pixel_format
dsc_dc_color_depth_to_dsc_bits_per_comp
dsc_init_reg_values
dsc_update_from_dsc_parameters
dsc_write_to_registers
   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  27 #include "reg_helper.h"
  28 #include "dcn20_dsc.h"
  29 #include "dsc/dscc_types.h"
  30 
  31 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
  32 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
  33                         struct dsc_optc_config *dsc_optc_cfg);
  34 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
  35 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
  36 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
  37 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple);
  38 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth);
  39 
  40 /* Object I/F functions */
  41 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
  42 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
  43 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
  44 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
  45                 struct dsc_optc_config *dsc_optc_cfg);
  46 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
  47 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
  48 static void dsc2_disable(struct display_stream_compressor *dsc);
  49 
  50 const struct dsc_funcs dcn20_dsc_funcs = {
  51         .dsc_get_enc_caps = dsc2_get_enc_caps,
  52         .dsc_read_state = dsc2_read_state,
  53         .dsc_validate_stream = dsc2_validate_stream,
  54         .dsc_set_config = dsc2_set_config,
  55         .dsc_get_packed_pps = dsc2_get_packed_pps,
  56         .dsc_enable = dsc2_enable,
  57         .dsc_disable = dsc2_disable,
  58 };
  59 
  60 /* Macro definitios for REG_SET macros*/
  61 #define CTX \
  62         dsc20->base.ctx
  63 
  64 #define REG(reg)\
  65         dsc20->dsc_regs->reg
  66 
  67 #undef FN
  68 #define FN(reg_name, field_name) \
  69         dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
  70 #define DC_LOGGER \
  71         dsc->ctx->logger
  72 
  73 enum dsc_bits_per_comp {
  74         DSC_BPC_8 = 8,
  75         DSC_BPC_10 = 10,
  76         DSC_BPC_12 = 12,
  77         DSC_BPC_UNKNOWN
  78 };
  79 
  80 /* API functions (external or via structure->function_pointer) */
  81 
  82 void dsc2_construct(struct dcn20_dsc *dsc,
  83                 struct dc_context *ctx,
  84                 int inst,
  85                 const struct dcn20_dsc_registers *dsc_regs,
  86                 const struct dcn20_dsc_shift *dsc_shift,
  87                 const struct dcn20_dsc_mask *dsc_mask)
  88 {
  89         dsc->base.ctx = ctx;
  90         dsc->base.inst = inst;
  91         dsc->base.funcs = &dcn20_dsc_funcs;
  92 
  93         dsc->dsc_regs = dsc_regs;
  94         dsc->dsc_shift = dsc_shift;
  95         dsc->dsc_mask = dsc_mask;
  96 
  97         dsc->max_image_width = 5184;
  98 }
  99 
 100 
 101 #define DCN20_MAX_PIXEL_CLOCK_Mhz      1188
 102 #define DCN20_MAX_DISPLAY_CLOCK_Mhz    1200
 103 
 104 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput
 105  * can be doubled, tripled etc. by using additional DSC engines.
 106  */
 107 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
 108 {
 109         dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
 110 
 111         dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
 112         dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
 113         dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
 114         dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
 115 
 116         dsc_enc_caps->lb_bit_depth = 13;
 117         dsc_enc_caps->is_block_pred_supported = true;
 118 
 119         dsc_enc_caps->color_formats.bits.RGB = 1;
 120         dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
 121         dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 0;
 122         dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
 123         dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
 124 
 125         dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
 126         dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
 127         dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
 128 
 129         /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
 130          * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
 131          * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
 132          * be sufficient to process the input pixel rate fed into a single DSC engine.
 133          */
 134         dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
 135 
 136         /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our
 137          * throughput and number of slices, but also introduces a lower limit of 2 slices
 138          */
 139         if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {
 140                 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
 141                 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
 142                 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
 143         }
 144 
 145         // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM.
 146         dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
 147         dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
 148 }
 149 
 150 
 151 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
 152  * into a dcn_dsc_state struct.
 153  */
 154 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
 155 {
 156         struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 157 
 158         REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
 159         REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
 160         REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel);
 161 }
 162 
 163 
 164 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
 165 {
 166         struct dsc_optc_config dsc_optc_cfg;
 167         struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 168 
 169         if (dsc_cfg->pic_width > dsc20->max_image_width)
 170                 return false;
 171 
 172         return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
 173 }
 174 
 175 
 176 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
 177 {
 178         DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
 179         DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
 180         DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
 181                 config->dc_dsc_cfg.bits_per_pixel,
 182                 config->dc_dsc_cfg.bits_per_pixel / 16,
 183                 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
 184         DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
 185 }
 186 
 187 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
 188                 struct dsc_optc_config *dsc_optc_cfg)
 189 {
 190         bool is_config_ok;
 191         struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 192 
 193         DC_LOG_DSC(" ");
 194         DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
 195         dsc_config_log(dsc, dsc_cfg);
 196         is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
 197         ASSERT(is_config_ok);
 198         DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
 199         dsc_log_pps(dsc, &dsc20->reg_vals.pps);
 200         dsc_write_to_registers(dsc, &dsc20->reg_vals);
 201 }
 202 
 203 
 204 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
 205 {
 206         bool is_config_ok;
 207         struct dsc_reg_values dsc_reg_vals;
 208         struct dsc_optc_config dsc_optc_cfg;
 209 
 210         DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
 211         dsc_config_log(dsc, dsc_cfg);
 212         DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
 213         is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
 214         ASSERT(is_config_ok);
 215         drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
 216         dsc_log_pps(dsc, &dsc_reg_vals.pps);
 217 
 218         return is_config_ok;
 219 }
 220 
 221 
 222 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
 223 {
 224         struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 225 
 226         /* TODO Check if DSC alreay in use? */
 227         DC_LOG_DSC("enable DSC at opp pipe %d", opp_pipe);
 228 
 229         REG_UPDATE(DSC_TOP_CONTROL,
 230                 DSC_CLOCK_EN, 1);
 231 
 232         REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
 233                 DSCRM_DSC_FORWARD_EN, 1,
 234                 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
 235 }
 236 
 237 
 238 static void dsc2_disable(struct display_stream_compressor *dsc)
 239 {
 240         struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 241 
 242         DC_LOG_DSC("disable DSC");
 243 
 244         REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
 245                 DSCRM_DSC_FORWARD_EN, 0);
 246 
 247         REG_UPDATE(DSC_TOP_CONTROL,
 248                 DSC_CLOCK_EN, 0);
 249 }
 250 
 251 
 252 /* This module's internal functions */
 253 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
 254 {
 255         int i;
 256         int bits_per_pixel = pps->bits_per_pixel;
 257 
 258         DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
 259         DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
 260         DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
 261         DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
 262         DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
 263         DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
 264         DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
 265         DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
 266         DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
 267         DC_LOG_DSC("\tpic_height %d", pps->pic_height);
 268         DC_LOG_DSC("\tpic_width %d", pps->pic_width);
 269         DC_LOG_DSC("\tslice_height %d", pps->slice_height);
 270         DC_LOG_DSC("\tslice_width %d", pps->slice_width);
 271         DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
 272         DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
 273         DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
 274         DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
 275         DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
 276         DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
 277         DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
 278         DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
 279         DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
 280         DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
 281         DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
 282         DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
 283         DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
 284         /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */
 285         DC_LOG_DSC("\tnative_420 %d", pps->native_420);
 286         DC_LOG_DSC("\tnative_422 %d", pps->native_422);
 287         DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
 288         DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
 289         DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
 290         DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
 291         DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
 292         DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
 293         DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
 294         DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
 295         DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
 296 
 297         for (i = 0; i < NUM_BUF_RANGES - 1; i++)
 298                 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
 299 
 300         for (i = 0; i < NUM_BUF_RANGES; i++) {
 301                 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
 302                 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
 303                 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
 304         }
 305 }
 306 
 307 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
 308                         struct dsc_optc_config *dsc_optc_cfg)
 309 {
 310         struct dsc_parameters dsc_params;
 311 
 312         /* Validate input parameters */
 313         ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
 314         ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
 315         ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
 316         ASSERT(dsc_cfg->pic_width);
 317         ASSERT(dsc_cfg->pic_height);
 318         ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
 319                   (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||
 320                 (dsc_cfg->dc_dsc_cfg.version_minor == 2 &&
 321                   ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
 322                     dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
 323         ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
 324 
 325         if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
 326                 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
 327                 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
 328                 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
 329                         8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||
 330                 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:
 331                         ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
 332                         dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||
 333                 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
 334                 dm_output_to_console("%s: Invalid parameters\n", __func__);
 335                 return false;
 336         }
 337 
 338         dsc_init_reg_values(dsc_reg_vals);
 339 
 340         /* Copy input config */
 341         dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
 342         dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
 343         dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
 344         dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
 345         dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
 346         dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
 347         dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
 348         dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
 349         dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
 350         dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
 351 
 352         // TODO: in addition to validating slice height (pic height must be divisible by slice height),
 353         // see what happens when the same condition doesn't apply for slice_width/pic_width.
 354         dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
 355         dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
 356 
 357         ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
 358         if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
 359                 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
 360                 return false;
 361         }
 362 
 363         dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
 364         if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
 365                 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
 366         else
 367                 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
 368 
 369         dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
 370         dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
 371         dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
 372         dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
 373 
 374         if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) {
 375                 dm_output_to_console("%s: DSC config failed\n", __func__);
 376                 return false;
 377         }
 378 
 379         dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
 380 
 381         dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
 382         dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
 383         dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
 384                                         dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
 385                                         dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
 386 
 387         return true;
 388 }
 389 
 390 
 391 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
 392 {
 393         enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
 394 
 395         /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */
 396 
 397         switch (dc_pix_enc) {
 398         case PIXEL_ENCODING_RGB:
 399                 dsc_pix_fmt = DSC_PIXFMT_RGB;
 400                 break;
 401         case PIXEL_ENCODING_YCBCR422:
 402                 if (is_ycbcr422_simple)
 403                         dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;
 404                 else
 405                         dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;
 406                 break;
 407         case PIXEL_ENCODING_YCBCR444:
 408                 dsc_pix_fmt = DSC_PIXFMT_YCBCR444;
 409                 break;
 410         case PIXEL_ENCODING_YCBCR420:
 411                 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;
 412                 break;
 413         default:
 414                 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
 415                 break;
 416         }
 417 
 418         ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
 419         return dsc_pix_fmt;
 420 }
 421 
 422 
 423 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)
 424 {
 425         enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;
 426 
 427         switch (dc_color_depth) {
 428         case COLOR_DEPTH_888:
 429                 bpc = DSC_BPC_8;
 430                 break;
 431         case COLOR_DEPTH_101010:
 432                 bpc = DSC_BPC_10;
 433                 break;
 434         case COLOR_DEPTH_121212:
 435                 bpc = DSC_BPC_12;
 436                 break;
 437         default:
 438                 bpc = DSC_BPC_UNKNOWN;
 439                 break;
 440         }
 441 
 442         return bpc;
 443 }
 444 
 445 
 446 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
 447 {
 448         int i;
 449 
 450         memset(reg_vals, 0, sizeof(struct dsc_reg_values));
 451 
 452         /* Non-PPS values */
 453         reg_vals->dsc_clock_enable            = 1;
 454         reg_vals->dsc_clock_gating_disable    = 0;
 455         reg_vals->underflow_recovery_en       = 0;
 456         reg_vals->underflow_occurred_int_en   = 0;
 457         reg_vals->underflow_occurred_status   = 0;
 458         reg_vals->ich_reset_at_eol            = 0;
 459         reg_vals->alternate_ich_encoding_en   = 0;
 460         reg_vals->rc_buffer_model_size        = 0;
 461         /*reg_vals->disable_ich                 = 0;*/
 462         reg_vals->dsc_dbg_en                  = 0;
 463 
 464         for (i = 0; i < 4; i++)
 465                 reg_vals->rc_buffer_model_overflow_int_en[i] = 0;
 466 
 467         /* PPS values */
 468         reg_vals->pps.dsc_version_minor           = 2;
 469         reg_vals->pps.dsc_version_major           = 1;
 470         reg_vals->pps.line_buf_depth              = 9;
 471         reg_vals->pps.bits_per_component          = 8;
 472         reg_vals->pps.block_pred_enable           = 1;
 473         reg_vals->pps.slice_chunk_size            = 0;
 474         reg_vals->pps.pic_width                   = 0;
 475         reg_vals->pps.pic_height                  = 0;
 476         reg_vals->pps.slice_width                 = 0;
 477         reg_vals->pps.slice_height                = 0;
 478         reg_vals->pps.initial_xmit_delay          = 170;
 479         reg_vals->pps.initial_dec_delay           = 0;
 480         reg_vals->pps.initial_scale_value         = 0;
 481         reg_vals->pps.scale_increment_interval    = 0;
 482         reg_vals->pps.scale_decrement_interval    = 0;
 483         reg_vals->pps.nfl_bpg_offset              = 0;
 484         reg_vals->pps.slice_bpg_offset            = 0;
 485         reg_vals->pps.nsl_bpg_offset              = 0;
 486         reg_vals->pps.initial_offset              = 6144;
 487         reg_vals->pps.final_offset                = 0;
 488         reg_vals->pps.flatness_min_qp             = 3;
 489         reg_vals->pps.flatness_max_qp             = 12;
 490         reg_vals->pps.rc_model_size               = 8192;
 491         reg_vals->pps.rc_edge_factor              = 6;
 492         reg_vals->pps.rc_quant_incr_limit0        = 11;
 493         reg_vals->pps.rc_quant_incr_limit1        = 11;
 494         reg_vals->pps.rc_tgt_offset_low           = 3;
 495         reg_vals->pps.rc_tgt_offset_high          = 3;
 496 }
 497 
 498 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.
 499  * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn
 500  * affects non-PPS register values.
 501  */
 502 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)
 503 {
 504         int i;
 505 
 506         reg_vals->pps = dsc_params->pps;
 507 
 508         // pps_computed will have the "expanded" values; need to shift them to make them fit for regs.
 509         for (i = 0; i < NUM_BUF_RANGES - 1; i++)
 510                 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;
 511 
 512         reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;
 513         reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf;
 514 }
 515 
 516 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
 517 {
 518         uint32_t temp_int;
 519         struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 520 
 521         REG_SET(DSC_DEBUG_CONTROL, 0,
 522                 DSC_DBG_EN, reg_vals->dsc_dbg_en);
 523 
 524         // dsccif registers
 525         REG_SET_5(DSCCIF_CONFIG0, 0,
 526                 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
 527                 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
 528                 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
 529                 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
 530                 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
 531 
 532         REG_SET_2(DSCCIF_CONFIG1, 0,
 533                 PIC_WIDTH, reg_vals->pps.pic_width,
 534                 PIC_HEIGHT, reg_vals->pps.pic_height);
 535 
 536         // dscc registers
 537         REG_SET_4(DSCC_CONFIG0, 0,
 538                 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol,
 539                 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
 540                 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
 541                 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
 542 
 543         REG_SET(DSCC_CONFIG1, 0,
 544                         DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
 545         /*REG_SET_2(DSCC_CONFIG1, 0,
 546                 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
 547                 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
 548 
 549         REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
 550                 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
 551                 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],
 552                 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],
 553                 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);
 554 
 555         REG_SET_3(DSCC_PPS_CONFIG0, 0,
 556                 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
 557                 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
 558                 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
 559 
 560         if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
 561                 temp_int = reg_vals->bpp_x32;
 562         else
 563                 temp_int = reg_vals->bpp_x32 >> 1;
 564 
 565         REG_SET_7(DSCC_PPS_CONFIG1, 0,
 566                 BITS_PER_PIXEL, temp_int,
 567                 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
 568                 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
 569                 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
 570                 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
 571                 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
 572                 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
 573 
 574         REG_SET_2(DSCC_PPS_CONFIG2, 0,
 575                 PIC_WIDTH, reg_vals->pps.pic_width,
 576                 PIC_HEIGHT, reg_vals->pps.pic_height);
 577 
 578         REG_SET_2(DSCC_PPS_CONFIG3, 0,
 579                 SLICE_WIDTH, reg_vals->pps.slice_width,
 580                 SLICE_HEIGHT, reg_vals->pps.slice_height);
 581 
 582         REG_SET(DSCC_PPS_CONFIG4, 0,
 583                 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
 584 
 585         REG_SET_2(DSCC_PPS_CONFIG5, 0,
 586                 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
 587                 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
 588 
 589         REG_SET_3(DSCC_PPS_CONFIG6, 0,
 590                 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
 591                 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
 592                 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
 593 
 594         REG_SET_2(DSCC_PPS_CONFIG7, 0,
 595                 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
 596                 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
 597 
 598         REG_SET_2(DSCC_PPS_CONFIG8, 0,
 599                 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
 600                 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
 601 
 602         REG_SET_2(DSCC_PPS_CONFIG9, 0,
 603                 INITIAL_OFFSET, reg_vals->pps.initial_offset,
 604                 FINAL_OFFSET, reg_vals->pps.final_offset);
 605 
 606         REG_SET_3(DSCC_PPS_CONFIG10, 0,
 607                 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
 608                 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
 609                 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
 610 
 611         REG_SET_5(DSCC_PPS_CONFIG11, 0,
 612                 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
 613                 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
 614                 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
 615                 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
 616                 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
 617 
 618         REG_SET_4(DSCC_PPS_CONFIG12, 0,
 619                 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
 620                 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
 621                 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
 622                 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
 623 
 624         REG_SET_4(DSCC_PPS_CONFIG13, 0,
 625                 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
 626                 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
 627                 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
 628                 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
 629 
 630         REG_SET_4(DSCC_PPS_CONFIG14, 0,
 631                 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
 632                 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
 633                 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
 634                 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
 635 
 636         REG_SET_5(DSCC_PPS_CONFIG15, 0,
 637                 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
 638                 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
 639                 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
 640                 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
 641                 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
 642 
 643         REG_SET_6(DSCC_PPS_CONFIG16, 0,
 644                 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
 645                 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
 646                 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
 647                 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
 648                 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
 649                 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
 650 
 651         REG_SET_6(DSCC_PPS_CONFIG17, 0,
 652                 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
 653                 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
 654                 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
 655                 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
 656                 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
 657                 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
 658 
 659         REG_SET_6(DSCC_PPS_CONFIG18, 0,
 660                 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
 661                 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
 662                 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
 663                 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
 664                 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
 665                 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
 666 
 667         REG_SET_6(DSCC_PPS_CONFIG19, 0,
 668                 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
 669                 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
 670                 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
 671                 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
 672                 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
 673                 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
 674 
 675         REG_SET_6(DSCC_PPS_CONFIG20, 0,
 676                 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
 677                 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
 678                 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
 679                 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
 680                 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
 681                 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
 682 
 683         REG_SET_6(DSCC_PPS_CONFIG21, 0,
 684                 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
 685                 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
 686                 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
 687                 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
 688                 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
 689                 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
 690 
 691         REG_SET_6(DSCC_PPS_CONFIG22, 0,
 692                 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
 693                 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
 694                 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
 695                 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
 696                 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
 697                 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
 698 
 699         if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) {
 700                 /* It's safe to do this as long as debug bus is not being used in DAL Diag environment.
 701                  *
 702                  * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder
 703                  * value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's
 704                  * required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are
 705                  * being read from Diag register dump. The register below is used in place of a scratch register to make
 706                  * 'initial_dec_delay' available.
 707                  */
 708 
 709                 temp_int = reg_vals->pps.initial_dec_delay;
 710                 REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0,
 711                         DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f,
 712                         DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f,
 713                         DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f,
 714                         DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1);
 715         }
 716 }
 717 
 718 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c

DEFINITIONS
