root/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

DEFINITIONS

1. amdgpu_ib_get
2. amdgpu_ib_free
3. amdgpu_ib_schedule
4. amdgpu_ib_pool_init
5. amdgpu_ib_pool_fini
6. amdgpu_ib_ring_tests
7. amdgpu_debugfs_sa_info
8. amdgpu_debugfs_sa_init

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_debugfs.h>
  34 
  35 #include "amdgpu.h"
  36 #include "atom.h"
  37 #include "amdgpu_trace.h"
  38 
  39 #define AMDGPU_IB_TEST_TIMEOUT  msecs_to_jiffies(1000)
  40 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000)
  41 
  42 /*
  43  * IB
  44  * IBs (Indirect Buffers) and areas of GPU accessible memory where
  45  * commands are stored.  You can put a pointer to the IB in the
  46  * command ring and the hw will fetch the commands from the IB
  47  * and execute them.  Generally userspace acceleration drivers
  48  * produce command buffers which are send to the kernel and
  49  * put in IBs for execution by the requested ring.
  50  */
  51 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
  52 
  53 /**
  54  * amdgpu_ib_get - request an IB (Indirect Buffer)
  55  *
  56  * @ring: ring index the IB is associated with
  57  * @size: requested IB size
  58  * @ib: IB object returned
  59  *
  60  * Request an IB (all asics).  IBs are allocated using the
  61  * suballocator.
  62  * Returns 0 on success, error on failure.
  63  */
  64 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  65                   unsigned size, struct amdgpu_ib *ib)
  66 {
  67         int r;
  68 
  69         if (size) {
  70                 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
  71                                       &ib->sa_bo, size, 256);
  72                 if (r) {
  73                         dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
  74                         return r;
  75                 }
  76 
  77                 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
  78 
  79                 if (!vm)
  80                         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
  81         }
  82 
  83         return 0;
  84 }
  85 
  86 /**
  87  * amdgpu_ib_free - free an IB (Indirect Buffer)
  88  *
  89  * @adev: amdgpu_device pointer
  90  * @ib: IB object to free
  91  * @f: the fence SA bo need wait on for the ib alloation
  92  *
  93  * Free an IB (all asics).
  94  */
  95 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
  96                     struct dma_fence *f)
  97 {
  98         amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
  99 }
 100 
 101 /**
 102  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
 103  *
 104  * @adev: amdgpu_device pointer
 105  * @num_ibs: number of IBs to schedule
 106  * @ibs: IB objects to schedule
 107  * @f: fence created during this submission
 108  *
 109  * Schedule an IB on the associated ring (all asics).
 110  * Returns 0 on success, error on failure.
 111  *
 112  * On SI, there are two parallel engines fed from the primary ring,
 113  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
 114  * resource descriptors have moved to memory, the CE allows you to
 115  * prime the caches while the DE is updating register state so that
 116  * the resource descriptors will be already in cache when the draw is
 117  * processed.  To accomplish this, the userspace driver submits two
 118  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
 119  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
 120  * to SI there was just a DE IB.
 121  */
 122 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 123                        struct amdgpu_ib *ibs, struct amdgpu_job *job,
 124                        struct dma_fence **f)
 125 {
 126         struct amdgpu_device *adev = ring->adev;
 127         struct amdgpu_ib *ib = &ibs[0];
 128         struct dma_fence *tmp = NULL;
 129         bool skip_preamble, need_ctx_switch;
 130         unsigned patch_offset = ~0;
 131         struct amdgpu_vm *vm;
 132         uint64_t fence_ctx;
 133         uint32_t status = 0, alloc_size;
 134         unsigned fence_flags = 0;
 135 
 136         unsigned i;
 137         int r = 0;
 138         bool need_pipe_sync = false;
 139 
 140         if (num_ibs == 0)
 141                 return -EINVAL;
 142 
 143         /* ring tests don't use a job */
 144         if (job) {
 145                 vm = job->vm;
 146                 fence_ctx = job->base.s_fence ?
 147                         job->base.s_fence->scheduled.context : 0;
 148         } else {
 149                 vm = NULL;
 150                 fence_ctx = 0;
 151         }
 152 
 153         if (!ring->sched.ready) {
 154                 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
 155                 return -EINVAL;
 156         }
 157 
 158         if (vm && !job->vmid) {
 159                 dev_err(adev->dev, "VM IB without ID\n");
 160                 return -EINVAL;
 161         }
 162 
 163         alloc_size = ring->funcs->emit_frame_size + num_ibs *
 164                 ring->funcs->emit_ib_size;
 165 
 166         r = amdgpu_ring_alloc(ring, alloc_size);
 167         if (r) {
 168                 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
 169                 return r;
 170         }
 171 
 172         need_ctx_switch = ring->current_ctx != fence_ctx;
 173         if (ring->funcs->emit_pipeline_sync && job &&
 174             ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
 175              (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
 176              amdgpu_vm_need_pipeline_sync(ring, job))) {
 177                 need_pipe_sync = true;
 178 
 179                 if (tmp)
 180                         trace_amdgpu_ib_pipe_sync(job, tmp);
 181 
 182                 dma_fence_put(tmp);
 183         }
 184 
 185         if (ring->funcs->insert_start)
 186                 ring->funcs->insert_start(ring);
 187 
 188         if (job) {
 189                 r = amdgpu_vm_flush(ring, job, need_pipe_sync);
 190                 if (r) {
 191                         amdgpu_ring_undo(ring);
 192                         return r;
 193                 }
 194         }
 195 
 196         if (job && ring->funcs->init_cond_exec)
 197                 patch_offset = amdgpu_ring_init_cond_exec(ring);
 198 
 199 #ifdef CONFIG_X86_64
 200         if (!(adev->flags & AMD_IS_APU))
 201 #endif
 202         {
 203                 if (ring->funcs->emit_hdp_flush)
 204                         amdgpu_ring_emit_hdp_flush(ring);
 205                 else
 206                         amdgpu_asic_flush_hdp(adev, ring);
 207         }
 208 
 209         if (need_ctx_switch)
 210                 status |= AMDGPU_HAVE_CTX_SWITCH;
 211 
 212         skip_preamble = ring->current_ctx == fence_ctx;
 213         if (job && ring->funcs->emit_cntxcntl) {
 214                 status |= job->preamble_status;
 215                 status |= job->preemption_status;
 216                 amdgpu_ring_emit_cntxcntl(ring, status);
 217         }
 218 
 219         for (i = 0; i < num_ibs; ++i) {
 220                 ib = &ibs[i];
 221 
 222                 /* drop preamble IBs if we don't have a context switch */
 223                 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
 224                     skip_preamble &&
 225                     !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
 226                     !amdgpu_mcbp &&
 227                     !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
 228                         continue;
 229 
 230                 amdgpu_ring_emit_ib(ring, job, ib, status);
 231                 status &= ~AMDGPU_HAVE_CTX_SWITCH;
 232         }
 233 
 234         if (ring->funcs->emit_tmz)
 235                 amdgpu_ring_emit_tmz(ring, false);
 236 
 237 #ifdef CONFIG_X86_64
 238         if (!(adev->flags & AMD_IS_APU))
 239 #endif
 240                 amdgpu_asic_invalidate_hdp(adev, ring);
 241 
 242         if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
 243                 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
 244 
 245         /* wrap the last IB with fence */
 246         if (job && job->uf_addr) {
 247                 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
 248                                        fence_flags | AMDGPU_FENCE_FLAG_64BIT);
 249         }
 250 
 251         r = amdgpu_fence_emit(ring, f, fence_flags);
 252         if (r) {
 253                 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
 254                 if (job && job->vmid)
 255                         amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
 256                 amdgpu_ring_undo(ring);
 257                 return r;
 258         }
 259 
 260         if (ring->funcs->insert_end)
 261                 ring->funcs->insert_end(ring);
 262 
 263         if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
 264                 amdgpu_ring_patch_cond_exec(ring, patch_offset);
 265 
 266         ring->current_ctx = fence_ctx;
 267         if (vm && ring->funcs->emit_switch_buffer)
 268                 amdgpu_ring_emit_switch_buffer(ring);
 269         amdgpu_ring_commit(ring);
 270         return 0;
 271 }
 272 
 273 /**
 274  * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
 275  *
 276  * @adev: amdgpu_device pointer
 277  *
 278  * Initialize the suballocator to manage a pool of memory
 279  * for use as IBs (all asics).
 280  * Returns 0 on success, error on failure.
 281  */
 282 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
 283 {
 284         int r;
 285 
 286         if (adev->ib_pool_ready) {
 287                 return 0;
 288         }
 289         r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
 290                                       AMDGPU_IB_POOL_SIZE*64*1024,
 291                                       AMDGPU_GPU_PAGE_SIZE,
 292                                       AMDGPU_GEM_DOMAIN_GTT);
 293         if (r) {
 294                 return r;
 295         }
 296 
 297         adev->ib_pool_ready = true;
 298         if (amdgpu_debugfs_sa_init(adev)) {
 299                 dev_err(adev->dev, "failed to register debugfs file for SA\n");
 300         }
 301         return 0;
 302 }
 303 
 304 /**
 305  * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
 306  *
 307  * @adev: amdgpu_device pointer
 308  *
 309  * Tear down the suballocator managing the pool of memory
 310  * for use as IBs (all asics).
 311  */
 312 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
 313 {
 314         if (adev->ib_pool_ready) {
 315                 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
 316                 adev->ib_pool_ready = false;
 317         }
 318 }
 319 
 320 /**
 321  * amdgpu_ib_ring_tests - test IBs on the rings
 322  *
 323  * @adev: amdgpu_device pointer
 324  *
 325  * Test an IB (Indirect Buffer) on each ring.
 326  * If the test fails, disable the ring.
 327  * Returns 0 on success, error if the primary GFX ring
 328  * IB test fails.
 329  */
 330 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
 331 {
 332         unsigned i;
 333         int r, ret = 0;
 334         long tmo_gfx, tmo_mm;
 335 
 336         tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
 337         if (amdgpu_sriov_vf(adev)) {
 338                 /* for MM engines in hypervisor side they are not scheduled together
 339                  * with CP and SDMA engines, so even in exclusive mode MM engine could
 340                  * still running on other VF thus the IB TEST TIMEOUT for MM engines
 341                  * under SR-IOV should be set to a long time. 8 sec should be enough
 342                  * for the MM comes back to this VF.
 343                  */
 344                 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
 345         }
 346 
 347         if (amdgpu_sriov_runtime(adev)) {
 348                 /* for CP & SDMA engines since they are scheduled together so
 349                  * need to make the timeout width enough to cover the time
 350                  * cost waiting for it coming back under RUNTIME only
 351                 */
 352                 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
 353         } else if (adev->gmc.xgmi.hive_id) {
 354                 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
 355         }
 356 
 357         for (i = 0; i < adev->num_rings; ++i) {
 358                 struct amdgpu_ring *ring = adev->rings[i];
 359                 long tmo;
 360 
 361                 /* KIQ rings don't have an IB test because we never submit IBs
 362                  * to them and they have no interrupt support.
 363                  */
 364                 if (!ring->sched.ready || !ring->funcs->test_ib)
 365                         continue;
 366 
 367                 /* MM engine need more time */
 368                 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 369                         ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
 370                         ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
 371                         ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
 372                         ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
 373                         ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
 374                         tmo = tmo_mm;
 375                 else
 376                         tmo = tmo_gfx;
 377 
 378                 r = amdgpu_ring_test_ib(ring, tmo);
 379                 if (!r) {
 380                         DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n",
 381                                       ring->name);
 382                         continue;
 383                 }
 384 
 385                 ring->sched.ready = false;
 386                 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n",
 387                           ring->name, r);
 388 
 389                 if (ring == &adev->gfx.gfx_ring[0]) {
 390                         /* oh, oh, that's really bad */
 391                         adev->accel_working = false;
 392                         return r;
 393 
 394                 } else {
 395                         ret = r;
 396                 }
 397         }
 398         return ret;
 399 }
 400 
 401 /*
 402  * Debugfs info
 403  */
 404 #if defined(CONFIG_DEBUG_FS)
 405 
 406 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
 407 {
 408         struct drm_info_node *node = (struct drm_info_node *) m->private;
 409         struct drm_device *dev = node->minor->dev;
 410         struct amdgpu_device *adev = dev->dev_private;
 411 
 412         amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
 413 
 414         return 0;
 415 
 416 }
 417 
 418 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
 419         {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
 420 };
 421 
 422 #endif
 423 
 424 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
 425 {
 426 #if defined(CONFIG_DEBUG_FS)
 427         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
 428 #else
 429         return 0;
 430 #endif
 431 }