This source file includes following definitions.
- dsi_calc_phy_rate
- dsi_get_phy_params
- dsi_get_dpi_color_coding
- dsi_phy_tst_set
- dsi_set_phy_timer
- dsi_set_mipi_phy
- dsi_set_mode_timing
- dsi_set_video_mode
- dsi_mipi_init
- dsi_encoder_disable
- dsi_encoder_enable
- dsi_encoder_phy_mode_valid
- dsi_encoder_mode_valid
- dsi_encoder_mode_set
- dsi_encoder_atomic_check
- dw_drm_encoder_init
- dsi_host_attach
- dsi_host_detach
- dsi_host_init
- dsi_bridge_init
- dsi_bind
- dsi_unbind
- dsi_parse_dt
- dsi_probe
- dsi_remove
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14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_device.h>
22 #include <drm/drm_encoder_slave.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_print.h>
26 #include <drm/drm_probe_helper.h>
27
28 #include "dw_dsi_reg.h"
29
30 #define MAX_TX_ESC_CLK 10
31 #define ROUND(x, y) ((x) / (y) + \
32 ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
33 #define PHY_REF_CLK_RATE 19200000
34 #define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000))
35
36 #define encoder_to_dsi(encoder) \
37 container_of(encoder, struct dw_dsi, encoder)
38 #define host_to_dsi(host) \
39 container_of(host, struct dw_dsi, host)
40
41 struct mipi_phy_params {
42 u32 clk_t_lpx;
43 u32 clk_t_hs_prepare;
44 u32 clk_t_hs_zero;
45 u32 clk_t_hs_trial;
46 u32 clk_t_wakeup;
47 u32 data_t_lpx;
48 u32 data_t_hs_prepare;
49 u32 data_t_hs_zero;
50 u32 data_t_hs_trial;
51 u32 data_t_ta_go;
52 u32 data_t_ta_get;
53 u32 data_t_wakeup;
54 u32 hstx_ckg_sel;
55 u32 pll_fbd_div5f;
56 u32 pll_fbd_div1f;
57 u32 pll_fbd_2p;
58 u32 pll_enbwt;
59 u32 pll_fbd_p;
60 u32 pll_fbd_s;
61 u32 pll_pre_div1p;
62 u32 pll_pre_p;
63 u32 pll_vco_750M;
64 u32 pll_lpf_rs;
65 u32 pll_lpf_cs;
66 u32 clklp2hs_time;
67 u32 clkhs2lp_time;
68 u32 lp2hs_time;
69 u32 hs2lp_time;
70 u32 clk_to_data_delay;
71 u32 data_to_clk_delay;
72 u32 lane_byte_clk_kHz;
73 u32 clk_division;
74 };
75
76 struct dsi_hw_ctx {
77 void __iomem *base;
78 struct clk *pclk;
79 };
80
81 struct dw_dsi {
82 struct drm_encoder encoder;
83 struct drm_bridge *bridge;
84 struct mipi_dsi_host host;
85 struct drm_display_mode cur_mode;
86 struct dsi_hw_ctx *ctx;
87 struct mipi_phy_params phy;
88
89 u32 lanes;
90 enum mipi_dsi_pixel_format format;
91 unsigned long mode_flags;
92 bool enable;
93 };
94
95 struct dsi_data {
96 struct dw_dsi dsi;
97 struct dsi_hw_ctx ctx;
98 };
99
100 struct dsi_phy_range {
101 u32 min_range_kHz;
102 u32 max_range_kHz;
103 u32 pll_vco_750M;
104 u32 hstx_ckg_sel;
105 };
106
107 static const struct dsi_phy_range dphy_range_info[] = {
108 { 46875, 62500, 1, 7 },
109 { 62500, 93750, 0, 7 },
110 { 93750, 125000, 1, 6 },
111 { 125000, 187500, 0, 6 },
112 { 187500, 250000, 1, 5 },
113 { 250000, 375000, 0, 5 },
114 { 375000, 500000, 1, 4 },
115 { 500000, 750000, 0, 4 },
116 { 750000, 1000000, 1, 0 },
117 { 1000000, 1500000, 0, 0 }
118 };
119
120 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
121 {
122 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
123 u32 tmp_kHz = req_kHz;
124 u32 i = 0;
125 u32 q_pll = 1;
126 u32 m_pll = 0;
127 u32 n_pll = 0;
128 u32 r_pll = 1;
129 u32 m_n = 0;
130 u32 m_n_int = 0;
131 u32 f_kHz = 0;
132 u64 temp;
133
134
135
136
137 do {
138 f_kHz = tmp_kHz;
139
140 for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
141 if (f_kHz >= dphy_range_info[i].min_range_kHz &&
142 f_kHz <= dphy_range_info[i].max_range_kHz)
143 break;
144
145 if (i == ARRAY_SIZE(dphy_range_info)) {
146 DRM_ERROR("%dkHz out of range\n", f_kHz);
147 return 0;
148 }
149
150 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
151 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
152
153 if (phy->hstx_ckg_sel <= 7 &&
154 phy->hstx_ckg_sel >= 4)
155 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
156
157 temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
158 m_n_int = temp / (u64)1000000000;
159 m_n = (temp % (u64)1000000000) / (u64)100000000;
160
161 if (m_n_int % 2 == 0) {
162 if (m_n * 6 >= 50) {
163 n_pll = 2;
164 m_pll = (m_n_int + 1) * n_pll;
165 } else if (m_n * 6 >= 30) {
166 n_pll = 3;
167 m_pll = m_n_int * n_pll + 2;
168 } else {
169 n_pll = 1;
170 m_pll = m_n_int * n_pll;
171 }
172 } else {
173 if (m_n * 6 >= 50) {
174 n_pll = 1;
175 m_pll = (m_n_int + 1) * n_pll;
176 } else if (m_n * 6 >= 30) {
177 n_pll = 1;
178 m_pll = (m_n_int + 1) * n_pll;
179 } else if (m_n * 6 >= 10) {
180 n_pll = 3;
181 m_pll = m_n_int * n_pll + 1;
182 } else {
183 n_pll = 2;
184 m_pll = m_n_int * n_pll;
185 }
186 }
187
188 if (n_pll == 1) {
189 phy->pll_fbd_p = 0;
190 phy->pll_pre_div1p = 1;
191 } else {
192 phy->pll_fbd_p = n_pll;
193 phy->pll_pre_div1p = 0;
194 }
195
196 if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
197 r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
198
199 if (m_pll == 2) {
200 phy->pll_pre_p = 0;
201 phy->pll_fbd_s = 0;
202 phy->pll_fbd_div1f = 0;
203 phy->pll_fbd_div5f = 1;
204 } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
205 phy->pll_pre_p = m_pll / (2 * r_pll);
206 phy->pll_fbd_s = 0;
207 phy->pll_fbd_div1f = 1;
208 phy->pll_fbd_div5f = 0;
209 } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
210 if (((m_pll / (2 * r_pll)) % 2) == 0) {
211 phy->pll_pre_p =
212 (m_pll / (2 * r_pll)) / 2 - 1;
213 phy->pll_fbd_s =
214 (m_pll / (2 * r_pll)) % 2 + 2;
215 } else {
216 phy->pll_pre_p =
217 (m_pll / (2 * r_pll)) / 2;
218 phy->pll_fbd_s =
219 (m_pll / (2 * r_pll)) % 2;
220 }
221 phy->pll_fbd_div1f = 0;
222 phy->pll_fbd_div5f = 0;
223 } else {
224 phy->pll_pre_p = 0;
225 phy->pll_fbd_s = 0;
226 phy->pll_fbd_div1f = 0;
227 phy->pll_fbd_div5f = 1;
228 }
229
230 f_kHz = (u64)1000000000 * (u64)m_pll /
231 ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
232
233 if (f_kHz >= req_kHz)
234 break;
235
236 tmp_kHz += 10;
237
238 } while (true);
239
240 return f_kHz;
241 }
242
243 static void dsi_get_phy_params(u32 phy_req_kHz,
244 struct mipi_phy_params *phy)
245 {
246 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
247 u32 phy_rate_kHz;
248 u32 ui;
249
250 memset(phy, 0, sizeof(*phy));
251
252 phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
253 if (!phy_rate_kHz)
254 return;
255
256 ui = 1000000 / phy_rate_kHz;
257
258 phy->clk_t_lpx = ROUND(50, 8 * ui);
259 phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
260
261 phy->clk_t_hs_zero = ROUND(262, 8 * ui);
262 phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
263 phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
264 if (phy->clk_t_wakeup > 0xff)
265 phy->clk_t_wakeup = 0xff;
266 phy->data_t_wakeup = phy->clk_t_wakeup;
267 phy->data_t_lpx = phy->clk_t_lpx;
268 phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
269 phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
270 phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
271 phy->data_t_ta_go = 3;
272 phy->data_t_ta_get = 4;
273
274 phy->pll_enbwt = 1;
275 phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
276 phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
277 phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
278 phy->hs2lp_time = phy->clkhs2lp_time;
279 phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
280 phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
281 phy->clkhs2lp_time;
282
283 phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
284 phy->clk_division =
285 DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
286 }
287
288 static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)
289 {
290 u32 val;
291
292
293
294
295 switch (format) {
296 case MIPI_DSI_FMT_RGB888:
297 val = DSI_24BITS_1;
298 break;
299 default:
300 val = DSI_24BITS_1;
301 break;
302 }
303
304 return val;
305 }
306
307
308
309
310 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
311 {
312 u32 reg_write = 0x10000 + reg;
313
314
315
316
317 writel(reg_write, base + PHY_TST_CTRL1);
318 writel(0x02, base + PHY_TST_CTRL0);
319 writel(0x00, base + PHY_TST_CTRL0);
320
321
322
323
324 writel(val, base + PHY_TST_CTRL1);
325 writel(0x02, base + PHY_TST_CTRL0);
326 writel(0x00, base + PHY_TST_CTRL0);
327 }
328
329 static void dsi_set_phy_timer(void __iomem *base,
330 struct mipi_phy_params *phy,
331 u32 lanes)
332 {
333 u32 val;
334
335
336
337
338 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
339 writel(val, base + PHY_IF_CFG);
340
341
342
343
344 val = readl(base + CLKMGR_CFG) | phy->clk_division;
345 writel(val, base + CLKMGR_CFG);
346
347
348
349
350 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
351 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
352 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
353 phy->clkhs2lp_time);
354 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
355 phy->clklp2hs_time);
356 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
357 phy->data_to_clk_delay);
358 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),
359 phy->clk_to_data_delay);
360 }
361
362 static void dsi_set_mipi_phy(void __iomem *base,
363 struct mipi_phy_params *phy,
364 u32 lanes)
365 {
366 u32 delay_count;
367 u32 val;
368 u32 i;
369
370
371 dsi_set_phy_timer(base, phy, lanes);
372
373
374
375
376 writel(0, base + PHY_RSTZ);
377 writel(0, base + PHY_TST_CTRL0);
378 writel(1, base + PHY_TST_CTRL0);
379 writel(0, base + PHY_TST_CTRL0);
380
381
382
383
384
385 dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
386 dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
387 dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
388 dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
389 dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
390
391
392
393
394
395 for (i = 0; i < lanes; i++) {
396 dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
397 dsi_phy_tst_set(base, DATA_THS_PREPARE(i),
398 phy->data_t_hs_prepare);
399 dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
400 dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
401 dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
402 dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
403 dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
404 }
405
406
407
408
409
410 dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
411 val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
412 (phy->pll_fbd_2p << 1) + phy->pll_enbwt;
413 dsi_phy_tst_set(base, PHY_CFG_PLL_I, val);
414 dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
415 dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
416 val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
417 dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val);
418 val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
419 phy->pll_lpf_cs;
420 dsi_phy_tst_set(base, PHY_CFG_PLL_V, val);
421
422 writel(PHY_ENABLECLK, base + PHY_RSTZ);
423 udelay(1);
424 writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
425 udelay(1);
426 writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
427 usleep_range(1000, 1500);
428
429
430
431
432 delay_count = 100;
433 while (delay_count) {
434 val = readl(base + PHY_STATUS);
435 if ((BIT(0) | BIT(2)) & val)
436 break;
437
438 udelay(1);
439 delay_count--;
440 }
441
442 if (!delay_count)
443 DRM_INFO("phylock and phystopstateclklane is not ready.\n");
444 }
445
446 static void dsi_set_mode_timing(void __iomem *base,
447 u32 lane_byte_clk_kHz,
448 struct drm_display_mode *mode,
449 enum mipi_dsi_pixel_format format)
450 {
451 u32 hfp, hbp, hsw, vfp, vbp, vsw;
452 u32 hline_time;
453 u32 hsa_time;
454 u32 hbp_time;
455 u32 pixel_clk_kHz;
456 int htot, vtot;
457 u32 val;
458 u64 tmp;
459
460 val = dsi_get_dpi_color_coding(format);
461 writel(val, base + DPI_COLOR_CODING);
462
463 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2;
464 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1;
465 writel(val, base + DPI_CFG_POL);
466
467
468
469
470
471
472
473
474 pixel_clk_kHz = mode->clock;
475 htot = mode->htotal;
476 vtot = mode->vtotal;
477 hfp = mode->hsync_start - mode->hdisplay;
478 hbp = mode->htotal - mode->hsync_end;
479 hsw = mode->hsync_end - mode->hsync_start;
480 vfp = mode->vsync_start - mode->vdisplay;
481 vbp = mode->vtotal - mode->vsync_end;
482 vsw = mode->vsync_end - mode->vsync_start;
483 if (vsw > 15) {
484 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
485 vsw = 15;
486 }
487
488 hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
489 hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
490 tmp = (u64)htot * (u64)lane_byte_clk_kHz;
491 hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
492
493
494 writel(hsa_time, base + VID_HSA_TIME);
495 writel(hbp_time, base + VID_HBP_TIME);
496 writel(hline_time, base + VID_HLINE_TIME);
497
498 writel(vsw, base + VID_VSA_LINES);
499 writel(vbp, base + VID_VBP_LINES);
500 writel(vfp, base + VID_VFP_LINES);
501 writel(mode->vdisplay, base + VID_VACTIVE_LINES);
502 writel(mode->hdisplay, base + VID_PKT_SIZE);
503
504 DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n",
505 htot, hfp, hbp, hsw);
506 DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n",
507 vtot, vfp, vbp, vsw);
508 DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n",
509 hsa_time, hbp_time, hline_time);
510 }
511
512 static void dsi_set_video_mode(void __iomem *base, unsigned long flags)
513 {
514 u32 val;
515 u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
516 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
517 u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO |
518 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
519 u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
520
521
522
523
524 if ((flags & mode_mask) == non_burst_sync_pulse)
525 val = DSI_NON_BURST_SYNC_PULSES;
526 else if ((flags & mode_mask) == non_burst_sync_event)
527 val = DSI_NON_BURST_SYNC_EVENTS;
528 else
529 val = DSI_BURST_SYNC_PULSES_1;
530 writel(val, base + VID_MODE_CFG);
531
532 writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
533 writel(DSI_VIDEO_MODE, base + MODE_CFG);
534 }
535
536 static void dsi_mipi_init(struct dw_dsi *dsi)
537 {
538 struct dsi_hw_ctx *ctx = dsi->ctx;
539 struct mipi_phy_params *phy = &dsi->phy;
540 struct drm_display_mode *mode = &dsi->cur_mode;
541 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
542 void __iomem *base = ctx->base;
543 u32 dphy_req_kHz;
544
545
546
547
548 dphy_req_kHz = mode->clock * bpp / dsi->lanes;
549 dsi_get_phy_params(dphy_req_kHz, phy);
550
551
552 writel(RESET, base + PWR_UP);
553
554
555 dsi_set_mipi_phy(base, phy, dsi->lanes);
556
557
558 dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
559
560
561 dsi_set_video_mode(base, dsi->mode_flags);
562
563
564 writel(POWERUP, base + PWR_UP);
565
566 DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
567 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
568 }
569
570 static void dsi_encoder_disable(struct drm_encoder *encoder)
571 {
572 struct dw_dsi *dsi = encoder_to_dsi(encoder);
573 struct dsi_hw_ctx *ctx = dsi->ctx;
574 void __iomem *base = ctx->base;
575
576 if (!dsi->enable)
577 return;
578
579 writel(0, base + PWR_UP);
580 writel(0, base + LPCLK_CTRL);
581 writel(0, base + PHY_RSTZ);
582 clk_disable_unprepare(ctx->pclk);
583
584 dsi->enable = false;
585 }
586
587 static void dsi_encoder_enable(struct drm_encoder *encoder)
588 {
589 struct dw_dsi *dsi = encoder_to_dsi(encoder);
590 struct dsi_hw_ctx *ctx = dsi->ctx;
591 int ret;
592
593 if (dsi->enable)
594 return;
595
596 ret = clk_prepare_enable(ctx->pclk);
597 if (ret) {
598 DRM_ERROR("fail to enable pclk: %d\n", ret);
599 return;
600 }
601
602 dsi_mipi_init(dsi);
603
604 dsi->enable = true;
605 }
606
607 static enum drm_mode_status dsi_encoder_phy_mode_valid(
608 struct drm_encoder *encoder,
609 const struct drm_display_mode *mode)
610 {
611 struct dw_dsi *dsi = encoder_to_dsi(encoder);
612 struct mipi_phy_params phy;
613 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
614 u32 req_kHz, act_kHz, lane_byte_clk_kHz;
615
616
617 memset(&phy, 0, sizeof(phy));
618 req_kHz = mode->clock * bpp / dsi->lanes;
619 act_kHz = dsi_calc_phy_rate(req_kHz, &phy);
620 lane_byte_clk_kHz = act_kHz / 8;
621
622 DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...",
623 mode->hdisplay, mode->vdisplay, bpp,
624 drm_mode_vrefresh(mode), mode->clock);
625
626
627
628
629
630 if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) {
631 DRM_DEBUG_DRIVER("OK!\n");
632 return MODE_OK;
633 }
634
635 DRM_DEBUG_DRIVER("BAD!\n");
636 return MODE_BAD;
637 }
638
639 static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder,
640 const struct drm_display_mode *mode)
641
642 {
643 const struct drm_crtc_helper_funcs *crtc_funcs = NULL;
644 struct drm_crtc *crtc = NULL;
645 struct drm_display_mode adj_mode;
646 enum drm_mode_status ret;
647
648
649
650
651
652
653
654 drm_for_each_crtc(crtc, encoder->dev) {
655
656
657
658
659 drm_mode_copy(&adj_mode, mode);
660
661 crtc_funcs = crtc->helper_private;
662 if (crtc_funcs && crtc_funcs->mode_fixup)
663 if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
664 return MODE_BAD;
665
666 ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
667 if (ret != MODE_OK)
668 return ret;
669 }
670 return MODE_OK;
671 }
672
673 static void dsi_encoder_mode_set(struct drm_encoder *encoder,
674 struct drm_display_mode *mode,
675 struct drm_display_mode *adj_mode)
676 {
677 struct dw_dsi *dsi = encoder_to_dsi(encoder);
678
679 drm_mode_copy(&dsi->cur_mode, adj_mode);
680 }
681
682 static int dsi_encoder_atomic_check(struct drm_encoder *encoder,
683 struct drm_crtc_state *crtc_state,
684 struct drm_connector_state *conn_state)
685 {
686
687 return 0;
688 }
689
690 static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = {
691 .atomic_check = dsi_encoder_atomic_check,
692 .mode_valid = dsi_encoder_mode_valid,
693 .mode_set = dsi_encoder_mode_set,
694 .enable = dsi_encoder_enable,
695 .disable = dsi_encoder_disable
696 };
697
698 static const struct drm_encoder_funcs dw_encoder_funcs = {
699 .destroy = drm_encoder_cleanup,
700 };
701
702 static int dw_drm_encoder_init(struct device *dev,
703 struct drm_device *drm_dev,
704 struct drm_encoder *encoder)
705 {
706 int ret;
707 u32 crtc_mask = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
708
709 if (!crtc_mask) {
710 DRM_ERROR("failed to find crtc mask\n");
711 return -EINVAL;
712 }
713
714 encoder->possible_crtcs = crtc_mask;
715 ret = drm_encoder_init(drm_dev, encoder, &dw_encoder_funcs,
716 DRM_MODE_ENCODER_DSI, NULL);
717 if (ret) {
718 DRM_ERROR("failed to init dsi encoder\n");
719 return ret;
720 }
721
722 drm_encoder_helper_add(encoder, &dw_encoder_helper_funcs);
723
724 return 0;
725 }
726
727 static int dsi_host_attach(struct mipi_dsi_host *host,
728 struct mipi_dsi_device *mdsi)
729 {
730 struct dw_dsi *dsi = host_to_dsi(host);
731
732 if (mdsi->lanes < 1 || mdsi->lanes > 4) {
733 DRM_ERROR("dsi device params invalid\n");
734 return -EINVAL;
735 }
736
737 dsi->lanes = mdsi->lanes;
738 dsi->format = mdsi->format;
739 dsi->mode_flags = mdsi->mode_flags;
740
741 return 0;
742 }
743
744 static int dsi_host_detach(struct mipi_dsi_host *host,
745 struct mipi_dsi_device *mdsi)
746 {
747
748 return 0;
749 }
750
751 static const struct mipi_dsi_host_ops dsi_host_ops = {
752 .attach = dsi_host_attach,
753 .detach = dsi_host_detach,
754 };
755
756 static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
757 {
758 struct mipi_dsi_host *host = &dsi->host;
759 int ret;
760
761 host->dev = dev;
762 host->ops = &dsi_host_ops;
763 ret = mipi_dsi_host_register(host);
764 if (ret) {
765 DRM_ERROR("failed to register dsi host\n");
766 return ret;
767 }
768
769 return 0;
770 }
771
772 static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi)
773 {
774 struct drm_encoder *encoder = &dsi->encoder;
775 struct drm_bridge *bridge = dsi->bridge;
776 int ret;
777
778
779 ret = drm_bridge_attach(encoder, bridge, NULL);
780 if (ret) {
781 DRM_ERROR("failed to attach external bridge\n");
782 return ret;
783 }
784
785 return 0;
786 }
787
788 static int dsi_bind(struct device *dev, struct device *master, void *data)
789 {
790 struct dsi_data *ddata = dev_get_drvdata(dev);
791 struct dw_dsi *dsi = &ddata->dsi;
792 struct drm_device *drm_dev = data;
793 int ret;
794
795 ret = dw_drm_encoder_init(dev, drm_dev, &dsi->encoder);
796 if (ret)
797 return ret;
798
799 ret = dsi_host_init(dev, dsi);
800 if (ret)
801 return ret;
802
803 ret = dsi_bridge_init(drm_dev, dsi);
804 if (ret)
805 return ret;
806
807 return 0;
808 }
809
810 static void dsi_unbind(struct device *dev, struct device *master, void *data)
811 {
812
813 }
814
815 static const struct component_ops dsi_ops = {
816 .bind = dsi_bind,
817 .unbind = dsi_unbind,
818 };
819
820 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
821 {
822 struct dsi_hw_ctx *ctx = dsi->ctx;
823 struct device_node *np = pdev->dev.of_node;
824 struct resource *res;
825 int ret;
826
827
828
829
830
831 ret = drm_of_find_panel_or_bridge(np, 1, 0, NULL, &dsi->bridge);
832 if (ret)
833 return ret;
834
835 ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
836 if (IS_ERR(ctx->pclk)) {
837 DRM_ERROR("failed to get pclk clock\n");
838 return PTR_ERR(ctx->pclk);
839 }
840
841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
842 ctx->base = devm_ioremap_resource(&pdev->dev, res);
843 if (IS_ERR(ctx->base)) {
844 DRM_ERROR("failed to remap dsi io region\n");
845 return PTR_ERR(ctx->base);
846 }
847
848 return 0;
849 }
850
851 static int dsi_probe(struct platform_device *pdev)
852 {
853 struct dsi_data *data;
854 struct dw_dsi *dsi;
855 struct dsi_hw_ctx *ctx;
856 int ret;
857
858 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
859 if (!data) {
860 DRM_ERROR("failed to allocate dsi data.\n");
861 return -ENOMEM;
862 }
863 dsi = &data->dsi;
864 ctx = &data->ctx;
865 dsi->ctx = ctx;
866
867 ret = dsi_parse_dt(pdev, dsi);
868 if (ret)
869 return ret;
870
871 platform_set_drvdata(pdev, data);
872
873 return component_add(&pdev->dev, &dsi_ops);
874 }
875
876 static int dsi_remove(struct platform_device *pdev)
877 {
878 component_del(&pdev->dev, &dsi_ops);
879
880 return 0;
881 }
882
883 static const struct of_device_id dsi_of_match[] = {
884 {.compatible = "hisilicon,hi6220-dsi"},
885 { }
886 };
887 MODULE_DEVICE_TABLE(of, dsi_of_match);
888
889 static struct platform_driver dsi_driver = {
890 .probe = dsi_probe,
891 .remove = dsi_remove,
892 .driver = {
893 .name = "dw-dsi",
894 .of_match_table = dsi_of_match,
895 },
896 };
897
898 module_platform_driver(dsi_driver);
899
900 MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
901 MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
902 MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
903 MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
904 MODULE_LICENSE("GPL v2");