1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef _DPU_HW_CATALOG_H
6 #define _DPU_HW_CATALOG_H
7
8 #include <linux/kernel.h>
9 #include <linux/bug.h>
10 #include <linux/bitmap.h>
11 #include <linux/err.h>
12
13 /**
14 * Max hardware block count: For ex: max 12 SSPP pipes or
15 * 5 ctl paths. In all cases, it can have max 12 hardware blocks
16 * based on current design
17 */
18 #define MAX_BLOCKS 12
19
20 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\
21 ((MINOR & 0xFFF) << 16) |\
22 (STEP & 0xFFFF))
23
24 #define DPU_HW_MAJOR(rev) ((rev) >> 28)
25 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF)
26 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF)
27 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16)
28
29 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \
30 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2)))
31
32 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */
33 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */
34 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */
35 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */
36 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */
37 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
38 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
39 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
40 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
41
42
43 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
44 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
45 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
46 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
47 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
48
49
50 #define DPU_HW_BLK_NAME_LEN 16
51
52 #define MAX_IMG_WIDTH 0x3fff
53 #define MAX_IMG_HEIGHT 0x3fff
54
55 #define CRTC_DUAL_MIXERS 2
56
57 #define MAX_XIN_COUNT 16
58
59 /**
60 * Supported UBWC feature versions
61 */
62 enum {
63 DPU_HW_UBWC_VER_10 = 0x100,
64 DPU_HW_UBWC_VER_20 = 0x200,
65 DPU_HW_UBWC_VER_30 = 0x300,
66 };
67
68 #define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20)
69
70 /**
71 * MDP TOP BLOCK features
72 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
73 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
74 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression.
75 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
76 * compression initial revision
77 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
78 * @DPU_MDP_MAX Maximum value
79
80 */
81 enum {
82 DPU_MDP_PANIC_PER_PIPE = 0x1,
83 DPU_MDP_10BIT_SUPPORT,
84 DPU_MDP_BWC,
85 DPU_MDP_UBWC_1_0,
86 DPU_MDP_UBWC_1_5,
87 DPU_MDP_MAX
88 };
89
90 /**
91 * SSPP sub-blocks/features
92 * @DPU_SSPP_SRC Src and fetch part of the pipes,
93 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support
94 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support
95 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes
96 * @DPU_SSPP_CSC, Support of Color space converion
97 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
98 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
99 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
100 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
101 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
102 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
103 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
104 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper
105 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
106 * @DPU_SSPP_CDP Supports client driven prefetch
107 * @DPU_SSPP_MAX maximum value
108 */
109 enum {
110 DPU_SSPP_SRC = 0x1,
111 DPU_SSPP_SCALER_QSEED2,
112 DPU_SSPP_SCALER_QSEED3,
113 DPU_SSPP_SCALER_RGB,
114 DPU_SSPP_CSC,
115 DPU_SSPP_CSC_10BIT,
116 DPU_SSPP_CURSOR,
117 DPU_SSPP_QOS,
118 DPU_SSPP_QOS_8LVL,
119 DPU_SSPP_EXCL_RECT,
120 DPU_SSPP_SMART_DMA_V1,
121 DPU_SSPP_SMART_DMA_V2,
122 DPU_SSPP_TS_PREFILL,
123 DPU_SSPP_TS_PREFILL_REC1,
124 DPU_SSPP_CDP,
125 DPU_SSPP_MAX
126 };
127
128 /*
129 * MIXER sub-blocks/features
130 * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
131 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
132 * @DPU_MIXER_GC Gamma correction block
133 * @DPU_DIM_LAYER Layer mixer supports dim layer
134 * @DPU_MIXER_MAX maximum value
135 */
136 enum {
137 DPU_MIXER_LAYER = 0x1,
138 DPU_MIXER_SOURCESPLIT,
139 DPU_MIXER_GC,
140 DPU_DIM_LAYER,
141 DPU_MIXER_MAX
142 };
143
144 /**
145 * PINGPONG sub-blocks
146 * @DPU_PINGPONG_TE Tear check block
147 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes
148 * @DPU_PINGPONG_SPLIT PP block supports split fifo
149 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
150 * @DPU_PINGPONG_DITHER, Dither blocks
151 * @DPU_PINGPONG_MAX
152 */
153 enum {
154 DPU_PINGPONG_TE = 0x1,
155 DPU_PINGPONG_TE2,
156 DPU_PINGPONG_SPLIT,
157 DPU_PINGPONG_SLAVE,
158 DPU_PINGPONG_DITHER,
159 DPU_PINGPONG_MAX
160 };
161
162 /**
163 * CTL sub-blocks
164 * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display
165 * @DPU_CTL_MAX
166 */
167 enum {
168 DPU_CTL_SPLIT_DISPLAY = 0x1,
169 DPU_CTL_MAX
170 };
171
172 /**
173 * VBIF sub-blocks and features
174 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit
175 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap
176 * @DPU_VBIF_MAX maximum value
177 */
178 enum {
179 DPU_VBIF_QOS_OTLIM = 0x1,
180 DPU_VBIF_QOS_REMAP,
181 DPU_VBIF_MAX
182 };
183
184 /**
185 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
186 * @name: string name for debug purposes
187 * @id: enum identifying this block
188 * @base: register base offset to mdss
189 * @len: length of hardware block
190 * @features bit mask identifying sub-blocks/features
191 */
192 #define DPU_HW_BLK_INFO \
193 char name[DPU_HW_BLK_NAME_LEN]; \
194 u32 id; \
195 u32 base; \
196 u32 len; \
197 unsigned long features
198
199 /**
200 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU
201 * @name: string name for debug purposes
202 * @id: enum identifying this sub-block
203 * @base: offset of this sub-block relative to the block
204 * offset
205 * @len register block length of this sub-block
206 */
207 #define DPU_HW_SUBBLK_INFO \
208 char name[DPU_HW_BLK_NAME_LEN]; \
209 u32 id; \
210 u32 base; \
211 u32 len
212
213 /**
214 * struct dpu_src_blk: SSPP part of the source pipes
215 * @info: HW register and features supported by this sub-blk
216 */
217 struct dpu_src_blk {
218 DPU_HW_SUBBLK_INFO;
219 };
220
221 /**
222 * struct dpu_scaler_blk: Scaler information
223 * @info: HW register and features supported by this sub-blk
224 * @version: qseed block revision
225 */
226 struct dpu_scaler_blk {
227 DPU_HW_SUBBLK_INFO;
228 u32 version;
229 };
230
231 struct dpu_csc_blk {
232 DPU_HW_SUBBLK_INFO;
233 };
234
235 /**
236 * struct dpu_pp_blk : Pixel processing sub-blk information
237 * @info: HW register and features supported by this sub-blk
238 * @version: HW Algorithm version
239 */
240 struct dpu_pp_blk {
241 DPU_HW_SUBBLK_INFO;
242 u32 version;
243 };
244
245 /**
246 * enum dpu_qos_lut_usage - define QoS LUT use cases
247 */
248 enum dpu_qos_lut_usage {
249 DPU_QOS_LUT_USAGE_LINEAR,
250 DPU_QOS_LUT_USAGE_MACROTILE,
251 DPU_QOS_LUT_USAGE_NRT,
252 DPU_QOS_LUT_USAGE_MAX,
253 };
254
255 /**
256 * struct dpu_qos_lut_entry - define QoS LUT table entry
257 * @fl: fill level, or zero on last entry to indicate default lut
258 * @lut: lut to use if equal to or less than fill level
259 */
260 struct dpu_qos_lut_entry {
261 u32 fl;
262 u64 lut;
263 };
264
265 /**
266 * struct dpu_qos_lut_tbl - define QoS LUT table
267 * @nentry: number of entry in this table
268 * @entries: Pointer to table entries
269 */
270 struct dpu_qos_lut_tbl {
271 u32 nentry;
272 struct dpu_qos_lut_entry *entries;
273 };
274
275 /**
276 * struct dpu_caps - define DPU capabilities
277 * @max_mixer_width max layer mixer line width support.
278 * @max_mixer_blendstages max layer mixer blend stages or
279 * supported z order
280 * @qseed_type qseed2 or qseed3 support.
281 * @smart_dma_rev Supported version of SmartDMA feature.
282 * @ubwc_version UBWC feature version (0x0 for not supported)
283 * @has_src_split source split feature status
284 * @has_dim_layer dim layer feature status
285 * @has_idle_pc indicate if idle power collapse feature is supported
286 */
287 struct dpu_caps {
288 u32 max_mixer_width;
289 u32 max_mixer_blendstages;
290 u32 qseed_type;
291 u32 smart_dma_rev;
292 u32 ubwc_version;
293 bool has_src_split;
294 bool has_dim_layer;
295 bool has_idle_pc;
296 };
297
298 /**
299 * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
300 * @maxwidth: max pixelwidth supported by this pipe
301 * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
302 * @maxhdeciexp: max horizontal decimation supported by this pipe
303 * (max is 2^value)
304 * @maxvdeciexp: max vertical decimation supported by this pipe
305 * (max is 2^value)
306 */
307 struct dpu_sspp_blks_common {
308 u32 maxlinewidth;
309 u32 pixel_ram_size;
310 u32 maxhdeciexp;
311 u32 maxvdeciexp;
312 };
313
314 /**
315 * struct dpu_sspp_sub_blks : SSPP sub-blocks
316 * common: Pointer to common configurations shared by sub blocks
317 * @creq_vblank: creq priority during vertical blanking
318 * @danger_vblank: danger priority during vertical blanking
319 * @maxdwnscale: max downscale ratio supported(without DECIMATION)
320 * @maxupscale: maxupscale ratio supported
321 * @smart_dma_priority: hw priority of rect1 of multirect pipe
322 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
323 * @src_blk:
324 * @scaler_blk:
325 * @csc_blk:
326 * @hsic:
327 * @memcolor:
328 * @pcc_blk:
329 * @igc_blk:
330 * @format_list: Pointer to list of supported formats
331 * @num_formats: Number of supported formats
332 * @virt_format_list: Pointer to list of supported formats for virtual planes
333 * @virt_num_formats: Number of supported formats for virtual planes
334 */
335 struct dpu_sspp_sub_blks {
336 const struct dpu_sspp_blks_common *common;
337 u32 creq_vblank;
338 u32 danger_vblank;
339 u32 maxdwnscale;
340 u32 maxupscale;
341 u32 smart_dma_priority;
342 u32 max_per_pipe_bw;
343 struct dpu_src_blk src_blk;
344 struct dpu_scaler_blk scaler_blk;
345 struct dpu_pp_blk csc_blk;
346 struct dpu_pp_blk hsic_blk;
347 struct dpu_pp_blk memcolor_blk;
348 struct dpu_pp_blk pcc_blk;
349 struct dpu_pp_blk igc_blk;
350
351 const u32 *format_list;
352 u32 num_formats;
353 const u32 *virt_format_list;
354 u32 virt_num_formats;
355 };
356
357 /**
358 * struct dpu_lm_sub_blks: information of mixer block
359 * @maxwidth: Max pixel width supported by this mixer
360 * @maxblendstages: Max number of blend-stages supported
361 * @blendstage_base: Blend-stage register base offset
362 * @gc: gamma correction block
363 */
364 struct dpu_lm_sub_blks {
365 u32 maxwidth;
366 u32 maxblendstages;
367 u32 blendstage_base[MAX_BLOCKS];
368 struct dpu_pp_blk gc;
369 };
370
371 struct dpu_pingpong_sub_blks {
372 struct dpu_pp_blk te;
373 struct dpu_pp_blk te2;
374 struct dpu_pp_blk dither;
375 };
376
377 /**
378 * dpu_clk_ctrl_type - Defines top level clock control signals
379 */
380 enum dpu_clk_ctrl_type {
381 DPU_CLK_CTRL_NONE,
382 DPU_CLK_CTRL_VIG0,
383 DPU_CLK_CTRL_VIG1,
384 DPU_CLK_CTRL_VIG2,
385 DPU_CLK_CTRL_VIG3,
386 DPU_CLK_CTRL_VIG4,
387 DPU_CLK_CTRL_RGB0,
388 DPU_CLK_CTRL_RGB1,
389 DPU_CLK_CTRL_RGB2,
390 DPU_CLK_CTRL_RGB3,
391 DPU_CLK_CTRL_DMA0,
392 DPU_CLK_CTRL_DMA1,
393 DPU_CLK_CTRL_CURSOR0,
394 DPU_CLK_CTRL_CURSOR1,
395 DPU_CLK_CTRL_INLINE_ROT0_SSPP,
396 DPU_CLK_CTRL_MAX,
397 };
398
399 /* struct dpu_clk_ctrl_reg : Clock control register
400 * @reg_off: register offset
401 * @bit_off: bit offset
402 */
403 struct dpu_clk_ctrl_reg {
404 u32 reg_off;
405 u32 bit_off;
406 };
407
408 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
409 * @id: index identifying this block
410 * @base: register base offset to mdss
411 * @features bit mask identifying sub-blocks/features
412 * @highest_bank_bit: UBWC parameter
413 * @ubwc_static: ubwc static configuration
414 * @ubwc_swizzle: ubwc default swizzle setting
415 * @clk_ctrls clock control register definition
416 */
417 struct dpu_mdp_cfg {
418 DPU_HW_BLK_INFO;
419 u32 highest_bank_bit;
420 u32 ubwc_static;
421 u32 ubwc_swizzle;
422 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
423 };
424
425 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
426 * @id: index identifying this block
427 * @base: register base offset to mdss
428 * @features bit mask identifying sub-blocks/features
429 */
430 struct dpu_ctl_cfg {
431 DPU_HW_BLK_INFO;
432 };
433
434 /**
435 * struct dpu_sspp_cfg - information of source pipes
436 * @id: index identifying this block
437 * @base register offset of this block
438 * @features bit mask identifying sub-blocks/features
439 * @sblk: SSPP sub-blocks information
440 * @xin_id: bus client identifier
441 * @clk_ctrl clock control identifier
442 * @type sspp type identifier
443 */
444 struct dpu_sspp_cfg {
445 DPU_HW_BLK_INFO;
446 const struct dpu_sspp_sub_blks *sblk;
447 u32 xin_id;
448 enum dpu_clk_ctrl_type clk_ctrl;
449 u32 type;
450 };
451
452 /**
453 * struct dpu_lm_cfg - information of layer mixer blocks
454 * @id: index identifying this block
455 * @base register offset of this block
456 * @features bit mask identifying sub-blocks/features
457 * @sblk: LM Sub-blocks information
458 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
459 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
460 */
461 struct dpu_lm_cfg {
462 DPU_HW_BLK_INFO;
463 const struct dpu_lm_sub_blks *sblk;
464 u32 pingpong;
465 unsigned long lm_pair_mask;
466 };
467
468 /**
469 * struct dpu_pingpong_cfg - information of PING-PONG blocks
470 * @id enum identifying this block
471 * @base register offset of this block
472 * @features bit mask identifying sub-blocks/features
473 * @sblk sub-blocks information
474 */
475 struct dpu_pingpong_cfg {
476 DPU_HW_BLK_INFO;
477 const struct dpu_pingpong_sub_blks *sblk;
478 };
479
480 /**
481 * struct dpu_intf_cfg - information of timing engine blocks
482 * @id enum identifying this block
483 * @base register offset of this block
484 * @features bit mask identifying sub-blocks/features
485 * @type: Interface type(DSI, DP, HDMI)
486 * @controller_id: Controller Instance ID in case of multiple of intf type
487 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
488 */
489 struct dpu_intf_cfg {
490 DPU_HW_BLK_INFO;
491 u32 type; /* interface type*/
492 u32 controller_id;
493 u32 prog_fetch_lines_worst_case;
494 };
495
496 /**
497 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
498 * @pps pixel per seconds
499 * @ot_limit OT limit to use up to specified pixel per second
500 */
501 struct dpu_vbif_dynamic_ot_cfg {
502 u64 pps;
503 u32 ot_limit;
504 };
505
506 /**
507 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
508 * @count length of cfg
509 * @cfg pointer to array of configuration settings with
510 * ascending requirements
511 */
512 struct dpu_vbif_dynamic_ot_tbl {
513 u32 count;
514 struct dpu_vbif_dynamic_ot_cfg *cfg;
515 };
516
517 /**
518 * struct dpu_vbif_qos_tbl - QoS priority table
519 * @npriority_lvl num of priority level
520 * @priority_lvl pointer to array of priority level in ascending order
521 */
522 struct dpu_vbif_qos_tbl {
523 u32 npriority_lvl;
524 u32 *priority_lvl;
525 };
526
527 /**
528 * struct dpu_vbif_cfg - information of VBIF blocks
529 * @id enum identifying this block
530 * @base register offset of this block
531 * @features bit mask identifying sub-blocks/features
532 * @ot_rd_limit default OT read limit
533 * @ot_wr_limit default OT write limit
534 * @xin_halt_timeout maximum time (in usec) for xin to halt
535 * @dynamic_ot_rd_tbl dynamic OT read configuration table
536 * @dynamic_ot_wr_tbl dynamic OT write configuration table
537 * @qos_rt_tbl real-time QoS priority table
538 * @qos_nrt_tbl non-real-time QoS priority table
539 * @memtype_count number of defined memtypes
540 * @memtype array of xin memtype definitions
541 */
542 struct dpu_vbif_cfg {
543 DPU_HW_BLK_INFO;
544 u32 default_ot_rd_limit;
545 u32 default_ot_wr_limit;
546 u32 xin_halt_timeout;
547 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
548 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
549 struct dpu_vbif_qos_tbl qos_rt_tbl;
550 struct dpu_vbif_qos_tbl qos_nrt_tbl;
551 u32 memtype_count;
552 u32 memtype[MAX_XIN_COUNT];
553 };
554 /**
555 * struct dpu_reg_dma_cfg - information of lut dma blocks
556 * @id enum identifying this block
557 * @base register offset of this block
558 * @features bit mask identifying sub-blocks/features
559 * @version version of lutdma hw block
560 * @trigger_sel_off offset to trigger select registers of lutdma
561 */
562 struct dpu_reg_dma_cfg {
563 DPU_HW_BLK_INFO;
564 u32 version;
565 u32 trigger_sel_off;
566 };
567
568 /**
569 * Define CDP use cases
570 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases
571 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
572 */
573 enum {
574 DPU_PERF_CDP_USAGE_RT,
575 DPU_PERF_CDP_USAGE_NRT,
576 DPU_PERF_CDP_USAGE_MAX
577 };
578
579 /**
580 * struct dpu_perf_cdp_cfg - define CDP use case configuration
581 * @rd_enable: true if read pipe CDP is enabled
582 * @wr_enable: true if write pipe CDP is enabled
583 */
584 struct dpu_perf_cdp_cfg {
585 bool rd_enable;
586 bool wr_enable;
587 };
588
589 /**
590 * struct dpu_perf_cfg - performance control settings
591 * @max_bw_low low threshold of maximum bandwidth (kbps)
592 * @max_bw_high high threshold of maximum bandwidth (kbps)
593 * @min_core_ib minimum bandwidth for core (kbps)
594 * @min_core_ib minimum mnoc ib vote in kbps
595 * @min_llcc_ib minimum llcc ib vote in kbps
596 * @min_dram_ib minimum dram ib vote in kbps
597 * @core_ib_ff core instantaneous bandwidth fudge factor
598 * @core_clk_ff core clock fudge factor
599 * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
600 * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
601 * @undersized_prefill_lines undersized prefill in lines
602 * @xtra_prefill_lines extra prefill latency in lines
603 * @dest_scale_prefill_lines destination scaler latency in lines
604 * @macrotile_perfill_lines macrotile latency in lines
605 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines
606 * @linear_prefill_lines linear latency in lines
607 * @downscaling_prefill_lines downscaling latency in lines
608 * @amortizable_theshold minimum y position for traffic shaping prefill
609 * @min_prefill_lines minimum pipeline latency in lines
610 * @safe_lut_tbl: LUT tables for safe signals
611 * @danger_lut_tbl: LUT tables for danger signals
612 * @qos_lut_tbl: LUT tables for QoS signals
613 * @cdp_cfg cdp use case configurations
614 */
615 struct dpu_perf_cfg {
616 u32 max_bw_low;
617 u32 max_bw_high;
618 u32 min_core_ib;
619 u32 min_llcc_ib;
620 u32 min_dram_ib;
621 const char *core_ib_ff;
622 const char *core_clk_ff;
623 const char *comp_ratio_rt;
624 const char *comp_ratio_nrt;
625 u32 undersized_prefill_lines;
626 u32 xtra_prefill_lines;
627 u32 dest_scale_prefill_lines;
628 u32 macrotile_prefill_lines;
629 u32 yuv_nv12_prefill_lines;
630 u32 linear_prefill_lines;
631 u32 downscaling_prefill_lines;
632 u32 amortizable_threshold;
633 u32 min_prefill_lines;
634 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
635 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
636 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
637 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
638 };
639
640 /**
641 * struct dpu_mdss_cfg - information of MDSS HW
642 * This is the main catalog data structure representing
643 * this HW version. Contains number of instances,
644 * register offsets, capabilities of the all MDSS HW sub-blocks.
645 *
646 * @dma_formats Supported formats for dma pipe
647 * @cursor_formats Supported formats for cursor pipe
648 * @vig_formats Supported formats for vig pipe
649 */
650 struct dpu_mdss_cfg {
651 u32 hwversion;
652
653 const struct dpu_caps *caps;
654
655 u32 mdp_count;
656 struct dpu_mdp_cfg *mdp;
657
658 u32 ctl_count;
659 struct dpu_ctl_cfg *ctl;
660
661 u32 sspp_count;
662 struct dpu_sspp_cfg *sspp;
663
664 u32 mixer_count;
665 struct dpu_lm_cfg *mixer;
666
667 u32 pingpong_count;
668 struct dpu_pingpong_cfg *pingpong;
669
670 u32 intf_count;
671 struct dpu_intf_cfg *intf;
672
673 u32 vbif_count;
674 struct dpu_vbif_cfg *vbif;
675
676 u32 reg_dma_count;
677 struct dpu_reg_dma_cfg dma_cfg;
678
679 u32 ad_count;
680
681 /* Add additional block data structures here */
682
683 struct dpu_perf_cfg perf;
684 struct dpu_format_extended *dma_formats;
685 struct dpu_format_extended *cursor_formats;
686 struct dpu_format_extended *vig_formats;
687 };
688
689 struct dpu_mdss_hw_cfg_handler {
690 u32 hw_rev;
691 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg);
692 };
693
694 /*
695 * Access Macros
696 */
697 #define BLK_MDP(s) ((s)->mdp)
698 #define BLK_CTL(s) ((s)->ctl)
699 #define BLK_VIG(s) ((s)->vig)
700 #define BLK_RGB(s) ((s)->rgb)
701 #define BLK_DMA(s) ((s)->dma)
702 #define BLK_CURSOR(s) ((s)->cursor)
703 #define BLK_MIXER(s) ((s)->mixer)
704 #define BLK_PINGPONG(s) ((s)->pingpong)
705 #define BLK_INTF(s) ((s)->intf)
706 #define BLK_AD(s) ((s)->ad)
707
708 /**
709 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
710 * hardcoded target specific catalog information in config structure
711 * @hw_rev: caller needs provide the hardware revision.
712 *
713 * Return: dpu config structure
714 */
715 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
716
717 /**
718 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup
719 * @dpu_cfg: pointer returned from init function
720 */
721 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
722
723 #endif /* _DPU_HW_CATALOG_H */