1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef _DPU_HW_SSPP_H
6 #define _DPU_HW_SSPP_H
7
8 #include "dpu_hw_catalog.h"
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_util.h"
11 #include "dpu_hw_blk.h"
12 #include "dpu_formats.h"
13
14 struct dpu_hw_pipe;
15
16 /**
17 * Flags
18 */
19 #define DPU_SSPP_FLIP_LR BIT(0)
20 #define DPU_SSPP_FLIP_UD BIT(1)
21 #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2)
22 #define DPU_SSPP_ROT_90 BIT(3)
23 #define DPU_SSPP_SOLID_FILL BIT(4)
24
25 /**
26 * Define all scaler feature bits in catalog
27 */
28 #define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \
29 (1UL << DPU_SSPP_SCALER_QSEED2) | \
30 (1UL << DPU_SSPP_SCALER_QSEED3))
31
32 /**
33 * Component indices
34 */
35 enum {
36 DPU_SSPP_COMP_0,
37 DPU_SSPP_COMP_1_2,
38 DPU_SSPP_COMP_2,
39 DPU_SSPP_COMP_3,
40
41 DPU_SSPP_COMP_MAX
42 };
43
44 /**
45 * DPU_SSPP_RECT_SOLO - multirect disabled
46 * DPU_SSPP_RECT_0 - rect0 of a multirect pipe
47 * DPU_SSPP_RECT_1 - rect1 of a multirect pipe
48 *
49 * Note: HW supports multirect with either RECT0 or
50 * RECT1. Considering no benefit of such configs over
51 * SOLO mode and to keep the plane management simple,
52 * we dont support single rect multirect configs.
53 */
54 enum dpu_sspp_multirect_index {
55 DPU_SSPP_RECT_SOLO = 0,
56 DPU_SSPP_RECT_0,
57 DPU_SSPP_RECT_1,
58 };
59
60 enum dpu_sspp_multirect_mode {
61 DPU_SSPP_MULTIRECT_NONE = 0,
62 DPU_SSPP_MULTIRECT_PARALLEL,
63 DPU_SSPP_MULTIRECT_TIME_MX,
64 };
65
66 enum {
67 DPU_FRAME_LINEAR,
68 DPU_FRAME_TILE_A4X,
69 DPU_FRAME_TILE_A5X,
70 };
71
72 enum dpu_hw_filter {
73 DPU_SCALE_FILTER_NEAREST = 0,
74 DPU_SCALE_FILTER_BIL,
75 DPU_SCALE_FILTER_PCMN,
76 DPU_SCALE_FILTER_CA,
77 DPU_SCALE_FILTER_MAX
78 };
79
80 enum dpu_hw_filter_alpa {
81 DPU_SCALE_ALPHA_PIXEL_REP,
82 DPU_SCALE_ALPHA_BIL
83 };
84
85 enum dpu_hw_filter_yuv {
86 DPU_SCALE_2D_4X4,
87 DPU_SCALE_2D_CIR,
88 DPU_SCALE_1D_SEP,
89 DPU_SCALE_BIL
90 };
91
92 struct dpu_hw_sharp_cfg {
93 u32 strength;
94 u32 edge_thr;
95 u32 smooth_thr;
96 u32 noise_thr;
97 };
98
99 struct dpu_hw_pixel_ext {
100 /* scaling factors are enabled for this input layer */
101 uint8_t enable_pxl_ext;
102
103 int init_phase_x[DPU_MAX_PLANES];
104 int phase_step_x[DPU_MAX_PLANES];
105 int init_phase_y[DPU_MAX_PLANES];
106 int phase_step_y[DPU_MAX_PLANES];
107
108 /*
109 * Number of pixels extension in left, right, top and bottom direction
110 * for all color components. This pixel value for each color component
111 * should be sum of fetch + repeat pixels.
112 */
113 int num_ext_pxls_left[DPU_MAX_PLANES];
114 int num_ext_pxls_right[DPU_MAX_PLANES];
115 int num_ext_pxls_top[DPU_MAX_PLANES];
116 int num_ext_pxls_btm[DPU_MAX_PLANES];
117
118 /*
119 * Number of pixels needs to be overfetched in left, right, top and
120 * bottom directions from source image for scaling.
121 */
122 int left_ftch[DPU_MAX_PLANES];
123 int right_ftch[DPU_MAX_PLANES];
124 int top_ftch[DPU_MAX_PLANES];
125 int btm_ftch[DPU_MAX_PLANES];
126
127 /*
128 * Number of pixels needs to be repeated in left, right, top and
129 * bottom directions for scaling.
130 */
131 int left_rpt[DPU_MAX_PLANES];
132 int right_rpt[DPU_MAX_PLANES];
133 int top_rpt[DPU_MAX_PLANES];
134 int btm_rpt[DPU_MAX_PLANES];
135
136 uint32_t roi_w[DPU_MAX_PLANES];
137 uint32_t roi_h[DPU_MAX_PLANES];
138
139 /*
140 * Filter type to be used for scaling in horizontal and vertical
141 * directions
142 */
143 enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
144 enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
145
146 };
147
148 /**
149 * struct dpu_hw_pipe_cfg : Pipe description
150 * @layout: format layout information for programming buffer to hardware
151 * @src_rect: src ROI, caller takes into account the different operations
152 * such as decimation, flip etc to program this field
153 * @dest_rect: destination ROI.
154 * @index: index of the rectangle of SSPP
155 * @mode: parallel or time multiplex multirect mode
156 */
157 struct dpu_hw_pipe_cfg {
158 struct dpu_hw_fmt_layout layout;
159 struct drm_rect src_rect;
160 struct drm_rect dst_rect;
161 enum dpu_sspp_multirect_index index;
162 enum dpu_sspp_multirect_mode mode;
163 };
164
165 /**
166 * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
167 * @danger_lut: LUT for generate danger level based on fill level
168 * @safe_lut: LUT for generate safe level based on fill level
169 * @creq_lut: LUT for generate creq level based on fill level
170 * @creq_vblank: creq value generated to vbif during vertical blanking
171 * @danger_vblank: danger value generated during vertical blanking
172 * @vblank_en: enable creq_vblank and danger_vblank during vblank
173 * @danger_safe_en: enable danger safe generation
174 */
175 struct dpu_hw_pipe_qos_cfg {
176 u32 danger_lut;
177 u32 safe_lut;
178 u64 creq_lut;
179 u32 creq_vblank;
180 u32 danger_vblank;
181 bool vblank_en;
182 bool danger_safe_en;
183 };
184
185 /**
186 * enum CDP preload ahead address size
187 */
188 enum {
189 DPU_SSPP_CDP_PRELOAD_AHEAD_32,
190 DPU_SSPP_CDP_PRELOAD_AHEAD_64
191 };
192
193 /**
194 * struct dpu_hw_pipe_cdp_cfg : CDP configuration
195 * @enable: true to enable CDP
196 * @ubwc_meta_enable: true to enable ubwc metadata preload
197 * @tile_amortize_enable: true to enable amortization control for tile format
198 * @preload_ahead: number of request to preload ahead
199 * DPU_SSPP_CDP_PRELOAD_AHEAD_32,
200 * DPU_SSPP_CDP_PRELOAD_AHEAD_64
201 */
202 struct dpu_hw_pipe_cdp_cfg {
203 bool enable;
204 bool ubwc_meta_enable;
205 bool tile_amortize_enable;
206 u32 preload_ahead;
207 };
208
209 /**
210 * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
211 * @size: size to prefill in bytes, or zero to disable
212 * @time: time to prefill in usec, or zero to disable
213 */
214 struct dpu_hw_pipe_ts_cfg {
215 u64 size;
216 u64 time;
217 };
218
219 /**
220 * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
221 * Caller must call the init function to get the pipe context for each pipe
222 * Assumption is these functions will be called after clocks are enabled
223 */
224 struct dpu_hw_sspp_ops {
225 /**
226 * setup_format - setup pixel format cropping rectangle, flip
227 * @ctx: Pointer to pipe context
228 * @cfg: Pointer to pipe config structure
229 * @flags: Extra flags for format config
230 * @index: rectangle index in multirect
231 */
232 void (*setup_format)(struct dpu_hw_pipe *ctx,
233 const struct dpu_format *fmt, u32 flags,
234 enum dpu_sspp_multirect_index index);
235
236 /**
237 * setup_rects - setup pipe ROI rectangles
238 * @ctx: Pointer to pipe context
239 * @cfg: Pointer to pipe config structure
240 * @index: rectangle index in multirect
241 */
242 void (*setup_rects)(struct dpu_hw_pipe *ctx,
243 struct dpu_hw_pipe_cfg *cfg,
244 enum dpu_sspp_multirect_index index);
245
246 /**
247 * setup_pe - setup pipe pixel extension
248 * @ctx: Pointer to pipe context
249 * @pe_ext: Pointer to pixel ext settings
250 */
251 void (*setup_pe)(struct dpu_hw_pipe *ctx,
252 struct dpu_hw_pixel_ext *pe_ext);
253
254 /**
255 * setup_sourceaddress - setup pipe source addresses
256 * @ctx: Pointer to pipe context
257 * @cfg: Pointer to pipe config structure
258 * @index: rectangle index in multirect
259 */
260 void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
261 struct dpu_hw_pipe_cfg *cfg,
262 enum dpu_sspp_multirect_index index);
263
264 /**
265 * setup_csc - setup color space coversion
266 * @ctx: Pointer to pipe context
267 * @data: Pointer to config structure
268 */
269 void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data);
270
271 /**
272 * setup_solidfill - enable/disable colorfill
273 * @ctx: Pointer to pipe context
274 * @const_color: Fill color value
275 * @flags: Pipe flags
276 * @index: rectangle index in multirect
277 */
278 void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
279 enum dpu_sspp_multirect_index index);
280
281 /**
282 * setup_multirect - setup multirect configuration
283 * @ctx: Pointer to pipe context
284 * @index: rectangle index in multirect
285 * @mode: parallel fetch / time multiplex multirect mode
286 */
287
288 void (*setup_multirect)(struct dpu_hw_pipe *ctx,
289 enum dpu_sspp_multirect_index index,
290 enum dpu_sspp_multirect_mode mode);
291
292 /**
293 * setup_sharpening - setup sharpening
294 * @ctx: Pointer to pipe context
295 * @cfg: Pointer to config structure
296 */
297 void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
298 struct dpu_hw_sharp_cfg *cfg);
299
300 /**
301 * setup_danger_safe_lut - setup danger safe LUTs
302 * @ctx: Pointer to pipe context
303 * @cfg: Pointer to pipe QoS configuration
304 *
305 */
306 void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
307 struct dpu_hw_pipe_qos_cfg *cfg);
308
309 /**
310 * setup_creq_lut - setup CREQ LUT
311 * @ctx: Pointer to pipe context
312 * @cfg: Pointer to pipe QoS configuration
313 *
314 */
315 void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
316 struct dpu_hw_pipe_qos_cfg *cfg);
317
318 /**
319 * setup_qos_ctrl - setup QoS control
320 * @ctx: Pointer to pipe context
321 * @cfg: Pointer to pipe QoS configuration
322 *
323 */
324 void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
325 struct dpu_hw_pipe_qos_cfg *cfg);
326
327 /**
328 * setup_histogram - setup histograms
329 * @ctx: Pointer to pipe context
330 * @cfg: Pointer to histogram configuration
331 */
332 void (*setup_histogram)(struct dpu_hw_pipe *ctx,
333 void *cfg);
334
335 /**
336 * setup_scaler - setup scaler
337 * @ctx: Pointer to pipe context
338 * @pipe_cfg: Pointer to pipe configuration
339 * @pe_cfg: Pointer to pixel extension configuration
340 * @scaler_cfg: Pointer to scaler configuration
341 */
342 void (*setup_scaler)(struct dpu_hw_pipe *ctx,
343 struct dpu_hw_pipe_cfg *pipe_cfg,
344 struct dpu_hw_pixel_ext *pe_cfg,
345 void *scaler_cfg);
346
347 /**
348 * get_scaler_ver - get scaler h/w version
349 * @ctx: Pointer to pipe context
350 */
351 u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
352
353 /**
354 * setup_cdp - setup client driven prefetch
355 * @ctx: Pointer to pipe context
356 * @cfg: Pointer to cdp configuration
357 */
358 void (*setup_cdp)(struct dpu_hw_pipe *ctx,
359 struct dpu_hw_pipe_cdp_cfg *cfg);
360 };
361
362 /**
363 * struct dpu_hw_pipe - pipe description
364 * @base: hardware block base structure
365 * @hw: block hardware details
366 * @catalog: back pointer to catalog
367 * @mdp: pointer to associated mdp portion of the catalog
368 * @idx: pipe index
369 * @cap: pointer to layer_cfg
370 * @ops: pointer to operations possible for this pipe
371 */
372 struct dpu_hw_pipe {
373 struct dpu_hw_blk base;
374 struct dpu_hw_blk_reg_map hw;
375 struct dpu_mdss_cfg *catalog;
376 struct dpu_mdp_cfg *mdp;
377
378 /* Pipe */
379 enum dpu_sspp idx;
380 const struct dpu_sspp_cfg *cap;
381
382 /* Ops */
383 struct dpu_hw_sspp_ops ops;
384 };
385
386 /**
387 * dpu_hw_sspp_init - initializes the sspp hw driver object.
388 * Should be called once before accessing every pipe.
389 * @idx: Pipe index for which driver object is required
390 * @addr: Mapped register io address of MDP
391 * @catalog : Pointer to mdss catalog data
392 * @is_virtual_pipe: is this pipe virtual pipe
393 */
394 struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
395 void __iomem *addr, struct dpu_mdss_cfg *catalog,
396 bool is_virtual_pipe);
397
398 /**
399 * dpu_hw_sspp_destroy(): Destroys SSPP driver context
400 * should be called during Hw pipe cleanup.
401 * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
402 */
403 void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
404
405 #endif /*_DPU_HW_SSPP_H */
406