This source file includes following definitions.
- max_mbps_to_parameter
- dsi_write
- dsi_read
- dsi_set
- dsi_update_bits
- dw_mipi_dsi_phy_write
- ns2bc
- ns2ui
- dw_mipi_dsi_phy_init
- dw_mipi_dsi_get_lane_mbps
- dw_mipi_dsi_rockchip_config
- dw_mipi_dsi_encoder_atomic_check
- dw_mipi_dsi_encoder_enable
- dw_mipi_dsi_encoder_disable
- rockchip_dsi_drm_create_encoder
- dw_mipi_dsi_rockchip_find_second
- dw_mipi_dsi_rockchip_bind
- dw_mipi_dsi_rockchip_unbind
- dw_mipi_dsi_rockchip_host_attach
- dw_mipi_dsi_rockchip_host_detach
- dw_mipi_dsi_rockchip_probe
- dw_mipi_dsi_rockchip_remove
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8
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/math64.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17
18 #include <video/mipi_display.h>
19
20 #include <drm/bridge/dw_mipi_dsi.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_of.h>
23
24 #include "rockchip_drm_drv.h"
25 #include "rockchip_drm_vop.h"
26
27 #define DSI_PHY_RSTZ 0xa0
28 #define PHY_DISFORCEPLL 0
29 #define PHY_ENFORCEPLL BIT(3)
30 #define PHY_DISABLECLK 0
31 #define PHY_ENABLECLK BIT(2)
32 #define PHY_RSTZ 0
33 #define PHY_UNRSTZ BIT(1)
34 #define PHY_SHUTDOWNZ 0
35 #define PHY_UNSHUTDOWNZ BIT(0)
36
37 #define DSI_PHY_IF_CFG 0xa4
38 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
39 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
40
41 #define DSI_PHY_STATUS 0xb0
42 #define LOCK BIT(0)
43 #define STOP_STATE_CLK_LANE BIT(2)
44
45 #define DSI_PHY_TST_CTRL0 0xb4
46 #define PHY_TESTCLK BIT(1)
47 #define PHY_UNTESTCLK 0
48 #define PHY_TESTCLR BIT(0)
49 #define PHY_UNTESTCLR 0
50
51 #define DSI_PHY_TST_CTRL1 0xb8
52 #define PHY_TESTEN BIT(16)
53 #define PHY_UNTESTEN 0
54 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
55 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
56
57 #define DSI_INT_ST0 0xbc
58 #define DSI_INT_ST1 0xc0
59 #define DSI_INT_MSK0 0xc4
60 #define DSI_INT_MSK1 0xc8
61
62 #define PHY_STATUS_TIMEOUT_US 10000
63 #define CMD_PKT_STATUS_TIMEOUT_US 20000
64
65 #define BYPASS_VCO_RANGE BIT(7)
66 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
67 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
68 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
69 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
70 #define REF_BIAS_CUR_SEL BIT(0)
71
72 #define CP_CURRENT_3UA 0x1
73 #define CP_CURRENT_4_5UA 0x2
74 #define CP_CURRENT_7_5UA 0x6
75 #define CP_CURRENT_6UA 0x9
76 #define CP_CURRENT_12UA 0xb
77 #define CP_CURRENT_SEL(val) ((val) & 0xf)
78 #define CP_PROGRAM_EN BIT(7)
79
80 #define LPF_RESISTORS_15_5KOHM 0x1
81 #define LPF_RESISTORS_13KOHM 0x2
82 #define LPF_RESISTORS_11_5KOHM 0x4
83 #define LPF_RESISTORS_10_5KOHM 0x8
84 #define LPF_RESISTORS_8KOHM 0x10
85 #define LPF_PROGRAM_EN BIT(6)
86 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
87
88 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
89
90 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
91 #define LOW_PROGRAM_EN 0
92 #define HIGH_PROGRAM_EN BIT(7)
93 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
94 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
95 #define PLL_LOOP_DIV_EN BIT(5)
96 #define PLL_INPUT_DIV_EN BIT(4)
97
98 #define POWER_CONTROL BIT(6)
99 #define INTERNAL_REG_CURRENT BIT(3)
100 #define BIAS_BLOCK_ON BIT(2)
101 #define BANDGAP_ON BIT(0)
102
103 #define TER_RESISTOR_HIGH BIT(7)
104 #define TER_RESISTOR_LOW 0
105 #define LEVEL_SHIFTERS_ON BIT(6)
106 #define TER_CAL_DONE BIT(5)
107 #define SETRD_MAX (0x7 << 2)
108 #define POWER_MANAGE BIT(1)
109 #define TER_RESISTORS_ON BIT(0)
110
111 #define BIASEXTR_SEL(val) ((val) & 0x7)
112 #define BANDGAP_SEL(val) ((val) & 0x7)
113 #define TLP_PROGRAM_EN BIT(7)
114 #define THS_PRE_PROGRAM_EN BIT(7)
115 #define THS_ZERO_PROGRAM_EN BIT(6)
116
117 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
118 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
119 #define PLL_LPF_AND_CP_CONTROL 0x12
120 #define PLL_INPUT_DIVIDER_RATIO 0x17
121 #define PLL_LOOP_DIVIDER_RATIO 0x18
122 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
123 #define BANDGAP_AND_BIAS_CONTROL 0x20
124 #define TERMINATION_RESISTER_CONTROL 0x21
125 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
126 #define HS_RX_CONTROL_OF_LANE_0 0x44
127 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
128 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
129 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
130 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
131 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
132 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
133 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
134 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
135 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
136 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
137 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
138
139 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
140 #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
141
142 #define RK3288_GRF_SOC_CON6 0x025c
143 #define RK3288_DSI0_LCDC_SEL BIT(6)
144 #define RK3288_DSI1_LCDC_SEL BIT(9)
145
146 #define RK3399_GRF_SOC_CON20 0x6250
147 #define RK3399_DSI0_LCDC_SEL BIT(0)
148 #define RK3399_DSI1_LCDC_SEL BIT(4)
149
150 #define RK3399_GRF_SOC_CON22 0x6258
151 #define RK3399_DSI0_TURNREQUEST (0xf << 12)
152 #define RK3399_DSI0_TURNDISABLE (0xf << 8)
153 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
154 #define RK3399_DSI0_FORCERXMODE (0xf << 0)
155
156 #define RK3399_GRF_SOC_CON23 0x625c
157 #define RK3399_DSI1_TURNDISABLE (0xf << 12)
158 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
159 #define RK3399_DSI1_FORCERXMODE (0xf << 4)
160 #define RK3399_DSI1_ENABLE (0xf << 0)
161
162 #define RK3399_GRF_SOC_CON24 0x6260
163 #define RK3399_TXRX_MASTERSLAVEZ BIT(7)
164 #define RK3399_TXRX_ENABLECLK BIT(6)
165 #define RK3399_TXRX_BASEDIR BIT(5)
166
167 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
168
169 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
170
171 enum {
172 BANDGAP_97_07,
173 BANDGAP_98_05,
174 BANDGAP_99_02,
175 BANDGAP_100_00,
176 BANDGAP_93_17,
177 BANDGAP_94_15,
178 BANDGAP_95_12,
179 BANDGAP_96_10,
180 };
181
182 enum {
183 BIASEXTR_87_1,
184 BIASEXTR_91_5,
185 BIASEXTR_95_9,
186 BIASEXTR_100,
187 BIASEXTR_105_94,
188 BIASEXTR_111_88,
189 BIASEXTR_118_8,
190 BIASEXTR_127_7,
191 };
192
193 struct rockchip_dw_dsi_chip_data {
194 u32 reg;
195
196 u32 lcdsel_grf_reg;
197 u32 lcdsel_big;
198 u32 lcdsel_lit;
199
200 u32 enable_grf_reg;
201 u32 enable;
202
203 u32 lanecfg1_grf_reg;
204 u32 lanecfg1;
205 u32 lanecfg2_grf_reg;
206 u32 lanecfg2;
207
208 unsigned int flags;
209 unsigned int max_data_lanes;
210 };
211
212 struct dw_mipi_dsi_rockchip {
213 struct device *dev;
214 struct drm_encoder encoder;
215 void __iomem *base;
216
217 struct regmap *grf_regmap;
218 struct clk *pllref_clk;
219 struct clk *grf_clk;
220 struct clk *phy_cfg_clk;
221
222
223 bool is_slave;
224 struct dw_mipi_dsi_rockchip *slave;
225
226 unsigned int lane_mbps;
227 u16 input_div;
228 u16 feedback_div;
229 u32 format;
230
231 struct dw_mipi_dsi *dmd;
232 const struct rockchip_dw_dsi_chip_data *cdata;
233 struct dw_mipi_dsi_plat_data pdata;
234 int devcnt;
235 };
236
237 struct dphy_pll_parameter_map {
238 unsigned int max_mbps;
239 u8 hsfreqrange;
240 u8 icpctrl;
241 u8 lpfctrl;
242 };
243
244
245 static const struct dphy_pll_parameter_map dppa_map[] = {
246 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
247 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
248 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
249 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
250 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
251 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
252 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
253 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
254 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
255 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
256 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
257 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
258 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
259 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
260 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
261 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
262 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
263 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
264 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
265 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
266 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
267 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
268 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
269 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
270 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
271 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
272 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
273 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
274 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
275 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
276 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
277 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
278 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
279 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
280 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
281 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
282 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
283 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
284 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
285 };
286
287 static int max_mbps_to_parameter(unsigned int max_mbps)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
292 if (dppa_map[i].max_mbps >= max_mbps)
293 return i;
294
295 return -EINVAL;
296 }
297
298 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
299 {
300 writel(val, dsi->base + reg);
301 }
302
303 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
304 {
305 return readl(dsi->base + reg);
306 }
307
308 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
309 {
310 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
311 }
312
313 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
314 u32 mask, u32 val)
315 {
316 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
317 }
318
319 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
320 u8 test_code,
321 u8 test_data)
322 {
323
324
325
326
327
328 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
329
330 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
331 PHY_TESTDIN(test_code));
332
333 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
334
335 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
336 PHY_TESTDIN(test_data));
337
338 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
339 }
340
341
342
343
344 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
345 {
346 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
347 }
348
349
350
351
352 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
353 {
354 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
355 }
356
357 static int dw_mipi_dsi_phy_init(void *priv_data)
358 {
359 struct dw_mipi_dsi_rockchip *dsi = priv_data;
360 int ret, i, vco;
361
362
363
364
365
366
367
368
369
370
371
372
373
374 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
375
376 i = max_mbps_to_parameter(dsi->lane_mbps);
377 if (i < 0) {
378 DRM_DEV_ERROR(dsi->dev,
379 "failed to get parameter for %dmbps clock\n",
380 dsi->lane_mbps);
381 return i;
382 }
383
384 ret = clk_prepare_enable(dsi->phy_cfg_clk);
385 if (ret) {
386 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
387 return ret;
388 }
389
390 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
391 BYPASS_VCO_RANGE |
392 VCO_RANGE_CON_SEL(vco) |
393 VCO_IN_CAP_CON_LOW |
394 REF_BIAS_CUR_SEL);
395
396 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
397 CP_CURRENT_SEL(dppa_map[i].icpctrl));
398 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
399 CP_PROGRAM_EN | LPF_PROGRAM_EN |
400 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
401
402 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
403 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
404
405 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
406 INPUT_DIVIDER(dsi->input_div));
407 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
408 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
409 LOW_PROGRAM_EN);
410
411
412
413
414
415
416 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
417 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
418 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
419 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
420 HIGH_PROGRAM_EN);
421 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
422 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
423
424 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
425 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
426 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
427 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
428
429 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
430 POWER_CONTROL | INTERNAL_REG_CURRENT |
431 BIAS_BLOCK_ON | BANDGAP_ON);
432
433 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
434 TER_RESISTOR_LOW | TER_CAL_DONE |
435 SETRD_MAX | TER_RESISTORS_ON);
436 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
437 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
438 SETRD_MAX | POWER_MANAGE |
439 TER_RESISTORS_ON);
440
441 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
442 TLP_PROGRAM_EN | ns2bc(dsi, 500));
443 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
444 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
445 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
446 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
447 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
448 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
449 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
450 BIT(5) | ns2bc(dsi, 100));
451 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
452 BIT(5) | (ns2bc(dsi, 60) + 7));
453
454 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
455 TLP_PROGRAM_EN | ns2bc(dsi, 500));
456 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
457 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
458 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
459 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
460 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
461 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
462 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
463 BIT(5) | ns2bc(dsi, 100));
464
465 clk_disable_unprepare(dsi->phy_cfg_clk);
466
467 return ret;
468 }
469
470 static int
471 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
472 unsigned long mode_flags, u32 lanes, u32 format,
473 unsigned int *lane_mbps)
474 {
475 struct dw_mipi_dsi_rockchip *dsi = priv_data;
476 int bpp;
477 unsigned long mpclk, tmp;
478 unsigned int target_mbps = 1000;
479 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
480 unsigned long best_freq = 0;
481 unsigned long fvco_min, fvco_max, fin, fout;
482 unsigned int min_prediv, max_prediv;
483 unsigned int _prediv, uninitialized_var(best_prediv);
484 unsigned long _fbdiv, uninitialized_var(best_fbdiv);
485 unsigned long min_delta = ULONG_MAX;
486
487 dsi->format = format;
488 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
489 if (bpp < 0) {
490 DRM_DEV_ERROR(dsi->dev,
491 "failed to get bpp for pixel format %d\n",
492 dsi->format);
493 return bpp;
494 }
495
496 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
497 if (mpclk) {
498
499 tmp = mpclk * (bpp / lanes) * 10 / 8;
500 if (tmp < max_mbps)
501 target_mbps = tmp;
502 else
503 DRM_DEV_ERROR(dsi->dev,
504 "DPHY clock frequency is out of range\n");
505 }
506
507 fin = clk_get_rate(dsi->pllref_clk);
508 fout = target_mbps * USEC_PER_SEC;
509
510
511 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
512 max_prediv = fin / (5 * USEC_PER_SEC);
513
514
515 fvco_min = 80 * USEC_PER_SEC;
516 fvco_max = 1500 * USEC_PER_SEC;
517
518 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
519 u64 tmp;
520 u32 delta;
521
522 tmp = (u64)fout * _prediv;
523 do_div(tmp, fin);
524 _fbdiv = tmp;
525
526
527
528
529
530 if (_fbdiv < 6 || _fbdiv > 512)
531 continue;
532
533 _fbdiv += _fbdiv % 2;
534
535 tmp = (u64)_fbdiv * fin;
536 do_div(tmp, _prediv);
537 if (tmp < fvco_min || tmp > fvco_max)
538 continue;
539
540 delta = abs(fout - tmp);
541 if (delta < min_delta) {
542 best_prediv = _prediv;
543 best_fbdiv = _fbdiv;
544 min_delta = delta;
545 best_freq = tmp;
546 }
547 }
548
549 if (best_freq) {
550 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
551 *lane_mbps = dsi->lane_mbps;
552 dsi->input_div = best_prediv;
553 dsi->feedback_div = best_fbdiv;
554 } else {
555 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
556 return -EINVAL;
557 }
558
559 return 0;
560 }
561
562 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
563 .init = dw_mipi_dsi_phy_init,
564 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
565 };
566
567 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
568 int mux)
569 {
570 if (dsi->cdata->lcdsel_grf_reg)
571 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
572 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
573
574 if (dsi->cdata->lanecfg1_grf_reg)
575 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
576 dsi->cdata->lanecfg1);
577
578 if (dsi->cdata->lanecfg2_grf_reg)
579 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
580 dsi->cdata->lanecfg2);
581
582 if (dsi->cdata->enable_grf_reg)
583 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
584 dsi->cdata->enable);
585 }
586
587 static int
588 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
589 struct drm_crtc_state *crtc_state,
590 struct drm_connector_state *conn_state)
591 {
592 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
593 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
594
595 switch (dsi->format) {
596 case MIPI_DSI_FMT_RGB888:
597 s->output_mode = ROCKCHIP_OUT_MODE_P888;
598 break;
599 case MIPI_DSI_FMT_RGB666:
600 s->output_mode = ROCKCHIP_OUT_MODE_P666;
601 break;
602 case MIPI_DSI_FMT_RGB565:
603 s->output_mode = ROCKCHIP_OUT_MODE_P565;
604 break;
605 default:
606 WARN_ON(1);
607 return -EINVAL;
608 }
609
610 s->output_type = DRM_MODE_CONNECTOR_DSI;
611 if (dsi->slave)
612 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
613
614 return 0;
615 }
616
617 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
618 {
619 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
620 int ret, mux;
621
622 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
623 &dsi->encoder);
624 if (mux < 0)
625 return;
626
627 pm_runtime_get_sync(dsi->dev);
628 if (dsi->slave)
629 pm_runtime_get_sync(dsi->slave->dev);
630
631
632
633
634
635
636 ret = clk_prepare_enable(dsi->grf_clk);
637 if (ret) {
638 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
639 return;
640 }
641
642 dw_mipi_dsi_rockchip_config(dsi, mux);
643 if (dsi->slave)
644 dw_mipi_dsi_rockchip_config(dsi->slave, mux);
645
646 clk_disable_unprepare(dsi->grf_clk);
647 }
648
649 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
650 {
651 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
652
653 if (dsi->slave)
654 pm_runtime_put(dsi->slave->dev);
655 pm_runtime_put(dsi->dev);
656 }
657
658 static const struct drm_encoder_helper_funcs
659 dw_mipi_dsi_encoder_helper_funcs = {
660 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
661 .enable = dw_mipi_dsi_encoder_enable,
662 .disable = dw_mipi_dsi_encoder_disable,
663 };
664
665 static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
666 .destroy = drm_encoder_cleanup,
667 };
668
669 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
670 struct drm_device *drm_dev)
671 {
672 struct drm_encoder *encoder = &dsi->encoder;
673 int ret;
674
675 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
676 dsi->dev->of_node);
677
678 ret = drm_encoder_init(drm_dev, encoder, &dw_mipi_dsi_encoder_funcs,
679 DRM_MODE_ENCODER_DSI, NULL);
680 if (ret) {
681 DRM_ERROR("Failed to initialize encoder with drm\n");
682 return ret;
683 }
684
685 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
686
687 return 0;
688 }
689
690 static struct device
691 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
692 {
693 const struct of_device_id *match;
694 struct device_node *node = NULL, *local;
695
696 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
697
698 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
699 if (!local)
700 return NULL;
701
702 while ((node = of_find_compatible_node(node, NULL,
703 match->compatible))) {
704 struct device_node *remote;
705
706
707 if (node == dsi->dev->of_node)
708 continue;
709
710 remote = of_graph_get_remote_node(node, 1, 0);
711 if (!remote)
712 continue;
713
714
715 if (remote == local) {
716 struct dw_mipi_dsi_rockchip *dsi2;
717 struct platform_device *pdev;
718
719 pdev = of_find_device_by_node(node);
720
721
722
723
724
725
726 of_node_put(remote);
727 of_node_put(node);
728 of_node_put(local);
729
730 if (!pdev)
731 return ERR_PTR(-EPROBE_DEFER);
732
733 dsi2 = platform_get_drvdata(pdev);
734 if (!dsi2) {
735 platform_device_put(pdev);
736 return ERR_PTR(-EPROBE_DEFER);
737 }
738
739 return &pdev->dev;
740 }
741
742 of_node_put(remote);
743 }
744
745 of_node_put(local);
746
747 return NULL;
748 }
749
750 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
751 struct device *master,
752 void *data)
753 {
754 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
755 struct drm_device *drm_dev = data;
756 struct device *second;
757 bool master1, master2;
758 int ret;
759
760 second = dw_mipi_dsi_rockchip_find_second(dsi);
761 if (IS_ERR(second))
762 return PTR_ERR(second);
763
764 if (second) {
765 master1 = of_property_read_bool(dsi->dev->of_node,
766 "clock-master");
767 master2 = of_property_read_bool(second->of_node,
768 "clock-master");
769
770 if (master1 && master2) {
771 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
772 return -EINVAL;
773 }
774
775 if (!master1 && !master2) {
776 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
777 return -EINVAL;
778 }
779
780
781 if (!master1) {
782 dsi->is_slave = true;
783 return 0;
784 }
785
786 dsi->slave = dev_get_drvdata(second);
787 if (!dsi->slave) {
788 DRM_DEV_ERROR(dev, "could not get slaves data\n");
789 return -ENODEV;
790 }
791
792 dsi->slave->is_slave = true;
793 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
794 put_device(second);
795 }
796
797 ret = clk_prepare_enable(dsi->pllref_clk);
798 if (ret) {
799 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
800 return ret;
801 }
802
803 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
804 if (ret) {
805 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
806 return ret;
807 }
808
809 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
810 if (ret) {
811 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
812 return ret;
813 }
814
815 return 0;
816 }
817
818 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
819 struct device *master,
820 void *data)
821 {
822 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
823
824 if (dsi->is_slave)
825 return;
826
827 dw_mipi_dsi_unbind(dsi->dmd);
828
829 clk_disable_unprepare(dsi->pllref_clk);
830 }
831
832 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
833 .bind = dw_mipi_dsi_rockchip_bind,
834 .unbind = dw_mipi_dsi_rockchip_unbind,
835 };
836
837 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
838 struct mipi_dsi_device *device)
839 {
840 struct dw_mipi_dsi_rockchip *dsi = priv_data;
841 struct device *second;
842 int ret;
843
844 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
845 if (ret) {
846 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
847 ret);
848 return ret;
849 }
850
851 second = dw_mipi_dsi_rockchip_find_second(dsi);
852 if (IS_ERR(second))
853 return PTR_ERR(second);
854 if (second) {
855 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
856 if (ret) {
857 DRM_DEV_ERROR(second,
858 "Failed to register component: %d\n",
859 ret);
860 return ret;
861 }
862 }
863
864 return 0;
865 }
866
867 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
868 struct mipi_dsi_device *device)
869 {
870 struct dw_mipi_dsi_rockchip *dsi = priv_data;
871 struct device *second;
872
873 second = dw_mipi_dsi_rockchip_find_second(dsi);
874 if (second && !IS_ERR(second))
875 component_del(second, &dw_mipi_dsi_rockchip_ops);
876
877 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
878
879 return 0;
880 }
881
882 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
883 .attach = dw_mipi_dsi_rockchip_host_attach,
884 .detach = dw_mipi_dsi_rockchip_host_detach,
885 };
886
887 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
888 {
889 struct device *dev = &pdev->dev;
890 struct device_node *np = dev->of_node;
891 struct dw_mipi_dsi_rockchip *dsi;
892 struct resource *res;
893 const struct rockchip_dw_dsi_chip_data *cdata =
894 of_device_get_match_data(dev);
895 int ret, i;
896
897 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
898 if (!dsi)
899 return -ENOMEM;
900
901 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 dsi->base = devm_ioremap_resource(dev, res);
903 if (IS_ERR(dsi->base)) {
904 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
905 return PTR_ERR(dsi->base);
906 }
907
908 i = 0;
909 while (cdata[i].reg) {
910 if (cdata[i].reg == res->start) {
911 dsi->cdata = &cdata[i];
912 break;
913 }
914
915 i++;
916 }
917
918 if (!dsi->cdata) {
919 dev_err(dev, "no dsi-config for %s node\n", np->name);
920 return -EINVAL;
921 }
922
923 dsi->pllref_clk = devm_clk_get(dev, "ref");
924 if (IS_ERR(dsi->pllref_clk)) {
925 ret = PTR_ERR(dsi->pllref_clk);
926 DRM_DEV_ERROR(dev,
927 "Unable to get pll reference clock: %d\n", ret);
928 return ret;
929 }
930
931 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
932 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
933 if (IS_ERR(dsi->phy_cfg_clk)) {
934 ret = PTR_ERR(dsi->phy_cfg_clk);
935 DRM_DEV_ERROR(dev,
936 "Unable to get phy_cfg_clk: %d\n", ret);
937 return ret;
938 }
939 }
940
941 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
942 dsi->grf_clk = devm_clk_get(dev, "grf");
943 if (IS_ERR(dsi->grf_clk)) {
944 ret = PTR_ERR(dsi->grf_clk);
945 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
946 return ret;
947 }
948 }
949
950 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
951 if (IS_ERR(dsi->grf_regmap)) {
952 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
953 return PTR_ERR(dsi->grf_regmap);
954 }
955
956 dsi->dev = dev;
957 dsi->pdata.base = dsi->base;
958 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
959 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
960 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
961 dsi->pdata.priv_data = dsi;
962 platform_set_drvdata(pdev, dsi);
963
964 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
965 if (IS_ERR(dsi->dmd)) {
966 ret = PTR_ERR(dsi->dmd);
967 if (ret != -EPROBE_DEFER)
968 DRM_DEV_ERROR(dev,
969 "Failed to probe dw_mipi_dsi: %d\n", ret);
970 goto err_clkdisable;
971 }
972
973 return 0;
974
975 err_clkdisable:
976 clk_disable_unprepare(dsi->pllref_clk);
977 return ret;
978 }
979
980 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
981 {
982 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
983
984 if (dsi->devcnt == 0)
985 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
986
987 dw_mipi_dsi_remove(dsi->dmd);
988
989 return 0;
990 }
991
992 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
993 {
994 .reg = 0xff960000,
995 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
996 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
997 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
998
999 .max_data_lanes = 4,
1000 },
1001 {
1002 .reg = 0xff964000,
1003 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1004 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1005 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1006
1007 .max_data_lanes = 4,
1008 },
1009 { }
1010 };
1011
1012 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1013 {
1014 .reg = 0xff960000,
1015 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1016 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1017 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1018 RK3399_DSI0_LCDC_SEL),
1019
1020 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1021 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1022 RK3399_DSI0_TURNDISABLE |
1023 RK3399_DSI0_FORCETXSTOPMODE |
1024 RK3399_DSI0_FORCERXMODE),
1025
1026 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1027 .max_data_lanes = 4,
1028 },
1029 {
1030 .reg = 0xff968000,
1031 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1032 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1033 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1034 RK3399_DSI1_LCDC_SEL),
1035
1036 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1037 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1038 RK3399_DSI1_FORCETXSTOPMODE |
1039 RK3399_DSI1_FORCERXMODE |
1040 RK3399_DSI1_ENABLE),
1041
1042 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1043 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1044 RK3399_TXRX_ENABLECLK,
1045 RK3399_TXRX_MASTERSLAVEZ |
1046 RK3399_TXRX_ENABLECLK |
1047 RK3399_TXRX_BASEDIR),
1048
1049 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1050 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1051
1052 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1053 .max_data_lanes = 4,
1054 },
1055 { }
1056 };
1057
1058 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1059 {
1060 .compatible = "rockchip,rk3288-mipi-dsi",
1061 .data = &rk3288_chip_data,
1062 }, {
1063 .compatible = "rockchip,rk3399-mipi-dsi",
1064 .data = &rk3399_chip_data,
1065 },
1066 { }
1067 };
1068 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1069
1070 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1071 .probe = dw_mipi_dsi_rockchip_probe,
1072 .remove = dw_mipi_dsi_rockchip_remove,
1073 .driver = {
1074 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1075 .name = "dw-mipi-dsi-rockchip",
1076 },
1077 };