drivers/misc/eeprom/at25.c

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This source file includes following definitions.
at25_ee_read
at25_ee_write
at25_fw_to_chip
at25_probe
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
   4  *
   5  * Copyright (C) 2006 David Brownell
   6  */
   7 
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/slab.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/sched.h>
  14 
  15 #include <linux/nvmem-provider.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/eeprom.h>
  18 #include <linux/property.h>
  19 
  20 /*
  21  * NOTE: this is an *EEPROM* driver.  The vagaries of product naming
  22  * mean that some AT25 products are EEPROMs, and others are FLASH.
  23  * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
  24  * not this one!
  25  */
  26 
  27 struct at25_data {
  28         struct spi_device       *spi;
  29         struct mutex            lock;
  30         struct spi_eeprom       chip;
  31         unsigned                addrlen;
  32         struct nvmem_config     nvmem_config;
  33         struct nvmem_device     *nvmem;
  34 };
  35 
  36 #define AT25_WREN       0x06            /* latch the write enable */
  37 #define AT25_WRDI       0x04            /* reset the write enable */
  38 #define AT25_RDSR       0x05            /* read status register */
  39 #define AT25_WRSR       0x01            /* write status register */
  40 #define AT25_READ       0x03            /* read byte(s) */
  41 #define AT25_WRITE      0x02            /* write byte(s)/sector */
  42 
  43 #define AT25_SR_nRDY    0x01            /* nRDY = write-in-progress */
  44 #define AT25_SR_WEN     0x02            /* write enable (latched) */
  45 #define AT25_SR_BP0     0x04            /* BP for software writeprotect */
  46 #define AT25_SR_BP1     0x08
  47 #define AT25_SR_WPEN    0x80            /* writeprotect enable */
  48 
  49 #define AT25_INSTR_BIT3 0x08            /* Additional address bit in instr */
  50 
  51 #define EE_MAXADDRLEN   3               /* 24 bit addresses, up to 2 MBytes */
  52 
  53 /* Specs often allow 5 msec for a page write, sometimes 20 msec;
  54  * it's important to recover from write timeouts.
  55  */
  56 #define EE_TIMEOUT      25
  57 
  58 /*-------------------------------------------------------------------------*/
  59 
  60 #define io_limit        PAGE_SIZE       /* bytes */
  61 
  62 static int at25_ee_read(void *priv, unsigned int offset,
  63                         void *val, size_t count)
  64 {
  65         struct at25_data *at25 = priv;
  66         char *buf = val;
  67         u8                      command[EE_MAXADDRLEN + 1];
  68         u8                      *cp;
  69         ssize_t                 status;
  70         struct spi_transfer     t[2];
  71         struct spi_message      m;
  72         u8                      instr;
  73 
  74         if (unlikely(offset >= at25->chip.byte_len))
  75                 return -EINVAL;
  76         if ((offset + count) > at25->chip.byte_len)
  77                 count = at25->chip.byte_len - offset;
  78         if (unlikely(!count))
  79                 return -EINVAL;
  80 
  81         cp = command;
  82 
  83         instr = AT25_READ;
  84         if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
  85                 if (offset >= (1U << (at25->addrlen * 8)))
  86                         instr |= AT25_INSTR_BIT3;
  87         *cp++ = instr;
  88 
  89         /* 8/16/24-bit address is written MSB first */
  90         switch (at25->addrlen) {
  91         default:        /* case 3 */
  92                 *cp++ = offset >> 16;
  93                 /* fall through */
  94         case 2:
  95                 *cp++ = offset >> 8;
  96                 /* fall through */
  97         case 1:
  98         case 0: /* can't happen: for better codegen */
  99                 *cp++ = offset >> 0;
 100         }
 101 
 102         spi_message_init(&m);
 103         memset(t, 0, sizeof(t));
 104 
 105         t[0].tx_buf = command;
 106         t[0].len = at25->addrlen + 1;
 107         spi_message_add_tail(&t[0], &m);
 108 
 109         t[1].rx_buf = buf;
 110         t[1].len = count;
 111         spi_message_add_tail(&t[1], &m);
 112 
 113         mutex_lock(&at25->lock);
 114 
 115         /* Read it all at once.
 116          *
 117          * REVISIT that's potentially a problem with large chips, if
 118          * other devices on the bus need to be accessed regularly or
 119          * this chip is clocked very slowly
 120          */
 121         status = spi_sync(at25->spi, &m);
 122         dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
 123                 count, offset, status);
 124 
 125         mutex_unlock(&at25->lock);
 126         return status;
 127 }
 128 
 129 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
 130 {
 131         struct at25_data *at25 = priv;
 132         const char *buf = val;
 133         int                     status = 0;
 134         unsigned                buf_size;
 135         u8                      *bounce;
 136 
 137         if (unlikely(off >= at25->chip.byte_len))
 138                 return -EFBIG;
 139         if ((off + count) > at25->chip.byte_len)
 140                 count = at25->chip.byte_len - off;
 141         if (unlikely(!count))
 142                 return -EINVAL;
 143 
 144         /* Temp buffer starts with command and address */
 145         buf_size = at25->chip.page_size;
 146         if (buf_size > io_limit)
 147                 buf_size = io_limit;
 148         bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
 149         if (!bounce)
 150                 return -ENOMEM;
 151 
 152         /* For write, rollover is within the page ... so we write at
 153          * most one page, then manually roll over to the next page.
 154          */
 155         mutex_lock(&at25->lock);
 156         do {
 157                 unsigned long   timeout, retries;
 158                 unsigned        segment;
 159                 unsigned        offset = (unsigned) off;
 160                 u8              *cp = bounce;
 161                 int             sr;
 162                 u8              instr;
 163 
 164                 *cp = AT25_WREN;
 165                 status = spi_write(at25->spi, cp, 1);
 166                 if (status < 0) {
 167                         dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
 168                         break;
 169                 }
 170 
 171                 instr = AT25_WRITE;
 172                 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
 173                         if (offset >= (1U << (at25->addrlen * 8)))
 174                                 instr |= AT25_INSTR_BIT3;
 175                 *cp++ = instr;
 176 
 177                 /* 8/16/24-bit address is written MSB first */
 178                 switch (at25->addrlen) {
 179                 default:        /* case 3 */
 180                         *cp++ = offset >> 16;
 181                         /* fall through */
 182                 case 2:
 183                         *cp++ = offset >> 8;
 184                         /* fall through */
 185                 case 1:
 186                 case 0: /* can't happen: for better codegen */
 187                         *cp++ = offset >> 0;
 188                 }
 189 
 190                 /* Write as much of a page as we can */
 191                 segment = buf_size - (offset % buf_size);
 192                 if (segment > count)
 193                         segment = count;
 194                 memcpy(cp, buf, segment);
 195                 status = spi_write(at25->spi, bounce,
 196                                 segment + at25->addrlen + 1);
 197                 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
 198                         segment, offset, status);
 199                 if (status < 0)
 200                         break;
 201 
 202                 /* REVISIT this should detect (or prevent) failed writes
 203                  * to readonly sections of the EEPROM...
 204                  */
 205 
 206                 /* Wait for non-busy status */
 207                 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
 208                 retries = 0;
 209                 do {
 210 
 211                         sr = spi_w8r8(at25->spi, AT25_RDSR);
 212                         if (sr < 0 || (sr & AT25_SR_nRDY)) {
 213                                 dev_dbg(&at25->spi->dev,
 214                                         "rdsr --> %d (%02x)\n", sr, sr);
 215                                 /* at HZ=100, this is sloooow */
 216                                 msleep(1);
 217                                 continue;
 218                         }
 219                         if (!(sr & AT25_SR_nRDY))
 220                                 break;
 221                 } while (retries++ < 3 || time_before_eq(jiffies, timeout));
 222 
 223                 if ((sr < 0) || (sr & AT25_SR_nRDY)) {
 224                         dev_err(&at25->spi->dev,
 225                                 "write %u bytes offset %u, timeout after %u msecs\n",
 226                                 segment, offset,
 227                                 jiffies_to_msecs(jiffies -
 228                                         (timeout - EE_TIMEOUT)));
 229                         status = -ETIMEDOUT;
 230                         break;
 231                 }
 232 
 233                 off += segment;
 234                 buf += segment;
 235                 count -= segment;
 236 
 237         } while (count > 0);
 238 
 239         mutex_unlock(&at25->lock);
 240 
 241         kfree(bounce);
 242         return status;
 243 }
 244 
 245 /*-------------------------------------------------------------------------*/
 246 
 247 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
 248 {
 249         u32 val;
 250 
 251         memset(chip, 0, sizeof(*chip));
 252         strncpy(chip->name, "at25", sizeof(chip->name));
 253 
 254         if (device_property_read_u32(dev, "size", &val) == 0 ||
 255             device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
 256                 chip->byte_len = val;
 257         } else {
 258                 dev_err(dev, "Error: missing \"size\" property\n");
 259                 return -ENODEV;
 260         }
 261 
 262         if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
 263             device_property_read_u32(dev, "at25,page-size", &val) == 0) {
 264                 chip->page_size = (u16)val;
 265         } else {
 266                 dev_err(dev, "Error: missing \"pagesize\" property\n");
 267                 return -ENODEV;
 268         }
 269 
 270         if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
 271                 chip->flags = (u16)val;
 272         } else {
 273                 if (device_property_read_u32(dev, "address-width", &val)) {
 274                         dev_err(dev,
 275                                 "Error: missing \"address-width\" property\n");
 276                         return -ENODEV;
 277                 }
 278                 switch (val) {
 279                 case 9:
 280                         chip->flags |= EE_INSTR_BIT3_IS_ADDR;
 281                         /* fall through */
 282                 case 8:
 283                         chip->flags |= EE_ADDR1;
 284                         break;
 285                 case 16:
 286                         chip->flags |= EE_ADDR2;
 287                         break;
 288                 case 24:
 289                         chip->flags |= EE_ADDR3;
 290                         break;
 291                 default:
 292                         dev_err(dev,
 293                                 "Error: bad \"address-width\" property: %u\n",
 294                                 val);
 295                         return -ENODEV;
 296                 }
 297                 if (device_property_present(dev, "read-only"))
 298                         chip->flags |= EE_READONLY;
 299         }
 300         return 0;
 301 }
 302 
 303 static int at25_probe(struct spi_device *spi)
 304 {
 305         struct at25_data        *at25 = NULL;
 306         struct spi_eeprom       chip;
 307         int                     err;
 308         int                     sr;
 309         int                     addrlen;
 310 
 311         /* Chip description */
 312         if (!spi->dev.platform_data) {
 313                 err = at25_fw_to_chip(&spi->dev, &chip);
 314                 if (err)
 315                         return err;
 316         } else
 317                 chip = *(struct spi_eeprom *)spi->dev.platform_data;
 318 
 319         /* For now we only support 8/16/24 bit addressing */
 320         if (chip.flags & EE_ADDR1)
 321                 addrlen = 1;
 322         else if (chip.flags & EE_ADDR2)
 323                 addrlen = 2;
 324         else if (chip.flags & EE_ADDR3)
 325                 addrlen = 3;
 326         else {
 327                 dev_dbg(&spi->dev, "unsupported address type\n");
 328                 return -EINVAL;
 329         }
 330 
 331         /* Ping the chip ... the status register is pretty portable,
 332          * unlike probing manufacturer IDs.  We do expect that system
 333          * firmware didn't write it in the past few milliseconds!
 334          */
 335         sr = spi_w8r8(spi, AT25_RDSR);
 336         if (sr < 0 || sr & AT25_SR_nRDY) {
 337                 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
 338                 return -ENXIO;
 339         }
 340 
 341         at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
 342         if (!at25)
 343                 return -ENOMEM;
 344 
 345         mutex_init(&at25->lock);
 346         at25->chip = chip;
 347         at25->spi = spi;
 348         spi_set_drvdata(spi, at25);
 349         at25->addrlen = addrlen;
 350 
 351         at25->nvmem_config.name = dev_name(&spi->dev);
 352         at25->nvmem_config.dev = &spi->dev;
 353         at25->nvmem_config.read_only = chip.flags & EE_READONLY;
 354         at25->nvmem_config.root_only = true;
 355         at25->nvmem_config.owner = THIS_MODULE;
 356         at25->nvmem_config.compat = true;
 357         at25->nvmem_config.base_dev = &spi->dev;
 358         at25->nvmem_config.reg_read = at25_ee_read;
 359         at25->nvmem_config.reg_write = at25_ee_write;
 360         at25->nvmem_config.priv = at25;
 361         at25->nvmem_config.stride = 4;
 362         at25->nvmem_config.word_size = 1;
 363         at25->nvmem_config.size = chip.byte_len;
 364 
 365         at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
 366         if (IS_ERR(at25->nvmem))
 367                 return PTR_ERR(at25->nvmem);
 368 
 369         dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
 370                 (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
 371                 (chip.byte_len < 1024) ? "Byte" : "KByte",
 372                 at25->chip.name,
 373                 (chip.flags & EE_READONLY) ? " (readonly)" : "",
 374                 at25->chip.page_size);
 375         return 0;
 376 }
 377 
 378 /*-------------------------------------------------------------------------*/
 379 
 380 static const struct of_device_id at25_of_match[] = {
 381         { .compatible = "atmel,at25", },
 382         { }
 383 };
 384 MODULE_DEVICE_TABLE(of, at25_of_match);
 385 
 386 static struct spi_driver at25_driver = {
 387         .driver = {
 388                 .name           = "at25",
 389                 .of_match_table = at25_of_match,
 390         },
 391         .probe          = at25_probe,
 392 };
 393 
 394 module_spi_driver(at25_driver);
 395 
 396 MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
 397 MODULE_AUTHOR("David Brownell");
 398 MODULE_LICENSE("GPL");
 399 MODULE_ALIAS("spi:at25");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/misc/eeprom/at25.c

DEFINITIONS
