1
2 #ifndef __MCB_INTERNAL
3 #define __MCB_INTERNAL
4
5 #include <linux/types.h>
6
7 #define PCI_VENDOR_ID_MEN 0x1a88
8 #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45
9 #define CHAMELEONV2_MAGIC 0xabce
10 #define CHAM_HEADER_SIZE 0x200
11
12 enum chameleon_descriptor_type {
13 CHAMELEON_DTYPE_GENERAL = 0x0,
14 CHAMELEON_DTYPE_BRIDGE = 0x1,
15 CHAMELEON_DTYPE_CPU = 0x2,
16 CHAMELEON_DTYPE_BAR = 0x3,
17 CHAMELEON_DTYPE_END = 0xf,
18 };
19
20 enum chameleon_bus_type {
21 CHAMELEON_BUS_WISHBONE,
22 CHAMELEON_BUS_AVALON,
23 CHAMELEON_BUS_LPC,
24 CHAMELEON_BUS_ISA,
25 };
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37
38 struct chameleon_fpga_header {
39 u8 revision;
40 char model;
41 u8 minor;
42 u8 bus_type;
43 u16 magic;
44 u16 reserved;
45
46 char filename[CHAMELEON_FILENAME_LEN];
47 } __packed;
48 #define HEADER_MAGIC_OFFSET 0x4
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64
65 struct chameleon_gdd {
66 __le32 reg1;
67 __le32 reg2;
68 __le32 offset;
69 __le32 size;
70
71 } __packed;
72
73
74 #define GDD_IRQ(x) ((x) & 0x1f)
75 #define GDD_REV(x) (((x) >> 5) & 0x3f)
76 #define GDD_VAR(x) (((x) >> 11) & 0x3f)
77 #define GDD_DEV(x) (((x) >> 18) & 0x3ff)
78 #define GDD_DTY(x) (((x) >> 28) & 0xf)
79
80
81 #define GDD_BAR(x) ((x) & 0x7)
82 #define GDD_INS(x) (((x) >> 3) & 0x3f)
83 #define GDD_GRP(x) (((x) >> 9) & 0x3f)
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99
100 struct chameleon_bdd {
101 unsigned int irq:6;
102 unsigned int rev:6;
103 unsigned int var:6;
104 unsigned int dev:10;
105 unsigned int dtype:4;
106 unsigned int bar:3;
107 unsigned int inst:6;
108 unsigned int dbar:3;
109 unsigned int group:6;
110 unsigned int reserved:14;
111 u32 chamoff;
112 u32 offset;
113 u32 size;
114 } __packed;
115
116 struct chameleon_bar {
117 u32 addr;
118 u32 size;
119 };
120
121 #define BAR_CNT(x) ((x) & 0x07)
122 #define CHAMELEON_BAR_MAX 6
123 #define BAR_DESC_SIZE(x) ((x) * sizeof(struct chameleon_bar) + sizeof(__le32))
124
125 int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase,
126 void __iomem *base);
127
128 #endif