This source file includes following definitions.
- axp20x_set_ramp_delay
- axp20x_regulator_enable_regmap
- axp20x_set_dcdc_freq
- axp20x_regulator_parse_dt
- axp20x_set_dcdc_workmode
- axp20x_is_polyphase_slave
- axp20x_regulator_probe
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16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/mfd/axp20x.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/of_regulator.h>
29
30 #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0)
31 #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0)
32
33 #define AXP20X_IO_ENABLED 0x03
34 #define AXP20X_IO_DISABLED 0x07
35
36 #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2)
37 #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1)
38
39 #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0)
40
41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2)
42
43 #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0)
44 #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0)
45 #define AXP20X_LDO24_V_OUT_MASK GENMASK(7, 4)
46 #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0)
47 #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4)
48
49 #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0)
50 #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1)
51 #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2)
52 #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3)
53 #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4)
54 #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6)
55
56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0)
57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
58 ((x) << 0)
59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1)
60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
61 ((x) << 1)
62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2)
63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2)
64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3)
65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3)
66
67 #define AXP20X_LDO4_V_OUT_1250mV_START 0x0
68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0
69 #define AXP20X_LDO4_V_OUT_1250mV_END \
70 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
71 #define AXP20X_LDO4_V_OUT_1300mV_START 0x1
72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7
73 #define AXP20X_LDO4_V_OUT_1300mV_END \
74 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
75 #define AXP20X_LDO4_V_OUT_2500mV_START 0x9
76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0
77 #define AXP20X_LDO4_V_OUT_2500mV_END \
78 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
79 #define AXP20X_LDO4_V_OUT_2700mV_START 0xa
80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1
81 #define AXP20X_LDO4_V_OUT_2700mV_END \
82 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
83 #define AXP20X_LDO4_V_OUT_3000mV_START 0xc
84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3
85 #define AXP20X_LDO4_V_OUT_3000mV_END \
86 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16
88
89 #define AXP22X_IO_ENABLED 0x03
90 #define AXP22X_IO_DISABLED 0x04
91
92 #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x)
93
94 #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
95
96 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0)
97 #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0)
98 #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0)
99 #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0)
100 #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0)
101 #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0)
102 #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0)
103 #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0)
104 #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0)
105 #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0)
106 #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0)
107 #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0)
108 #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0)
109 #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0)
110 #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0)
111 #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0)
112 #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0)
113 #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0)
114
115 #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0)
116 #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1)
117 #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2)
118 #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3)
119 #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4)
120 #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5)
121 #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6)
122 #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7)
123
124 #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6)
125 #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7)
126
127 #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0)
128 #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1)
129 #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2)
130 #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3)
131 #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4)
132 #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5)
133 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6)
134 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7)
135
136 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0)
137 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1)
138 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2)
139 #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3)
140 #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4)
141 #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5)
142
143 #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2)
144 #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3)
145
146 #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0)
147 #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0)
148 #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0)
149 #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0)
150 #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0)
151 #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0)
152
153 #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0)
154 #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0)
155
156 #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6)
157 #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5)
158
159 #define AXP803_DCDC234_500mV_START 0x00
160 #define AXP803_DCDC234_500mV_STEPS 70
161 #define AXP803_DCDC234_500mV_END \
162 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
163 #define AXP803_DCDC234_1220mV_START 0x47
164 #define AXP803_DCDC234_1220mV_STEPS 4
165 #define AXP803_DCDC234_1220mV_END \
166 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
167 #define AXP803_DCDC234_NUM_VOLTAGES 76
168
169 #define AXP803_DCDC5_800mV_START 0x00
170 #define AXP803_DCDC5_800mV_STEPS 32
171 #define AXP803_DCDC5_800mV_END \
172 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
173 #define AXP803_DCDC5_1140mV_START 0x21
174 #define AXP803_DCDC5_1140mV_STEPS 35
175 #define AXP803_DCDC5_1140mV_END \
176 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
177 #define AXP803_DCDC5_NUM_VOLTAGES 69
178
179 #define AXP803_DCDC6_600mV_START 0x00
180 #define AXP803_DCDC6_600mV_STEPS 50
181 #define AXP803_DCDC6_600mV_END \
182 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
183 #define AXP803_DCDC6_1120mV_START 0x33
184 #define AXP803_DCDC6_1120mV_STEPS 20
185 #define AXP803_DCDC6_1120mV_END \
186 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
187 #define AXP803_DCDC6_NUM_VOLTAGES 72
188
189 #define AXP803_DLDO2_700mV_START 0x00
190 #define AXP803_DLDO2_700mV_STEPS 26
191 #define AXP803_DLDO2_700mV_END \
192 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
193 #define AXP803_DLDO2_3400mV_START 0x1b
194 #define AXP803_DLDO2_3400mV_STEPS 4
195 #define AXP803_DLDO2_3400mV_END \
196 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
197 #define AXP803_DLDO2_NUM_VOLTAGES 32
198
199 #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0)
200 #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0)
201 #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0)
202 #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0)
203 #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0)
204 #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0)
205 #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0)
206 #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0)
207 #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0)
208 #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0)
209 #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0)
210 #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0)
211 #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0)
212 #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0)
213 #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0)
214
215 #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0)
216 #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1)
217 #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2)
218 #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3)
219 #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4)
220 #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5)
221 #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6)
222 #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7)
223 #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0)
224 #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1)
225 #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2)
226 #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3)
227 #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4)
228 #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5)
229 #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6)
230 #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7)
231
232 #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40
233 #define AXP806_DCDCABC_POLYPHASE_TRI 0x80
234 #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6)
235
236 #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5)
237
238 #define AXP806_DCDCA_600mV_START 0x00
239 #define AXP806_DCDCA_600mV_STEPS 50
240 #define AXP806_DCDCA_600mV_END \
241 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
242 #define AXP806_DCDCA_1120mV_START 0x33
243 #define AXP806_DCDCA_1120mV_STEPS 20
244 #define AXP806_DCDCA_1120mV_END \
245 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
246 #define AXP806_DCDCA_NUM_VOLTAGES 72
247
248 #define AXP806_DCDCD_600mV_START 0x00
249 #define AXP806_DCDCD_600mV_STEPS 45
250 #define AXP806_DCDCD_600mV_END \
251 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
252 #define AXP806_DCDCD_1600mV_START 0x2e
253 #define AXP806_DCDCD_1600mV_STEPS 17
254 #define AXP806_DCDCD_1600mV_END \
255 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
256 #define AXP806_DCDCD_NUM_VOLTAGES 64
257
258 #define AXP809_DCDC4_600mV_START 0x00
259 #define AXP809_DCDC4_600mV_STEPS 47
260 #define AXP809_DCDC4_600mV_END \
261 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
262 #define AXP809_DCDC4_1800mV_START 0x30
263 #define AXP809_DCDC4_1800mV_STEPS 8
264 #define AXP809_DCDC4_1800mV_END \
265 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
266 #define AXP809_DCDC4_NUM_VOLTAGES 57
267
268 #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0)
269
270 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6)
271
272 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
273 _vmask, _ereg, _emask, _enable_val, _disable_val) \
274 [_family##_##_id] = { \
275 .name = (_match), \
276 .supply_name = (_supply), \
277 .of_match = of_match_ptr(_match), \
278 .regulators_node = of_match_ptr("regulators"), \
279 .type = REGULATOR_VOLTAGE, \
280 .id = _family##_##_id, \
281 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
282 .owner = THIS_MODULE, \
283 .min_uV = (_min) * 1000, \
284 .uV_step = (_step) * 1000, \
285 .vsel_reg = (_vreg), \
286 .vsel_mask = (_vmask), \
287 .enable_reg = (_ereg), \
288 .enable_mask = (_emask), \
289 .enable_val = (_enable_val), \
290 .disable_val = (_disable_val), \
291 .ops = &axp20x_ops, \
292 }
293
294 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
295 _vmask, _ereg, _emask) \
296 [_family##_##_id] = { \
297 .name = (_match), \
298 .supply_name = (_supply), \
299 .of_match = of_match_ptr(_match), \
300 .regulators_node = of_match_ptr("regulators"), \
301 .type = REGULATOR_VOLTAGE, \
302 .id = _family##_##_id, \
303 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
304 .owner = THIS_MODULE, \
305 .min_uV = (_min) * 1000, \
306 .uV_step = (_step) * 1000, \
307 .vsel_reg = (_vreg), \
308 .vsel_mask = (_vmask), \
309 .enable_reg = (_ereg), \
310 .enable_mask = (_emask), \
311 .ops = &axp20x_ops, \
312 }
313
314 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
315 [_family##_##_id] = { \
316 .name = (_match), \
317 .supply_name = (_supply), \
318 .of_match = of_match_ptr(_match), \
319 .regulators_node = of_match_ptr("regulators"), \
320 .type = REGULATOR_VOLTAGE, \
321 .id = _family##_##_id, \
322 .owner = THIS_MODULE, \
323 .enable_reg = (_ereg), \
324 .enable_mask = (_emask), \
325 .ops = &axp20x_ops_sw, \
326 }
327
328 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
329 [_family##_##_id] = { \
330 .name = (_match), \
331 .supply_name = (_supply), \
332 .of_match = of_match_ptr(_match), \
333 .regulators_node = of_match_ptr("regulators"), \
334 .type = REGULATOR_VOLTAGE, \
335 .id = _family##_##_id, \
336 .n_voltages = 1, \
337 .owner = THIS_MODULE, \
338 .min_uV = (_volt) * 1000, \
339 .ops = &axp20x_ops_fixed \
340 }
341
342 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
343 _vreg, _vmask, _ereg, _emask) \
344 [_family##_##_id] = { \
345 .name = (_match), \
346 .supply_name = (_supply), \
347 .of_match = of_match_ptr(_match), \
348 .regulators_node = of_match_ptr("regulators"), \
349 .type = REGULATOR_VOLTAGE, \
350 .id = _family##_##_id, \
351 .n_voltages = (_n_voltages), \
352 .owner = THIS_MODULE, \
353 .vsel_reg = (_vreg), \
354 .vsel_mask = (_vmask), \
355 .enable_reg = (_ereg), \
356 .enable_mask = (_emask), \
357 .linear_ranges = (_ranges), \
358 .n_linear_ranges = ARRAY_SIZE(_ranges), \
359 .ops = &axp20x_ops_range, \
360 }
361
362 static const int axp209_dcdc2_ldo3_slew_rates[] = {
363 1600,
364 800,
365 };
366
367 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
368 {
369 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
370 int id = rdev_get_id(rdev);
371 u8 reg, mask, enable, cfg = 0xff;
372 const int *slew_rates;
373 int rate_count = 0;
374
375 switch (axp20x->variant) {
376 case AXP209_ID:
377 if (id == AXP20X_DCDC2) {
378 slew_rates = axp209_dcdc2_ldo3_slew_rates;
379 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
380 reg = AXP20X_DCDC2_LDO3_V_RAMP;
381 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
382 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
383 enable = (ramp > 0) ?
384 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN :
385 !AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN;
386 break;
387 }
388
389 if (id == AXP20X_LDO3) {
390 slew_rates = axp209_dcdc2_ldo3_slew_rates;
391 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
392 reg = AXP20X_DCDC2_LDO3_V_RAMP;
393 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
394 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
395 enable = (ramp > 0) ?
396 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN :
397 !AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN;
398 break;
399 }
400
401 if (rate_count > 0)
402 break;
403
404
405 default:
406
407 return -ENOTSUPP;
408 }
409
410 if (ramp == 0) {
411 cfg = enable;
412 } else {
413 int i;
414
415 for (i = 0; i < rate_count; i++) {
416 if (ramp > slew_rates[i])
417 break;
418
419 if (id == AXP20X_DCDC2)
420 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
421 else
422 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
423 }
424
425 if (cfg == 0xff) {
426 dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
427 return -EINVAL;
428 }
429
430 cfg |= enable;
431 }
432
433 return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
434 }
435
436 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
437 {
438 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
439 int id = rdev_get_id(rdev);
440
441 switch (axp20x->variant) {
442 case AXP209_ID:
443 if ((id == AXP20X_LDO3) &&
444 rdev->constraints && rdev->constraints->soft_start) {
445 int v_out;
446 int ret;
447
448
449
450
451
452
453
454
455 if (regulator_is_enabled_regmap(rdev))
456 break;
457
458 v_out = regulator_get_voltage_sel_regmap(rdev);
459 if (v_out < 0)
460 return v_out;
461
462 if (v_out == 0)
463 break;
464
465 ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
466
467
468
469
470
471 usleep_range(1000, 5000);
472 ret |= regulator_enable_regmap(rdev);
473 ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
474
475 return ret;
476 }
477 break;
478 default:
479
480 break;
481 }
482
483 return regulator_enable_regmap(rdev);
484 };
485
486 static const struct regulator_ops axp20x_ops_fixed = {
487 .list_voltage = regulator_list_voltage_linear,
488 };
489
490 static const struct regulator_ops axp20x_ops_range = {
491 .set_voltage_sel = regulator_set_voltage_sel_regmap,
492 .get_voltage_sel = regulator_get_voltage_sel_regmap,
493 .list_voltage = regulator_list_voltage_linear_range,
494 .enable = regulator_enable_regmap,
495 .disable = regulator_disable_regmap,
496 .is_enabled = regulator_is_enabled_regmap,
497 };
498
499 static const struct regulator_ops axp20x_ops = {
500 .set_voltage_sel = regulator_set_voltage_sel_regmap,
501 .get_voltage_sel = regulator_get_voltage_sel_regmap,
502 .list_voltage = regulator_list_voltage_linear,
503 .enable = axp20x_regulator_enable_regmap,
504 .disable = regulator_disable_regmap,
505 .is_enabled = regulator_is_enabled_regmap,
506 .set_ramp_delay = axp20x_set_ramp_delay,
507 };
508
509 static const struct regulator_ops axp20x_ops_sw = {
510 .enable = regulator_enable_regmap,
511 .disable = regulator_disable_regmap,
512 .is_enabled = regulator_is_enabled_regmap,
513 };
514
515 static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
516 REGULATOR_LINEAR_RANGE(1250000,
517 AXP20X_LDO4_V_OUT_1250mV_START,
518 AXP20X_LDO4_V_OUT_1250mV_END,
519 0),
520 REGULATOR_LINEAR_RANGE(1300000,
521 AXP20X_LDO4_V_OUT_1300mV_START,
522 AXP20X_LDO4_V_OUT_1300mV_END,
523 100000),
524 REGULATOR_LINEAR_RANGE(2500000,
525 AXP20X_LDO4_V_OUT_2500mV_START,
526 AXP20X_LDO4_V_OUT_2500mV_END,
527 0),
528 REGULATOR_LINEAR_RANGE(2700000,
529 AXP20X_LDO4_V_OUT_2700mV_START,
530 AXP20X_LDO4_V_OUT_2700mV_END,
531 100000),
532 REGULATOR_LINEAR_RANGE(3000000,
533 AXP20X_LDO4_V_OUT_3000mV_START,
534 AXP20X_LDO4_V_OUT_3000mV_END,
535 100000),
536 };
537
538 static const struct regulator_desc axp20x_regulators[] = {
539 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
540 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
541 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
542 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
543 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
544 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
545 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
546 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
547 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK,
548 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
549 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
550 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
551 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
552 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
553 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
554 AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK,
555 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
556 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
557 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
558 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
559 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
560 };
561
562 static const struct regulator_desc axp22x_regulators[] = {
563 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
564 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
565 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
566 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
567 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
568 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
569 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
570 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
571 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
572 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
573 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
574 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
575 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
576 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
577 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
578
579 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
580 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
581
582 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
583 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
584 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
585 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
586 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
587 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
588 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
589 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
590 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
591 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
592 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
593 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
594 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
595 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
596 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
597 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
598 AXP22X_DLDO2_V_OUT, AXP22X_PWR_OUT_DLDO2_MASK,
599 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
600 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
601 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
602 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
603 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
604 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
605 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
606 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
607 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
608 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
609 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
610 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
611 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
612 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
613 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
614 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
615
616
617 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
618 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
619 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
620 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
621
622
623 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
624 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
625 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
626 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
627 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
628 };
629
630 static const struct regulator_desc axp22x_drivevbus_regulator = {
631 .name = "drivevbus",
632 .supply_name = "drivevbus",
633 .of_match = of_match_ptr("drivevbus"),
634 .regulators_node = of_match_ptr("regulators"),
635 .type = REGULATOR_VOLTAGE,
636 .owner = THIS_MODULE,
637 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
638 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK,
639 .ops = &axp20x_ops_sw,
640 };
641
642
643 static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
644 REGULATOR_LINEAR_RANGE(500000,
645 AXP803_DCDC234_500mV_START,
646 AXP803_DCDC234_500mV_END,
647 10000),
648 REGULATOR_LINEAR_RANGE(1220000,
649 AXP803_DCDC234_1220mV_START,
650 AXP803_DCDC234_1220mV_END,
651 20000),
652 };
653
654 static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
655 REGULATOR_LINEAR_RANGE(800000,
656 AXP803_DCDC5_800mV_START,
657 AXP803_DCDC5_800mV_END,
658 10000),
659 REGULATOR_LINEAR_RANGE(1140000,
660 AXP803_DCDC5_1140mV_START,
661 AXP803_DCDC5_1140mV_END,
662 20000),
663 };
664
665 static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
666 REGULATOR_LINEAR_RANGE(600000,
667 AXP803_DCDC6_600mV_START,
668 AXP803_DCDC6_600mV_END,
669 10000),
670 REGULATOR_LINEAR_RANGE(1120000,
671 AXP803_DCDC6_1120mV_START,
672 AXP803_DCDC6_1120mV_END,
673 20000),
674 };
675
676
677 static const struct regulator_linear_range axp803_dldo2_ranges[] = {
678 REGULATOR_LINEAR_RANGE(700000,
679 AXP803_DLDO2_700mV_START,
680 AXP803_DLDO2_700mV_END,
681 100000),
682 REGULATOR_LINEAR_RANGE(3400000,
683 AXP803_DLDO2_3400mV_START,
684 AXP803_DLDO2_3400mV_END,
685 200000),
686 };
687
688 static const struct regulator_desc axp803_regulators[] = {
689 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
690 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
691 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
692 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
693 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
694 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
695 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
696 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
697 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
698 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
699 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
700 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
701 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
702 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
703 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
704 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
705 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
706 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
707 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
708 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
709 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
710 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
711 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
712
713 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
714 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
715 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
716 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
717 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
718 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
719 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
720 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
721 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
722 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
723 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
724 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
725 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
726 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
727 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
728 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
729 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
730 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
731 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
732 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
733 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
734 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
735 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
736 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
737 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
738 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
739 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
740 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
741 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
742 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
743 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
744 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
745 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
746 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
747 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
748 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
749 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
750 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
751 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
752 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
753 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
754 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
755 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
756 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
757 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
758 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
759 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
760 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
761 };
762
763 static const struct regulator_linear_range axp806_dcdca_ranges[] = {
764 REGULATOR_LINEAR_RANGE(600000,
765 AXP806_DCDCA_600mV_START,
766 AXP806_DCDCA_600mV_END,
767 10000),
768 REGULATOR_LINEAR_RANGE(1120000,
769 AXP806_DCDCA_1120mV_START,
770 AXP806_DCDCA_1120mV_END,
771 20000),
772 };
773
774 static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
775 REGULATOR_LINEAR_RANGE(600000,
776 AXP806_DCDCD_600mV_START,
777 AXP806_DCDCD_600mV_END,
778 20000),
779 REGULATOR_LINEAR_RANGE(1600000,
780 AXP806_DCDCD_1600mV_START,
781 AXP806_DCDCD_1600mV_END,
782 100000),
783 };
784
785 static const struct regulator_desc axp806_regulators[] = {
786 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
787 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
788 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
789 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
790 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
791 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
792 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
793 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
794 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
795 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
796 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
797 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
798 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
799 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
800 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
801 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
802 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
803 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
804 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
805 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
806 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
807 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
808 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
809 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
810 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
811 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
812 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
813 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
814 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
815 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
816 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
817 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
818 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
819 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
820 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
821 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
822 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
823 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
824 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
825 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
826 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
827 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
828 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
829 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
830 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
831 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
832 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
833 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
834 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
835 AXP_DESC_SW(AXP806, SW, "sw", "swin",
836 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
837 };
838
839 static const struct regulator_linear_range axp809_dcdc4_ranges[] = {
840 REGULATOR_LINEAR_RANGE(600000,
841 AXP809_DCDC4_600mV_START,
842 AXP809_DCDC4_600mV_END,
843 20000),
844 REGULATOR_LINEAR_RANGE(1800000,
845 AXP809_DCDC4_1800mV_START,
846 AXP809_DCDC4_1800mV_END,
847 100000),
848 };
849
850 static const struct regulator_desc axp809_regulators[] = {
851 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
852 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
853 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
854 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
855 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
856 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
857 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
858 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
859 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
860 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
861 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
862 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
863 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
864 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
865 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
866 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
867
868 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
869 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
870
871 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
872 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
873 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
874 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
875 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
876 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
877 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
878 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
879 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
880 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
881 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
882 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
883 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
884 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
885 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
886 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
887 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
888 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
889 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
890 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
891 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
892 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
893 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
894 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
895 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
896 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
897 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
898 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
899
900
901
902
903 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
904 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
905 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
906 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
907
908
909
910
911 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
912 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
913 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
914 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
915 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
916 AXP_DESC_SW(AXP809, SW, "sw", "swin",
917 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
918 };
919
920 static const struct regulator_desc axp813_regulators[] = {
921 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
922 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
923 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
924 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
925 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
926 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
927 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
928 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
929 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
930 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
931 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
932 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
933 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
934 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
935 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
936 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
937 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
938 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
939 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
940 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
941 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
942 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
943 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
944 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
945 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
946 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
947 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
948 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
949 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
950 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
951 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
952 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
953 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
954 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
955 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
956 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
957 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
958 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
959 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
960 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
961 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
962 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
963 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
964 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
965 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
966 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
967 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
968 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
969 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
970 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
971 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
972 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
973 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
974 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
975 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
976 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
977 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
978 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
979
980 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
981 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
982 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
983 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
984 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
985 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
986
987
988
989
990
991
992 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
993 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
994 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
995 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
996 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
997 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
998 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
999 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1000 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1001 AXP_DESC_SW(AXP813, SW, "sw", "swin",
1002 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1003 };
1004
1005 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1006 {
1007 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1008 unsigned int reg = AXP20X_DCDC_FREQ;
1009 u32 min, max, def, step;
1010
1011 switch (axp20x->variant) {
1012 case AXP202_ID:
1013 case AXP209_ID:
1014 min = 750;
1015 max = 1875;
1016 def = 1500;
1017 step = 75;
1018 break;
1019 case AXP803_ID:
1020 case AXP813_ID:
1021
1022
1023
1024
1025
1026 reg = AXP803_DCDC_FREQ_CTRL;
1027
1028 case AXP806_ID:
1029
1030
1031
1032
1033 if (axp20x->variant == AXP806_ID)
1034 reg = AXP806_DCDC_FREQ_CTRL;
1035
1036 case AXP221_ID:
1037 case AXP223_ID:
1038 case AXP809_ID:
1039 min = 1800;
1040 max = 4050;
1041 def = 3000;
1042 step = 150;
1043 break;
1044 default:
1045 dev_err(&pdev->dev,
1046 "Setting DCDC frequency for unsupported AXP variant\n");
1047 return -EINVAL;
1048 }
1049
1050 if (dcdcfreq == 0)
1051 dcdcfreq = def;
1052
1053 if (dcdcfreq < min) {
1054 dcdcfreq = min;
1055 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1056 min);
1057 }
1058
1059 if (dcdcfreq > max) {
1060 dcdcfreq = max;
1061 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1062 max);
1063 }
1064
1065 dcdcfreq = (dcdcfreq - min) / step;
1066
1067 return regmap_update_bits(axp20x->regmap, reg,
1068 AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1069 }
1070
1071 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1072 {
1073 struct device_node *np, *regulators;
1074 int ret;
1075 u32 dcdcfreq = 0;
1076
1077 np = of_node_get(pdev->dev.parent->of_node);
1078 if (!np)
1079 return 0;
1080
1081 regulators = of_get_child_by_name(np, "regulators");
1082 if (!regulators) {
1083 dev_warn(&pdev->dev, "regulators node not found\n");
1084 } else {
1085 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1086 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1087 if (ret < 0) {
1088 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1089 return ret;
1090 }
1091
1092 of_node_put(regulators);
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1099 {
1100 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1101 unsigned int reg = AXP20X_DCDC_MODE;
1102 unsigned int mask;
1103
1104 switch (axp20x->variant) {
1105 case AXP202_ID:
1106 case AXP209_ID:
1107 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1108 return -EINVAL;
1109
1110 mask = AXP20X_WORKMODE_DCDC2_MASK;
1111 if (id == AXP20X_DCDC3)
1112 mask = AXP20X_WORKMODE_DCDC3_MASK;
1113
1114 workmode <<= ffs(mask) - 1;
1115 break;
1116
1117 case AXP806_ID:
1118
1119
1120
1121
1122 reg = AXP806_DCDC_MODE_CTRL2;
1123
1124 case AXP221_ID:
1125 case AXP223_ID:
1126 case AXP809_ID:
1127 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1128 return -EINVAL;
1129
1130 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1131 workmode <<= id - AXP22X_DCDC1;
1132 break;
1133
1134 case AXP803_ID:
1135 if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1136 return -EINVAL;
1137
1138 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1139 workmode <<= id - AXP803_DCDC1;
1140 break;
1141
1142 case AXP813_ID:
1143 if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1144 return -EINVAL;
1145
1146 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1147 workmode <<= id - AXP813_DCDC1;
1148 break;
1149
1150 default:
1151
1152 WARN_ON(1);
1153 return -EINVAL;
1154 }
1155
1156 return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1157 }
1158
1159
1160
1161
1162
1163 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1164 {
1165 u32 reg = 0;
1166
1167
1168
1169
1170
1171 switch (axp20x->variant) {
1172 case AXP803_ID:
1173 case AXP813_ID:
1174 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®);
1175
1176 switch (id) {
1177 case AXP803_DCDC3:
1178 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1179 case AXP803_DCDC6:
1180 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1181 }
1182 break;
1183
1184 case AXP806_ID:
1185 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®);
1186
1187 switch (id) {
1188 case AXP806_DCDCB:
1189 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1190 AXP806_DCDCAB_POLYPHASE_DUAL) ||
1191 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1192 AXP806_DCDCABC_POLYPHASE_TRI));
1193 case AXP806_DCDCC:
1194 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1195 AXP806_DCDCABC_POLYPHASE_TRI);
1196 case AXP806_DCDCE:
1197 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1198 }
1199 break;
1200
1201 default:
1202 return false;
1203 }
1204
1205 return false;
1206 }
1207
1208 static int axp20x_regulator_probe(struct platform_device *pdev)
1209 {
1210 struct regulator_dev *rdev;
1211 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1212 const struct regulator_desc *regulators;
1213 struct regulator_config config = {
1214 .dev = pdev->dev.parent,
1215 .regmap = axp20x->regmap,
1216 .driver_data = axp20x,
1217 };
1218 int ret, i, nregulators;
1219 u32 workmode;
1220 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1221 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1222 bool drivevbus = false;
1223
1224 switch (axp20x->variant) {
1225 case AXP202_ID:
1226 case AXP209_ID:
1227 regulators = axp20x_regulators;
1228 nregulators = AXP20X_REG_ID_MAX;
1229 break;
1230 case AXP221_ID:
1231 case AXP223_ID:
1232 regulators = axp22x_regulators;
1233 nregulators = AXP22X_REG_ID_MAX;
1234 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1235 "x-powers,drive-vbus-en");
1236 break;
1237 case AXP803_ID:
1238 regulators = axp803_regulators;
1239 nregulators = AXP803_REG_ID_MAX;
1240 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1241 "x-powers,drive-vbus-en");
1242 break;
1243 case AXP806_ID:
1244 regulators = axp806_regulators;
1245 nregulators = AXP806_REG_ID_MAX;
1246 break;
1247 case AXP809_ID:
1248 regulators = axp809_regulators;
1249 nregulators = AXP809_REG_ID_MAX;
1250 break;
1251 case AXP813_ID:
1252 regulators = axp813_regulators;
1253 nregulators = AXP813_REG_ID_MAX;
1254 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1255 "x-powers,drive-vbus-en");
1256 break;
1257 default:
1258 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1259 axp20x->variant);
1260 return -EINVAL;
1261 }
1262
1263
1264 axp20x_regulator_parse_dt(pdev);
1265
1266 for (i = 0; i < nregulators; i++) {
1267 const struct regulator_desc *desc = ®ulators[i];
1268 struct regulator_desc *new_desc;
1269
1270
1271
1272
1273
1274
1275 if (axp20x_is_polyphase_slave(axp20x, i))
1276 continue;
1277
1278
1279 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1280 continue;
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1292 (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1293 (regulators == axp809_regulators && i == AXP809_DC1SW)) {
1294 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1295 GFP_KERNEL);
1296 if (!new_desc)
1297 return -ENOMEM;
1298
1299 *new_desc = regulators[i];
1300 new_desc->supply_name = dcdc1_name;
1301 desc = new_desc;
1302 }
1303
1304 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1305 (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
1306 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1307 GFP_KERNEL);
1308 if (!new_desc)
1309 return -ENOMEM;
1310
1311 *new_desc = regulators[i];
1312 new_desc->supply_name = dcdc5_name;
1313 desc = new_desc;
1314 }
1315
1316 rdev = devm_regulator_register(&pdev->dev, desc, &config);
1317 if (IS_ERR(rdev)) {
1318 dev_err(&pdev->dev, "Failed to register %s\n",
1319 regulators[i].name);
1320
1321 return PTR_ERR(rdev);
1322 }
1323
1324 ret = of_property_read_u32(rdev->dev.of_node,
1325 "x-powers,dcdc-workmode",
1326 &workmode);
1327 if (!ret) {
1328 if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1329 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1330 rdev->desc->name);
1331 }
1332
1333
1334
1335
1336 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1337 (regulators == axp809_regulators && i == AXP809_DCDC1))
1338 of_property_read_string(rdev->dev.of_node,
1339 "regulator-name",
1340 &dcdc1_name);
1341
1342 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1343 (regulators == axp809_regulators && i == AXP809_DCDC5))
1344 of_property_read_string(rdev->dev.of_node,
1345 "regulator-name",
1346 &dcdc5_name);
1347 }
1348
1349 if (drivevbus) {
1350
1351 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1352 AXP22X_MISC_N_VBUSEN_FUNC, 0);
1353 rdev = devm_regulator_register(&pdev->dev,
1354 &axp22x_drivevbus_regulator,
1355 &config);
1356 if (IS_ERR(rdev)) {
1357 dev_err(&pdev->dev, "Failed to register drivevbus\n");
1358 return PTR_ERR(rdev);
1359 }
1360 }
1361
1362 return 0;
1363 }
1364
1365 static struct platform_driver axp20x_regulator_driver = {
1366 .probe = axp20x_regulator_probe,
1367 .driver = {
1368 .name = "axp20x-regulator",
1369 },
1370 };
1371
1372 module_platform_driver(axp20x_regulator_driver);
1373
1374 MODULE_LICENSE("GPL v2");
1375 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1376 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1377 MODULE_ALIAS("platform:axp20x-regulator");