This source file includes following definitions.
- rpm_reg_write_active
- rpm_reg_enable
- rpm_reg_is_enabled
- rpm_reg_disable
- rpm_reg_get_voltage
- rpm_reg_set_voltage
- rpm_reg_set_load
- rpm_reg_probe
- rpm_reg_init
- rpm_reg_exit
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7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/regulator/driver.h>
12 #include <linux/soc/qcom/smd-rpm.h>
13
14 struct qcom_rpm_reg {
15 struct device *dev;
16
17 struct qcom_smd_rpm *rpm;
18
19 u32 type;
20 u32 id;
21
22 struct regulator_desc desc;
23
24 int is_enabled;
25 int uV;
26 u32 load;
27
28 unsigned int enabled_updated:1;
29 unsigned int uv_updated:1;
30 unsigned int load_updated:1;
31 };
32
33 struct rpm_regulator_req {
34 __le32 key;
35 __le32 nbytes;
36 __le32 value;
37 };
38
39 #define RPM_KEY_SWEN 0x6e657773
40 #define RPM_KEY_UV 0x00007675
41 #define RPM_KEY_MA 0x0000616d
42
43 static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
44 {
45 struct rpm_regulator_req req[3];
46 int reqlen = 0;
47 int ret;
48
49 if (vreg->enabled_updated) {
50 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
51 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
52 req[reqlen].value = cpu_to_le32(vreg->is_enabled);
53 reqlen++;
54 }
55
56 if (vreg->uv_updated && vreg->is_enabled) {
57 req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
58 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
59 req[reqlen].value = cpu_to_le32(vreg->uV);
60 reqlen++;
61 }
62
63 if (vreg->load_updated && vreg->is_enabled) {
64 req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
65 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
66 req[reqlen].value = cpu_to_le32(vreg->load / 1000);
67 reqlen++;
68 }
69
70 if (!reqlen)
71 return 0;
72
73 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
74 vreg->type, vreg->id,
75 req, sizeof(req[0]) * reqlen);
76 if (!ret) {
77 vreg->enabled_updated = 0;
78 vreg->uv_updated = 0;
79 vreg->load_updated = 0;
80 }
81
82 return ret;
83 }
84
85 static int rpm_reg_enable(struct regulator_dev *rdev)
86 {
87 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
88 int ret;
89
90 vreg->is_enabled = 1;
91 vreg->enabled_updated = 1;
92
93 ret = rpm_reg_write_active(vreg);
94 if (ret)
95 vreg->is_enabled = 0;
96
97 return ret;
98 }
99
100 static int rpm_reg_is_enabled(struct regulator_dev *rdev)
101 {
102 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
103
104 return vreg->is_enabled;
105 }
106
107 static int rpm_reg_disable(struct regulator_dev *rdev)
108 {
109 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
110 int ret;
111
112 vreg->is_enabled = 0;
113 vreg->enabled_updated = 1;
114
115 ret = rpm_reg_write_active(vreg);
116 if (ret)
117 vreg->is_enabled = 1;
118
119 return ret;
120 }
121
122 static int rpm_reg_get_voltage(struct regulator_dev *rdev)
123 {
124 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
125
126 return vreg->uV;
127 }
128
129 static int rpm_reg_set_voltage(struct regulator_dev *rdev,
130 int min_uV,
131 int max_uV,
132 unsigned *selector)
133 {
134 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
135 int ret;
136 int old_uV = vreg->uV;
137
138 vreg->uV = min_uV;
139 vreg->uv_updated = 1;
140
141 ret = rpm_reg_write_active(vreg);
142 if (ret)
143 vreg->uV = old_uV;
144
145 return ret;
146 }
147
148 static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
149 {
150 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
151 u32 old_load = vreg->load;
152 int ret;
153
154 vreg->load = load_uA;
155 vreg->load_updated = 1;
156 ret = rpm_reg_write_active(vreg);
157 if (ret)
158 vreg->load = old_load;
159
160 return ret;
161 }
162
163 static const struct regulator_ops rpm_smps_ldo_ops = {
164 .enable = rpm_reg_enable,
165 .disable = rpm_reg_disable,
166 .is_enabled = rpm_reg_is_enabled,
167 .list_voltage = regulator_list_voltage_linear_range,
168
169 .get_voltage = rpm_reg_get_voltage,
170 .set_voltage = rpm_reg_set_voltage,
171
172 .set_load = rpm_reg_set_load,
173 };
174
175 static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
176 .enable = rpm_reg_enable,
177 .disable = rpm_reg_disable,
178 .is_enabled = rpm_reg_is_enabled,
179
180 .get_voltage = rpm_reg_get_voltage,
181 .set_voltage = rpm_reg_set_voltage,
182
183 .set_load = rpm_reg_set_load,
184 };
185
186 static const struct regulator_ops rpm_switch_ops = {
187 .enable = rpm_reg_enable,
188 .disable = rpm_reg_disable,
189 .is_enabled = rpm_reg_is_enabled,
190 };
191
192 static const struct regulator_ops rpm_bob_ops = {
193 .enable = rpm_reg_enable,
194 .disable = rpm_reg_disable,
195 .is_enabled = rpm_reg_is_enabled,
196
197 .get_voltage = rpm_reg_get_voltage,
198 .set_voltage = rpm_reg_set_voltage,
199 };
200
201 static const struct regulator_desc pma8084_hfsmps = {
202 .linear_ranges = (struct regulator_linear_range[]) {
203 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
204 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
205 },
206 .n_linear_ranges = 2,
207 .n_voltages = 159,
208 .ops = &rpm_smps_ldo_ops,
209 };
210
211 static const struct regulator_desc pma8084_ftsmps = {
212 .linear_ranges = (struct regulator_linear_range[]) {
213 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
214 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
215 },
216 .n_linear_ranges = 2,
217 .n_voltages = 262,
218 .ops = &rpm_smps_ldo_ops,
219 };
220
221 static const struct regulator_desc pma8084_pldo = {
222 .linear_ranges = (struct regulator_linear_range[]) {
223 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
224 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
225 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
226 },
227 .n_linear_ranges = 3,
228 .n_voltages = 164,
229 .ops = &rpm_smps_ldo_ops,
230 };
231
232 static const struct regulator_desc pma8084_nldo = {
233 .linear_ranges = (struct regulator_linear_range[]) {
234 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
235 },
236 .n_linear_ranges = 1,
237 .n_voltages = 64,
238 .ops = &rpm_smps_ldo_ops,
239 };
240
241 static const struct regulator_desc pma8084_switch = {
242 .ops = &rpm_switch_ops,
243 };
244
245 static const struct regulator_desc pm8x41_hfsmps = {
246 .linear_ranges = (struct regulator_linear_range[]) {
247 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
248 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
249 },
250 .n_linear_ranges = 2,
251 .n_voltages = 159,
252 .ops = &rpm_smps_ldo_ops,
253 };
254
255 static const struct regulator_desc pm8841_ftsmps = {
256 .linear_ranges = (struct regulator_linear_range[]) {
257 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
258 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
259 },
260 .n_linear_ranges = 2,
261 .n_voltages = 262,
262 .ops = &rpm_smps_ldo_ops,
263 };
264
265 static const struct regulator_desc pm8941_boost = {
266 .linear_ranges = (struct regulator_linear_range[]) {
267 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
268 },
269 .n_linear_ranges = 1,
270 .n_voltages = 31,
271 .ops = &rpm_smps_ldo_ops,
272 };
273
274 static const struct regulator_desc pm8941_pldo = {
275 .linear_ranges = (struct regulator_linear_range[]) {
276 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
277 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
278 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
279 },
280 .n_linear_ranges = 3,
281 .n_voltages = 164,
282 .ops = &rpm_smps_ldo_ops,
283 };
284
285 static const struct regulator_desc pm8941_nldo = {
286 .linear_ranges = (struct regulator_linear_range[]) {
287 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
288 },
289 .n_linear_ranges = 1,
290 .n_voltages = 64,
291 .ops = &rpm_smps_ldo_ops,
292 };
293
294 static const struct regulator_desc pm8941_lnldo = {
295 .fixed_uV = 1740000,
296 .n_voltages = 1,
297 .ops = &rpm_smps_ldo_ops_fixed,
298 };
299
300 static const struct regulator_desc pm8941_switch = {
301 .ops = &rpm_switch_ops,
302 };
303
304 static const struct regulator_desc pm8916_pldo = {
305 .linear_ranges = (struct regulator_linear_range[]) {
306 REGULATOR_LINEAR_RANGE(750000, 0, 208, 12500),
307 },
308 .n_linear_ranges = 1,
309 .n_voltages = 209,
310 .ops = &rpm_smps_ldo_ops,
311 };
312
313 static const struct regulator_desc pm8916_nldo = {
314 .linear_ranges = (struct regulator_linear_range[]) {
315 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
316 },
317 .n_linear_ranges = 1,
318 .n_voltages = 94,
319 .ops = &rpm_smps_ldo_ops,
320 };
321
322 static const struct regulator_desc pm8916_buck_lvo_smps = {
323 .linear_ranges = (struct regulator_linear_range[]) {
324 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
325 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
326 },
327 .n_linear_ranges = 2,
328 .n_voltages = 128,
329 .ops = &rpm_smps_ldo_ops,
330 };
331
332 static const struct regulator_desc pm8916_buck_hvo_smps = {
333 .linear_ranges = (struct regulator_linear_range[]) {
334 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
335 },
336 .n_linear_ranges = 1,
337 .n_voltages = 32,
338 .ops = &rpm_smps_ldo_ops,
339 };
340
341 static const struct regulator_desc pm8994_hfsmps = {
342 .linear_ranges = (struct regulator_linear_range[]) {
343 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
344 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
345 },
346 .n_linear_ranges = 2,
347 .n_voltages = 159,
348 .ops = &rpm_smps_ldo_ops,
349 };
350
351 static const struct regulator_desc pm8994_ftsmps = {
352 .linear_ranges = (struct regulator_linear_range[]) {
353 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
354 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
355 },
356 .n_linear_ranges = 2,
357 .n_voltages = 350,
358 .ops = &rpm_smps_ldo_ops,
359 };
360
361 static const struct regulator_desc pm8994_nldo = {
362 .linear_ranges = (struct regulator_linear_range[]) {
363 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
364 },
365 .n_linear_ranges = 1,
366 .n_voltages = 64,
367 .ops = &rpm_smps_ldo_ops,
368 };
369
370 static const struct regulator_desc pm8994_pldo = {
371 .linear_ranges = (struct regulator_linear_range[]) {
372 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
373 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
374 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
375 },
376 .n_linear_ranges = 3,
377 .n_voltages = 164,
378 .ops = &rpm_smps_ldo_ops,
379 };
380
381 static const struct regulator_desc pm8994_switch = {
382 .ops = &rpm_switch_ops,
383 };
384
385 static const struct regulator_desc pm8994_lnldo = {
386 .fixed_uV = 1740000,
387 .n_voltages = 1,
388 .ops = &rpm_smps_ldo_ops_fixed,
389 };
390
391 static const struct regulator_desc pm8998_ftsmps = {
392 .linear_ranges = (struct regulator_linear_range[]) {
393 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
394 },
395 .n_linear_ranges = 1,
396 .n_voltages = 259,
397 .ops = &rpm_smps_ldo_ops,
398 };
399
400 static const struct regulator_desc pm8998_hfsmps = {
401 .linear_ranges = (struct regulator_linear_range[]) {
402 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
403 },
404 .n_linear_ranges = 1,
405 .n_voltages = 216,
406 .ops = &rpm_smps_ldo_ops,
407 };
408
409 static const struct regulator_desc pm8998_nldo = {
410 .linear_ranges = (struct regulator_linear_range[]) {
411 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
412 },
413 .n_linear_ranges = 1,
414 .n_voltages = 128,
415 .ops = &rpm_smps_ldo_ops,
416 };
417
418 static const struct regulator_desc pm8998_pldo = {
419 .linear_ranges = (struct regulator_linear_range[]) {
420 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
421 },
422 .n_linear_ranges = 1,
423 .n_voltages = 256,
424 .ops = &rpm_smps_ldo_ops,
425 };
426
427 static const struct regulator_desc pm8998_pldo_lv = {
428 .linear_ranges = (struct regulator_linear_range[]) {
429 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
430 },
431 .n_linear_ranges = 1,
432 .n_voltages = 128,
433 .ops = &rpm_smps_ldo_ops,
434 };
435
436 static const struct regulator_desc pm8998_switch = {
437 .ops = &rpm_switch_ops,
438 };
439
440 static const struct regulator_desc pmi8998_bob = {
441 .linear_ranges = (struct regulator_linear_range[]) {
442 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
443 },
444 .n_linear_ranges = 1,
445 .n_voltages = 84,
446 .ops = &rpm_bob_ops,
447 };
448
449 static const struct regulator_desc pms405_hfsmps3 = {
450 .linear_ranges = (struct regulator_linear_range[]) {
451 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
452 },
453 .n_linear_ranges = 1,
454 .n_voltages = 216,
455 .ops = &rpm_smps_ldo_ops,
456 };
457
458 static const struct regulator_desc pms405_nldo300 = {
459 .linear_ranges = (struct regulator_linear_range[]) {
460 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
461 },
462 .n_linear_ranges = 1,
463 .n_voltages = 128,
464 .ops = &rpm_smps_ldo_ops,
465 };
466
467 static const struct regulator_desc pms405_nldo1200 = {
468 .linear_ranges = (struct regulator_linear_range[]) {
469 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
470 },
471 .n_linear_ranges = 1,
472 .n_voltages = 128,
473 .ops = &rpm_smps_ldo_ops,
474 };
475
476 static const struct regulator_desc pms405_pldo50 = {
477 .linear_ranges = (struct regulator_linear_range[]) {
478 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
479 },
480 .n_linear_ranges = 1,
481 .n_voltages = 129,
482 .ops = &rpm_smps_ldo_ops,
483 };
484
485 static const struct regulator_desc pms405_pldo150 = {
486 .linear_ranges = (struct regulator_linear_range[]) {
487 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
488 },
489 .n_linear_ranges = 1,
490 .n_voltages = 129,
491 .ops = &rpm_smps_ldo_ops,
492 };
493
494 static const struct regulator_desc pms405_pldo600 = {
495 .linear_ranges = (struct regulator_linear_range[]) {
496 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
497 },
498 .n_linear_ranges = 1,
499 .n_voltages = 99,
500 .ops = &rpm_smps_ldo_ops,
501 };
502
503 struct rpm_regulator_data {
504 const char *name;
505 u32 type;
506 u32 id;
507 const struct regulator_desc *desc;
508 const char *supply;
509 };
510
511 static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
512 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
513 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
514 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
515 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
516 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
517 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
518 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
519 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
520 {}
521 };
522
523 static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
524 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
525 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
526 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
527 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
528 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
529 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
530 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
531 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
532 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
533 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
534 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
535 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
536 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
537 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
538 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
539 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
540 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
541 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
542 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
543 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
544 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
545 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
546 {}
547 };
548
549 static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
550 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
551 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
552 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
553 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
554
555 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
556 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
557 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
558 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
559 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
560 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
561 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
562 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
563 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
564 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
565 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
566 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
567 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
568 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
569 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
570 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
571 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
572 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
573 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
574 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
575 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
576 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
577 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
578 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
579
580 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
581 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
582 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
583
584 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
585 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
586
587 {}
588 };
589
590 static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
591 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
592 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
593 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
594 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
595 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
596 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
597 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
598 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
599 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
600 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
601 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
602 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
603
604 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
605 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
606 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
607 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
608 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
609 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
610 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
611 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
612 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
613 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
614 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
615 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
616 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
617 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
618 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
619 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
620 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
621 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
622 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
623 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
624 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
625 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
626 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
627 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
628 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
629 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
630 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
631
632 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
633 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
634 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
635 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
636 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
637
638 {}
639 };
640
641 static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
642 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
643 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
644 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
645 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
646 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
647 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
648 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
649 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
650 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
651 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
652 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
653 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
654 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
655 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
656 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
657 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
658 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
659 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
660 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
661 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
662 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
663 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
664 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
665 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
666 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
667 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
668 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
669 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
670 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
671 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
672 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
673 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
674 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
675 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
676 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
677 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
678 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
679 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
680 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
681 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
682 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
683 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
684 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
685 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
686 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
687 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
688
689 {}
690 };
691
692 static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
693 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
694 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
695 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
696 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
697 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
698 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
699 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
700 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
701 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
702 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
703 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
704 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
705 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
706 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
707 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
708 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
709 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
710 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
711 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
712 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
713 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
714 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
715 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
716 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
717 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
718 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
719 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
720 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
721 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
722 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
723 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
724 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
725 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
726 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
727 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
728 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
729 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
730 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
731 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
732 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
733 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
734 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
735 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
736 {}
737 };
738
739 static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
740 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
741 {}
742 };
743
744 static const struct rpm_regulator_data rpm_pms405_regulators[] = {
745 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
746 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
747 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
748 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
749 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
750 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
751 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
752 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
753 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
754 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
755 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
756 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
757 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
758 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
759 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
760 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
761 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
762 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
763 {}
764 };
765
766 static const struct of_device_id rpm_of_match[] = {
767 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
768 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
769 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
770 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
771 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
772 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
773 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
774 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
775 {}
776 };
777 MODULE_DEVICE_TABLE(of, rpm_of_match);
778
779 static int rpm_reg_probe(struct platform_device *pdev)
780 {
781 const struct rpm_regulator_data *reg;
782 const struct of_device_id *match;
783 struct regulator_config config = { };
784 struct regulator_dev *rdev;
785 struct qcom_rpm_reg *vreg;
786 struct qcom_smd_rpm *rpm;
787
788 rpm = dev_get_drvdata(pdev->dev.parent);
789 if (!rpm) {
790 dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
791 return -ENODEV;
792 }
793
794 match = of_match_device(rpm_of_match, &pdev->dev);
795 if (!match) {
796 dev_err(&pdev->dev, "failed to match device\n");
797 return -ENODEV;
798 }
799
800 for (reg = match->data; reg->name; reg++) {
801 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
802 if (!vreg)
803 return -ENOMEM;
804
805 vreg->dev = &pdev->dev;
806 vreg->type = reg->type;
807 vreg->id = reg->id;
808 vreg->rpm = rpm;
809
810 memcpy(&vreg->desc, reg->desc, sizeof(vreg->desc));
811
812 vreg->desc.id = -1;
813 vreg->desc.owner = THIS_MODULE;
814 vreg->desc.type = REGULATOR_VOLTAGE;
815 vreg->desc.name = reg->name;
816 vreg->desc.supply_name = reg->supply;
817 vreg->desc.of_match = reg->name;
818
819 config.dev = &pdev->dev;
820 config.driver_data = vreg;
821 rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
822 if (IS_ERR(rdev)) {
823 dev_err(&pdev->dev, "failed to register %s\n", reg->name);
824 return PTR_ERR(rdev);
825 }
826 }
827
828 return 0;
829 }
830
831 static struct platform_driver rpm_reg_driver = {
832 .probe = rpm_reg_probe,
833 .driver = {
834 .name = "qcom_rpm_smd_regulator",
835 .of_match_table = rpm_of_match,
836 },
837 };
838
839 static int __init rpm_reg_init(void)
840 {
841 return platform_driver_register(&rpm_reg_driver);
842 }
843 subsys_initcall(rpm_reg_init);
844
845 static void __exit rpm_reg_exit(void)
846 {
847 platform_driver_unregister(&rpm_reg_driver);
848 }
849 module_exit(rpm_reg_exit)
850
851 MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
852 MODULE_LICENSE("GPL v2");