drivers/pinctrl/pinctrl-at91.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
at91_pinctrl_find_group_by_name
at91_get_groups_count
at91_get_group_name
at91_get_group_pins
at91_pin_dbg_show
at91_dt_node_to_map
at91_dt_free_map
pin_to_controller
pin_to_bank
pin_to_mask
two_bit_pin_value_shift_amount
sama5d3_get_drive_register
at91sam9x5_get_drive_register
at91_mux_disable_interrupt
at91_mux_get_pullup
at91_mux_set_pullup
at91_mux_get_output
at91_mux_set_output
at91_mux_get_multidrive
at91_mux_set_multidrive
at91_mux_set_A_periph
at91_mux_set_B_periph
at91_mux_pio3_set_A_periph
at91_mux_pio3_set_B_periph
at91_mux_pio3_set_C_periph
at91_mux_pio3_set_D_periph
at91_mux_pio3_get_periph
at91_mux_get_periph
at91_mux_get_deglitch
at91_mux_set_deglitch
at91_mux_pio3_get_deglitch
at91_mux_pio3_set_deglitch
at91_mux_pio3_get_debounce
at91_mux_pio3_set_debounce
at91_mux_pio3_get_pulldown
at91_mux_pio3_set_pulldown
at91_mux_pio3_disable_schmitt_trig
at91_mux_pio3_get_schmitt_trig
read_drive_strength
at91_mux_sama5d3_get_drivestrength
at91_mux_sam9x5_get_drivestrength
at91_mux_sam9x60_get_drivestrength
at91_mux_sam9x60_get_slewrate
set_drive_strength
at91_mux_sama5d3_set_drivestrength
at91_mux_sam9x5_set_drivestrength
at91_mux_sam9x60_set_drivestrength
at91_mux_sam9x60_set_slewrate
at91_pin_dbg
pin_check_config
at91_mux_gpio_disable
at91_mux_gpio_enable
at91_pmx_set
at91_pmx_get_funcs_count
at91_pmx_get_func_name
at91_pmx_get_groups
at91_gpio_request_enable
at91_gpio_disable_free
at91_pinconf_get
at91_pinconf_set
at91_pinconf_dbg_show
at91_pinconf_group_dbg_show
at91_pinctrl_child_count
at91_pinctrl_mux_mask
at91_pinctrl_parse_groups
at91_pinctrl_parse_functions
at91_pinctrl_probe_dt
at91_pinctrl_probe
at91_gpio_get_direction
at91_gpio_direction_input
at91_gpio_get
at91_gpio_set
at91_gpio_set_multiple
at91_gpio_direction_output
at91_gpio_dbg_show
gpio_irq_mask
gpio_irq_unmask
gpio_irq_type
alt_gpio_irq_type
gpio_irq_ack
gpio_irq_set_wake
at91_pinctrl_gpio_suspend
at91_pinctrl_gpio_resume
gpio_irq_handler
at91_gpio_of_irq_setup
at91_gpio_probe
at91_pinctrl_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * at91 pinctrl driver based on at91 pinmux core
   4  *
   5  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   6  */
   7 
   8 #include <linux/clk.h>
   9 #include <linux/err.h>
  10 #include <linux/init.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/slab.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/gpio/driver.h>
  19 #include <linux/pinctrl/machine.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 /* Since we request GPIOs from ourself */
  24 #include <linux/pinctrl/consumer.h>
  25 
  26 #include "pinctrl-at91.h"
  27 #include "core.h"
  28 
  29 #define MAX_GPIO_BANKS          5
  30 #define MAX_NB_GPIO_PER_BANK    32
  31 
  32 struct at91_pinctrl_mux_ops;
  33 
  34 struct at91_gpio_chip {
  35         struct gpio_chip        chip;
  36         struct pinctrl_gpio_range range;
  37         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
  38         int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
  39         int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
  40         int                     pioc_idx;       /* PIO bank index */
  41         void __iomem            *regbase;       /* PIO bank virtual address */
  42         struct clk              *clock;         /* associated clock */
  43         struct at91_pinctrl_mux_ops *ops;       /* ops */
  44 };
  45 
  46 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
  47 
  48 static int gpio_banks;
  49 
  50 #define PULL_UP         (1 << 0)
  51 #define MULTI_DRIVE     (1 << 1)
  52 #define DEGLITCH        (1 << 2)
  53 #define PULL_DOWN       (1 << 3)
  54 #define DIS_SCHMIT      (1 << 4)
  55 #define DRIVE_STRENGTH_SHIFT    5
  56 #define DRIVE_STRENGTH_MASK             0x3
  57 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
  58 #define OUTPUT          (1 << 7)
  59 #define OUTPUT_VAL_SHIFT        8
  60 #define OUTPUT_VAL      (0x1 << OUTPUT_VAL_SHIFT)
  61 #define SLEWRATE_SHIFT  9
  62 #define SLEWRATE_MASK   0x1
  63 #define SLEWRATE        (SLEWRATE_MASK << SLEWRATE_SHIFT)
  64 #define DEBOUNCE        (1 << 16)
  65 #define DEBOUNCE_VAL_SHIFT      17
  66 #define DEBOUNCE_VAL    (0x3fff << DEBOUNCE_VAL_SHIFT)
  67 
  68 /**
  69  * These defines will translated the dt binding settings to our internal
  70  * settings. They are not necessarily the same value as the register setting.
  71  * The actual drive strength current of low, medium and high must be looked up
  72  * from the corresponding device datasheet. This value is different for pins
  73  * that are even in the same banks. It is also dependent on VCC.
  74  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
  75  * strength when there is no dt config for it.
  76  */
  77 enum drive_strength_bit {
  78         DRIVE_STRENGTH_BIT_DEF,
  79         DRIVE_STRENGTH_BIT_LOW,
  80         DRIVE_STRENGTH_BIT_MED,
  81         DRIVE_STRENGTH_BIT_HI,
  82 };
  83 
  84 #define DRIVE_STRENGTH_BIT_MSK(name)    (DRIVE_STRENGTH_BIT_##name << \
  85                                          DRIVE_STRENGTH_SHIFT)
  86 
  87 enum slewrate_bit {
  88         SLEWRATE_BIT_DIS,
  89         SLEWRATE_BIT_ENA,
  90 };
  91 
  92 #define SLEWRATE_BIT_MSK(name)          (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
  93 
  94 /**
  95  * struct at91_pmx_func - describes AT91 pinmux functions
  96  * @name: the name of this specific function
  97  * @groups: corresponding pin groups
  98  * @ngroups: the number of groups
  99  */
 100 struct at91_pmx_func {
 101         const char      *name;
 102         const char      **groups;
 103         unsigned        ngroups;
 104 };
 105 
 106 enum at91_mux {
 107         AT91_MUX_GPIO = 0,
 108         AT91_MUX_PERIPH_A = 1,
 109         AT91_MUX_PERIPH_B = 2,
 110         AT91_MUX_PERIPH_C = 3,
 111         AT91_MUX_PERIPH_D = 4,
 112 };
 113 
 114 /**
 115  * struct at91_pmx_pin - describes an At91 pin mux
 116  * @bank: the bank of the pin
 117  * @pin: the pin number in the @bank
 118  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
 119  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
 120  */
 121 struct at91_pmx_pin {
 122         uint32_t        bank;
 123         uint32_t        pin;
 124         enum at91_mux   mux;
 125         unsigned long   conf;
 126 };
 127 
 128 /**
 129  * struct at91_pin_group - describes an At91 pin group
 130  * @name: the name of this specific pin group
 131  * @pins_conf: the mux mode for each pin in this group. The size of this
 132  *      array is the same as pins.
 133  * @pins: an array of discrete physical pins used in this group, taken
 134  *      from the driver-local pin enumeration space
 135  * @npins: the number of pins in this group array, i.e. the number of
 136  *      elements in .pins so we can iterate over that array
 137  */
 138 struct at91_pin_group {
 139         const char              *name;
 140         struct at91_pmx_pin     *pins_conf;
 141         unsigned int            *pins;
 142         unsigned                npins;
 143 };
 144 
 145 /**
 146  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
 147  * on new IP with support for periph C and D the way to mux in
 148  * periph A and B has changed
 149  * So provide the right call back
 150  * if not present means the IP does not support it
 151  * @get_periph: return the periph mode configured
 152  * @mux_A_periph: mux as periph A
 153  * @mux_B_periph: mux as periph B
 154  * @mux_C_periph: mux as periph C
 155  * @mux_D_periph: mux as periph D
 156  * @get_deglitch: get deglitch status
 157  * @set_deglitch: enable/disable deglitch
 158  * @get_debounce: get debounce status
 159  * @set_debounce: enable/disable debounce
 160  * @get_pulldown: get pulldown status
 161  * @set_pulldown: enable/disable pulldown
 162  * @get_schmitt_trig: get schmitt trigger status
 163  * @disable_schmitt_trig: disable schmitt trigger
 164  * @irq_type: return irq type
 165  */
 166 struct at91_pinctrl_mux_ops {
 167         enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
 168         void (*mux_A_periph)(void __iomem *pio, unsigned mask);
 169         void (*mux_B_periph)(void __iomem *pio, unsigned mask);
 170         void (*mux_C_periph)(void __iomem *pio, unsigned mask);
 171         void (*mux_D_periph)(void __iomem *pio, unsigned mask);
 172         bool (*get_deglitch)(void __iomem *pio, unsigned pin);
 173         void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
 174         bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
 175         void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
 176         bool (*get_pulldown)(void __iomem *pio, unsigned pin);
 177         void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
 178         bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
 179         void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
 180         unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
 181         void (*set_drivestrength)(void __iomem *pio, unsigned pin,
 182                                         u32 strength);
 183         unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
 184         void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
 185         /* irq */
 186         int (*irq_type)(struct irq_data *d, unsigned type);
 187 };
 188 
 189 static int gpio_irq_type(struct irq_data *d, unsigned type);
 190 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
 191 
 192 struct at91_pinctrl {
 193         struct device           *dev;
 194         struct pinctrl_dev      *pctl;
 195 
 196         int                     nactive_banks;
 197 
 198         uint32_t                *mux_mask;
 199         int                     nmux;
 200 
 201         struct at91_pmx_func    *functions;
 202         int                     nfunctions;
 203 
 204         struct at91_pin_group   *groups;
 205         int                     ngroups;
 206 
 207         struct at91_pinctrl_mux_ops *ops;
 208 };
 209 
 210 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
 211                                 const struct at91_pinctrl *info,
 212                                 const char *name)
 213 {
 214         const struct at91_pin_group *grp = NULL;
 215         int i;
 216 
 217         for (i = 0; i < info->ngroups; i++) {
 218                 if (strcmp(info->groups[i].name, name))
 219                         continue;
 220 
 221                 grp = &info->groups[i];
 222                 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
 223                 break;
 224         }
 225 
 226         return grp;
 227 }
 228 
 229 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
 230 {
 231         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 232 
 233         return info->ngroups;
 234 }
 235 
 236 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
 237                                        unsigned selector)
 238 {
 239         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 240 
 241         return info->groups[selector].name;
 242 }
 243 
 244 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 245                                const unsigned **pins,
 246                                unsigned *npins)
 247 {
 248         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 249 
 250         if (selector >= info->ngroups)
 251                 return -EINVAL;
 252 
 253         *pins = info->groups[selector].pins;
 254         *npins = info->groups[selector].npins;
 255 
 256         return 0;
 257 }
 258 
 259 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 260                    unsigned offset)
 261 {
 262         seq_printf(s, "%s", dev_name(pctldev->dev));
 263 }
 264 
 265 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
 266                         struct device_node *np,
 267                         struct pinctrl_map **map, unsigned *num_maps)
 268 {
 269         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 270         const struct at91_pin_group *grp;
 271         struct pinctrl_map *new_map;
 272         struct device_node *parent;
 273         int map_num = 1;
 274         int i;
 275 
 276         /*
 277          * first find the group of this node and check if we need to create
 278          * config maps for pins
 279          */
 280         grp = at91_pinctrl_find_group_by_name(info, np->name);
 281         if (!grp) {
 282                 dev_err(info->dev, "unable to find group for node %pOFn\n",
 283                         np);
 284                 return -EINVAL;
 285         }
 286 
 287         map_num += grp->npins;
 288         new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
 289                                GFP_KERNEL);
 290         if (!new_map)
 291                 return -ENOMEM;
 292 
 293         *map = new_map;
 294         *num_maps = map_num;
 295 
 296         /* create mux map */
 297         parent = of_get_parent(np);
 298         if (!parent) {
 299                 devm_kfree(pctldev->dev, new_map);
 300                 return -EINVAL;
 301         }
 302         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 303         new_map[0].data.mux.function = parent->name;
 304         new_map[0].data.mux.group = np->name;
 305         of_node_put(parent);
 306 
 307         /* create config map */
 308         new_map++;
 309         for (i = 0; i < grp->npins; i++) {
 310                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 311                 new_map[i].data.configs.group_or_pin =
 312                                 pin_get_name(pctldev, grp->pins[i]);
 313                 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
 314                 new_map[i].data.configs.num_configs = 1;
 315         }
 316 
 317         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 318                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 319 
 320         return 0;
 321 }
 322 
 323 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
 324                                 struct pinctrl_map *map, unsigned num_maps)
 325 {
 326 }
 327 
 328 static const struct pinctrl_ops at91_pctrl_ops = {
 329         .get_groups_count       = at91_get_groups_count,
 330         .get_group_name         = at91_get_group_name,
 331         .get_group_pins         = at91_get_group_pins,
 332         .pin_dbg_show           = at91_pin_dbg_show,
 333         .dt_node_to_map         = at91_dt_node_to_map,
 334         .dt_free_map            = at91_dt_free_map,
 335 };
 336 
 337 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
 338                                  unsigned int bank)
 339 {
 340         if (!gpio_chips[bank])
 341                 return NULL;
 342 
 343         return gpio_chips[bank]->regbase;
 344 }
 345 
 346 static inline int pin_to_bank(unsigned pin)
 347 {
 348         return pin /= MAX_NB_GPIO_PER_BANK;
 349 }
 350 
 351 static unsigned pin_to_mask(unsigned int pin)
 352 {
 353         return 1 << pin;
 354 }
 355 
 356 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
 357 {
 358         /* return the shift value for a pin for "two bit" per pin registers,
 359          * i.e. drive strength */
 360         return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
 361                         ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
 362 }
 363 
 364 static unsigned sama5d3_get_drive_register(unsigned int pin)
 365 {
 366         /* drive strength is split between two registers
 367          * with two bits per pin */
 368         return (pin >= MAX_NB_GPIO_PER_BANK/2)
 369                         ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
 370 }
 371 
 372 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
 373 {
 374         /* drive strength is split between two registers
 375          * with two bits per pin */
 376         return (pin >= MAX_NB_GPIO_PER_BANK/2)
 377                         ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
 378 }
 379 
 380 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
 381 {
 382         writel_relaxed(mask, pio + PIO_IDR);
 383 }
 384 
 385 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
 386 {
 387         return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
 388 }
 389 
 390 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
 391 {
 392         if (on)
 393                 writel_relaxed(mask, pio + PIO_PPDDR);
 394 
 395         writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
 396 }
 397 
 398 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
 399 {
 400         *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
 401         return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
 402 }
 403 
 404 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
 405                                 bool is_on, bool val)
 406 {
 407         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
 408         writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
 409 }
 410 
 411 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
 412 {
 413         return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
 414 }
 415 
 416 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
 417 {
 418         writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
 419 }
 420 
 421 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
 422 {
 423         writel_relaxed(mask, pio + PIO_ASR);
 424 }
 425 
 426 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
 427 {
 428         writel_relaxed(mask, pio + PIO_BSR);
 429 }
 430 
 431 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
 432 {
 433 
 434         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
 435                                                 pio + PIO_ABCDSR1);
 436         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
 437                                                 pio + PIO_ABCDSR2);
 438 }
 439 
 440 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
 441 {
 442         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
 443                                                 pio + PIO_ABCDSR1);
 444         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
 445                                                 pio + PIO_ABCDSR2);
 446 }
 447 
 448 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
 449 {
 450         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
 451         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
 452 }
 453 
 454 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
 455 {
 456         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
 457         writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
 458 }
 459 
 460 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
 461 {
 462         unsigned select;
 463 
 464         if (readl_relaxed(pio + PIO_PSR) & mask)
 465                 return AT91_MUX_GPIO;
 466 
 467         select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
 468         select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
 469 
 470         return select + 1;
 471 }
 472 
 473 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
 474 {
 475         unsigned select;
 476 
 477         if (readl_relaxed(pio + PIO_PSR) & mask)
 478                 return AT91_MUX_GPIO;
 479 
 480         select = readl_relaxed(pio + PIO_ABSR) & mask;
 481 
 482         return select + 1;
 483 }
 484 
 485 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
 486 {
 487         return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
 488 }
 489 
 490 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
 491 {
 492         writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
 493 }
 494 
 495 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
 496 {
 497         if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
 498                 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
 499 
 500         return false;
 501 }
 502 
 503 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
 504 {
 505         if (is_on)
 506                 writel_relaxed(mask, pio + PIO_IFSCDR);
 507         at91_mux_set_deglitch(pio, mask, is_on);
 508 }
 509 
 510 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
 511 {
 512         *div = readl_relaxed(pio + PIO_SCDR);
 513 
 514         return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
 515                ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
 516 }
 517 
 518 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
 519                                 bool is_on, u32 div)
 520 {
 521         if (is_on) {
 522                 writel_relaxed(mask, pio + PIO_IFSCER);
 523                 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
 524                 writel_relaxed(mask, pio + PIO_IFER);
 525         } else
 526                 writel_relaxed(mask, pio + PIO_IFSCDR);
 527 }
 528 
 529 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
 530 {
 531         return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
 532 }
 533 
 534 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
 535 {
 536         if (is_on)
 537                 writel_relaxed(mask, pio + PIO_PUDR);
 538 
 539         writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
 540 }
 541 
 542 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
 543 {
 544         writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
 545 }
 546 
 547 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
 548 {
 549         return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
 550 }
 551 
 552 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
 553 {
 554         unsigned tmp = readl_relaxed(reg);
 555 
 556         tmp = tmp >> two_bit_pin_value_shift_amount(pin);
 557 
 558         return tmp & DRIVE_STRENGTH_MASK;
 559 }
 560 
 561 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
 562                                                         unsigned pin)
 563 {
 564         unsigned tmp = read_drive_strength(pio +
 565                                         sama5d3_get_drive_register(pin), pin);
 566 
 567         /* SAMA5 strength is 1:1 with our defines,
 568          * except 0 is equivalent to low per datasheet */
 569         if (!tmp)
 570                 tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
 571 
 572         return tmp;
 573 }
 574 
 575 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
 576                                                         unsigned pin)
 577 {
 578         unsigned tmp = read_drive_strength(pio +
 579                                 at91sam9x5_get_drive_register(pin), pin);
 580 
 581         /* strength is inverse in SAM9x5s hardware with the pinctrl defines
 582          * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
 583         tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
 584 
 585         return tmp;
 586 }
 587 
 588 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
 589                                                    unsigned pin)
 590 {
 591         unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
 592 
 593         if (tmp & BIT(pin))
 594                 return DRIVE_STRENGTH_BIT_HI;
 595 
 596         return DRIVE_STRENGTH_BIT_LOW;
 597 }
 598 
 599 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
 600 {
 601         unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
 602 
 603         if ((tmp & BIT(pin)))
 604                 return SLEWRATE_BIT_ENA;
 605 
 606         return SLEWRATE_BIT_DIS;
 607 }
 608 
 609 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
 610 {
 611         unsigned tmp = readl_relaxed(reg);
 612         unsigned shift = two_bit_pin_value_shift_amount(pin);
 613 
 614         tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
 615         tmp |= strength << shift;
 616 
 617         writel_relaxed(tmp, reg);
 618 }
 619 
 620 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
 621                                                 u32 setting)
 622 {
 623         /* do nothing if setting is zero */
 624         if (!setting)
 625                 return;
 626 
 627         /* strength is 1 to 1 with setting for SAMA5 */
 628         set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
 629 }
 630 
 631 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
 632                                                 u32 setting)
 633 {
 634         /* do nothing if setting is zero */
 635         if (!setting)
 636                 return;
 637 
 638         /* strength is inverse on SAM9x5s with our defines
 639          * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
 640         setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
 641 
 642         set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
 643                                 setting);
 644 }
 645 
 646 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
 647                                                u32 setting)
 648 {
 649         unsigned int tmp;
 650 
 651         if (setting <= DRIVE_STRENGTH_BIT_DEF ||
 652             setting == DRIVE_STRENGTH_BIT_MED ||
 653             setting > DRIVE_STRENGTH_BIT_HI)
 654                 return;
 655 
 656         tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
 657 
 658         /* Strength is 0: low, 1: hi */
 659         if (setting == DRIVE_STRENGTH_BIT_LOW)
 660                 tmp &= ~BIT(pin);
 661         else
 662                 tmp |= BIT(pin);
 663 
 664         writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
 665 }
 666 
 667 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
 668                                           u32 setting)
 669 {
 670         unsigned int tmp;
 671 
 672         if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
 673                 return;
 674 
 675         tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
 676 
 677         if (setting == SLEWRATE_BIT_DIS)
 678                 tmp &= ~BIT(pin);
 679         else
 680                 tmp |= BIT(pin);
 681 
 682         writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
 683 }
 684 
 685 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
 686         .get_periph     = at91_mux_get_periph,
 687         .mux_A_periph   = at91_mux_set_A_periph,
 688         .mux_B_periph   = at91_mux_set_B_periph,
 689         .get_deglitch   = at91_mux_get_deglitch,
 690         .set_deglitch   = at91_mux_set_deglitch,
 691         .irq_type       = gpio_irq_type,
 692 };
 693 
 694 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
 695         .get_periph     = at91_mux_pio3_get_periph,
 696         .mux_A_periph   = at91_mux_pio3_set_A_periph,
 697         .mux_B_periph   = at91_mux_pio3_set_B_periph,
 698         .mux_C_periph   = at91_mux_pio3_set_C_periph,
 699         .mux_D_periph   = at91_mux_pio3_set_D_periph,
 700         .get_deglitch   = at91_mux_pio3_get_deglitch,
 701         .set_deglitch   = at91_mux_pio3_set_deglitch,
 702         .get_debounce   = at91_mux_pio3_get_debounce,
 703         .set_debounce   = at91_mux_pio3_set_debounce,
 704         .get_pulldown   = at91_mux_pio3_get_pulldown,
 705         .set_pulldown   = at91_mux_pio3_set_pulldown,
 706         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
 707         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
 708         .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
 709         .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
 710         .irq_type       = alt_gpio_irq_type,
 711 };
 712 
 713 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
 714         .get_periph     = at91_mux_pio3_get_periph,
 715         .mux_A_periph   = at91_mux_pio3_set_A_periph,
 716         .mux_B_periph   = at91_mux_pio3_set_B_periph,
 717         .mux_C_periph   = at91_mux_pio3_set_C_periph,
 718         .mux_D_periph   = at91_mux_pio3_set_D_periph,
 719         .get_deglitch   = at91_mux_pio3_get_deglitch,
 720         .set_deglitch   = at91_mux_pio3_set_deglitch,
 721         .get_debounce   = at91_mux_pio3_get_debounce,
 722         .set_debounce   = at91_mux_pio3_set_debounce,
 723         .get_pulldown   = at91_mux_pio3_get_pulldown,
 724         .set_pulldown   = at91_mux_pio3_set_pulldown,
 725         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
 726         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
 727         .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
 728         .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
 729         .get_slewrate   = at91_mux_sam9x60_get_slewrate,
 730         .set_slewrate   = at91_mux_sam9x60_set_slewrate,
 731         .irq_type       = alt_gpio_irq_type,
 732 
 733 };
 734 
 735 static struct at91_pinctrl_mux_ops sama5d3_ops = {
 736         .get_periph     = at91_mux_pio3_get_periph,
 737         .mux_A_periph   = at91_mux_pio3_set_A_periph,
 738         .mux_B_periph   = at91_mux_pio3_set_B_periph,
 739         .mux_C_periph   = at91_mux_pio3_set_C_periph,
 740         .mux_D_periph   = at91_mux_pio3_set_D_periph,
 741         .get_deglitch   = at91_mux_pio3_get_deglitch,
 742         .set_deglitch   = at91_mux_pio3_set_deglitch,
 743         .get_debounce   = at91_mux_pio3_get_debounce,
 744         .set_debounce   = at91_mux_pio3_set_debounce,
 745         .get_pulldown   = at91_mux_pio3_get_pulldown,
 746         .set_pulldown   = at91_mux_pio3_set_pulldown,
 747         .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
 748         .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
 749         .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
 750         .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
 751         .irq_type       = alt_gpio_irq_type,
 752 };
 753 
 754 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
 755 {
 756         if (pin->mux) {
 757                 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
 758                         pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
 759         } else {
 760                 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
 761                         pin->bank + 'A', pin->pin, pin->conf);
 762         }
 763 }
 764 
 765 static int pin_check_config(struct at91_pinctrl *info, const char *name,
 766                             int index, const struct at91_pmx_pin *pin)
 767 {
 768         int mux;
 769 
 770         /* check if it's a valid config */
 771         if (pin->bank >= gpio_banks) {
 772                 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
 773                         name, index, pin->bank, gpio_banks);
 774                 return -EINVAL;
 775         }
 776 
 777         if (!gpio_chips[pin->bank]) {
 778                 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
 779                         name, index, pin->bank);
 780                 return -ENXIO;
 781         }
 782 
 783         if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
 784                 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
 785                         name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
 786                 return -EINVAL;
 787         }
 788 
 789         if (!pin->mux)
 790                 return 0;
 791 
 792         mux = pin->mux - 1;
 793 
 794         if (mux >= info->nmux) {
 795                 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
 796                         name, index, mux, info->nmux);
 797                 return -EINVAL;
 798         }
 799 
 800         if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
 801                 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
 802                         name, index, mux, pin->bank + 'A', pin->pin);
 803                 return -EINVAL;
 804         }
 805 
 806         return 0;
 807 }
 808 
 809 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
 810 {
 811         writel_relaxed(mask, pio + PIO_PDR);
 812 }
 813 
 814 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
 815 {
 816         writel_relaxed(mask, pio + PIO_PER);
 817         writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
 818 }
 819 
 820 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 821                         unsigned group)
 822 {
 823         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 824         const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
 825         const struct at91_pmx_pin *pin;
 826         uint32_t npins = info->groups[group].npins;
 827         int i, ret;
 828         unsigned mask;
 829         void __iomem *pio;
 830 
 831         dev_dbg(info->dev, "enable function %s group %s\n",
 832                 info->functions[selector].name, info->groups[group].name);
 833 
 834         /* first check that all the pins of the group are valid with a valid
 835          * parameter */
 836         for (i = 0; i < npins; i++) {
 837                 pin = &pins_conf[i];
 838                 ret = pin_check_config(info, info->groups[group].name, i, pin);
 839                 if (ret)
 840                         return ret;
 841         }
 842 
 843         for (i = 0; i < npins; i++) {
 844                 pin = &pins_conf[i];
 845                 at91_pin_dbg(info->dev, pin);
 846                 pio = pin_to_controller(info, pin->bank);
 847 
 848                 if (!pio)
 849                         continue;
 850 
 851                 mask = pin_to_mask(pin->pin);
 852                 at91_mux_disable_interrupt(pio, mask);
 853                 switch (pin->mux) {
 854                 case AT91_MUX_GPIO:
 855                         at91_mux_gpio_enable(pio, mask, 1);
 856                         break;
 857                 case AT91_MUX_PERIPH_A:
 858                         info->ops->mux_A_periph(pio, mask);
 859                         break;
 860                 case AT91_MUX_PERIPH_B:
 861                         info->ops->mux_B_periph(pio, mask);
 862                         break;
 863                 case AT91_MUX_PERIPH_C:
 864                         if (!info->ops->mux_C_periph)
 865                                 return -EINVAL;
 866                         info->ops->mux_C_periph(pio, mask);
 867                         break;
 868                 case AT91_MUX_PERIPH_D:
 869                         if (!info->ops->mux_D_periph)
 870                                 return -EINVAL;
 871                         info->ops->mux_D_periph(pio, mask);
 872                         break;
 873                 }
 874                 if (pin->mux)
 875                         at91_mux_gpio_disable(pio, mask);
 876         }
 877 
 878         return 0;
 879 }
 880 
 881 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 882 {
 883         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 884 
 885         return info->nfunctions;
 886 }
 887 
 888 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
 889                                           unsigned selector)
 890 {
 891         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 892 
 893         return info->functions[selector].name;
 894 }
 895 
 896 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 897                                const char * const **groups,
 898                                unsigned * const num_groups)
 899 {
 900         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 901 
 902         *groups = info->functions[selector].groups;
 903         *num_groups = info->functions[selector].ngroups;
 904 
 905         return 0;
 906 }
 907 
 908 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
 909                                     struct pinctrl_gpio_range *range,
 910                                     unsigned offset)
 911 {
 912         struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 913         struct at91_gpio_chip *at91_chip;
 914         struct gpio_chip *chip;
 915         unsigned mask;
 916 
 917         if (!range) {
 918                 dev_err(npct->dev, "invalid range\n");
 919                 return -EINVAL;
 920         }
 921         if (!range->gc) {
 922                 dev_err(npct->dev, "missing GPIO chip in range\n");
 923                 return -EINVAL;
 924         }
 925         chip = range->gc;
 926         at91_chip = gpiochip_get_data(chip);
 927 
 928         dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
 929 
 930         mask = 1 << (offset - chip->base);
 931 
 932         dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
 933                 offset, 'A' + range->id, offset - chip->base, mask);
 934 
 935         writel_relaxed(mask, at91_chip->regbase + PIO_PER);
 936 
 937         return 0;
 938 }
 939 
 940 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
 941                                    struct pinctrl_gpio_range *range,
 942                                    unsigned offset)
 943 {
 944         struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 945 
 946         dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
 947         /* Set the pin to some default state, GPIO is usually default */
 948 }
 949 
 950 static const struct pinmux_ops at91_pmx_ops = {
 951         .get_functions_count    = at91_pmx_get_funcs_count,
 952         .get_function_name      = at91_pmx_get_func_name,
 953         .get_function_groups    = at91_pmx_get_groups,
 954         .set_mux                = at91_pmx_set,
 955         .gpio_request_enable    = at91_gpio_request_enable,
 956         .gpio_disable_free      = at91_gpio_disable_free,
 957 };
 958 
 959 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
 960                              unsigned pin_id, unsigned long *config)
 961 {
 962         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 963         void __iomem *pio;
 964         unsigned pin;
 965         int div;
 966         bool out;
 967 
 968         *config = 0;
 969         dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
 970         pio = pin_to_controller(info, pin_to_bank(pin_id));
 971 
 972         if (!pio)
 973                 return -EINVAL;
 974 
 975         pin = pin_id % MAX_NB_GPIO_PER_BANK;
 976 
 977         if (at91_mux_get_multidrive(pio, pin))
 978                 *config |= MULTI_DRIVE;
 979 
 980         if (at91_mux_get_pullup(pio, pin))
 981                 *config |= PULL_UP;
 982 
 983         if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
 984                 *config |= DEGLITCH;
 985         if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
 986                 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
 987         if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
 988                 *config |= PULL_DOWN;
 989         if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
 990                 *config |= DIS_SCHMIT;
 991         if (info->ops->get_drivestrength)
 992                 *config |= (info->ops->get_drivestrength(pio, pin)
 993                                 << DRIVE_STRENGTH_SHIFT);
 994         if (info->ops->get_slewrate)
 995                 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
 996         if (at91_mux_get_output(pio, pin, &out))
 997                 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
 998 
 999         return 0;
1000 }
1001 
1002 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1003                              unsigned pin_id, unsigned long *configs,
1004                              unsigned num_configs)
1005 {
1006         struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1007         unsigned mask;
1008         void __iomem *pio;
1009         int i;
1010         unsigned long config;
1011         unsigned pin;
1012 
1013         for (i = 0; i < num_configs; i++) {
1014                 config = configs[i];
1015 
1016                 dev_dbg(info->dev,
1017                         "%s:%d, pin_id=%d, config=0x%lx",
1018                         __func__, __LINE__, pin_id, config);
1019                 pio = pin_to_controller(info, pin_to_bank(pin_id));
1020 
1021                 if (!pio)
1022                         return -EINVAL;
1023 
1024                 pin = pin_id % MAX_NB_GPIO_PER_BANK;
1025                 mask = pin_to_mask(pin);
1026 
1027                 if (config & PULL_UP && config & PULL_DOWN)
1028                         return -EINVAL;
1029 
1030                 at91_mux_set_output(pio, mask, config & OUTPUT,
1031                                     (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1032                 at91_mux_set_pullup(pio, mask, config & PULL_UP);
1033                 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1034                 if (info->ops->set_deglitch)
1035                         info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1036                 if (info->ops->set_debounce)
1037                         info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1038                                 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1039                 if (info->ops->set_pulldown)
1040                         info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1041                 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1042                         info->ops->disable_schmitt_trig(pio, mask);
1043                 if (info->ops->set_drivestrength)
1044                         info->ops->set_drivestrength(pio, pin,
1045                                 (config & DRIVE_STRENGTH)
1046                                         >> DRIVE_STRENGTH_SHIFT);
1047                 if (info->ops->set_slewrate)
1048                         info->ops->set_slewrate(pio, pin,
1049                                 (config & SLEWRATE) >> SLEWRATE_SHIFT);
1050 
1051         } /* for each config */
1052 
1053         return 0;
1054 }
1055 
1056 #define DBG_SHOW_FLAG(flag) do {                \
1057         if (config & flag) {                    \
1058                 if (num_conf)                   \
1059                         seq_puts(s, "|");       \
1060                 seq_puts(s, #flag);             \
1061                 num_conf++;                     \
1062         }                                       \
1063 } while (0)
1064 
1065 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1066         if ((config & mask) == flag) {          \
1067                 if (num_conf)                   \
1068                         seq_puts(s, "|");       \
1069                 seq_puts(s, #name);             \
1070                 num_conf++;                     \
1071         }                                       \
1072 } while (0)
1073 
1074 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1075                                    struct seq_file *s, unsigned pin_id)
1076 {
1077         unsigned long config;
1078         int val, num_conf = 0;
1079 
1080         at91_pinconf_get(pctldev, pin_id, &config);
1081 
1082         DBG_SHOW_FLAG(MULTI_DRIVE);
1083         DBG_SHOW_FLAG(PULL_UP);
1084         DBG_SHOW_FLAG(PULL_DOWN);
1085         DBG_SHOW_FLAG(DIS_SCHMIT);
1086         DBG_SHOW_FLAG(DEGLITCH);
1087         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1088                              DRIVE_STRENGTH_LOW);
1089         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1090                              DRIVE_STRENGTH_MED);
1091         DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1092                              DRIVE_STRENGTH_HI);
1093         DBG_SHOW_FLAG(SLEWRATE);
1094         DBG_SHOW_FLAG(DEBOUNCE);
1095         if (config & DEBOUNCE) {
1096                 val = config >> DEBOUNCE_VAL_SHIFT;
1097                 seq_printf(s, "(%d)", val);
1098         }
1099 
1100         return;
1101 }
1102 
1103 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1104                                          struct seq_file *s, unsigned group)
1105 {
1106 }
1107 
1108 static const struct pinconf_ops at91_pinconf_ops = {
1109         .pin_config_get                 = at91_pinconf_get,
1110         .pin_config_set                 = at91_pinconf_set,
1111         .pin_config_dbg_show            = at91_pinconf_dbg_show,
1112         .pin_config_group_dbg_show      = at91_pinconf_group_dbg_show,
1113 };
1114 
1115 static struct pinctrl_desc at91_pinctrl_desc = {
1116         .pctlops        = &at91_pctrl_ops,
1117         .pmxops         = &at91_pmx_ops,
1118         .confops        = &at91_pinconf_ops,
1119         .owner          = THIS_MODULE,
1120 };
1121 
1122 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1123 
1124 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1125                                      struct device_node *np)
1126 {
1127         struct device_node *child;
1128 
1129         for_each_child_of_node(np, child) {
1130                 if (of_device_is_compatible(child, gpio_compat)) {
1131                         if (of_device_is_available(child))
1132                                 info->nactive_banks++;
1133                 } else {
1134                         info->nfunctions++;
1135                         info->ngroups += of_get_child_count(child);
1136                 }
1137         }
1138 }
1139 
1140 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1141                                  struct device_node *np)
1142 {
1143         int ret = 0;
1144         int size;
1145         const __be32 *list;
1146 
1147         list = of_get_property(np, "atmel,mux-mask", &size);
1148         if (!list) {
1149                 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1150                 return -EINVAL;
1151         }
1152 
1153         size /= sizeof(*list);
1154         if (!size || size % gpio_banks) {
1155                 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1156                 return -EINVAL;
1157         }
1158         info->nmux = size / gpio_banks;
1159 
1160         info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1161                                       GFP_KERNEL);
1162         if (!info->mux_mask)
1163                 return -ENOMEM;
1164 
1165         ret = of_property_read_u32_array(np, "atmel,mux-mask",
1166                                           info->mux_mask, size);
1167         if (ret)
1168                 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1169         return ret;
1170 }
1171 
1172 static int at91_pinctrl_parse_groups(struct device_node *np,
1173                                      struct at91_pin_group *grp,
1174                                      struct at91_pinctrl *info, u32 index)
1175 {
1176         struct at91_pmx_pin *pin;
1177         int size;
1178         const __be32 *list;
1179         int i, j;
1180 
1181         dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1182 
1183         /* Initialise group */
1184         grp->name = np->name;
1185 
1186         /*
1187          * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1188          * do sanity check and calculate pins number
1189          */
1190         list = of_get_property(np, "atmel,pins", &size);
1191         /* we do not check return since it's safe node passed down */
1192         size /= sizeof(*list);
1193         if (!size || size % 4) {
1194                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1195                 return -EINVAL;
1196         }
1197 
1198         grp->npins = size / 4;
1199         pin = grp->pins_conf = devm_kcalloc(info->dev,
1200                                             grp->npins,
1201                                             sizeof(struct at91_pmx_pin),
1202                                             GFP_KERNEL);
1203         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1204                                  GFP_KERNEL);
1205         if (!grp->pins_conf || !grp->pins)
1206                 return -ENOMEM;
1207 
1208         for (i = 0, j = 0; i < size; i += 4, j++) {
1209                 pin->bank = be32_to_cpu(*list++);
1210                 pin->pin = be32_to_cpu(*list++);
1211                 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1212                 pin->mux = be32_to_cpu(*list++);
1213                 pin->conf = be32_to_cpu(*list++);
1214 
1215                 at91_pin_dbg(info->dev, pin);
1216                 pin++;
1217         }
1218 
1219         return 0;
1220 }
1221 
1222 static int at91_pinctrl_parse_functions(struct device_node *np,
1223                                         struct at91_pinctrl *info, u32 index)
1224 {
1225         struct device_node *child;
1226         struct at91_pmx_func *func;
1227         struct at91_pin_group *grp;
1228         int ret;
1229         static u32 grp_index;
1230         u32 i = 0;
1231 
1232         dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1233 
1234         func = &info->functions[index];
1235 
1236         /* Initialise function */
1237         func->name = np->name;
1238         func->ngroups = of_get_child_count(np);
1239         if (func->ngroups == 0) {
1240                 dev_err(info->dev, "no groups defined\n");
1241                 return -EINVAL;
1242         }
1243         func->groups = devm_kcalloc(info->dev,
1244                         func->ngroups, sizeof(char *), GFP_KERNEL);
1245         if (!func->groups)
1246                 return -ENOMEM;
1247 
1248         for_each_child_of_node(np, child) {
1249                 func->groups[i] = child->name;
1250                 grp = &info->groups[grp_index++];
1251                 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1252                 if (ret) {
1253                         of_node_put(child);
1254                         return ret;
1255                 }
1256         }
1257 
1258         return 0;
1259 }
1260 
1261 static const struct of_device_id at91_pinctrl_of_match[] = {
1262         { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1263         { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1264         { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1265         { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1266         { /* sentinel */ }
1267 };
1268 
1269 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1270                                  struct at91_pinctrl *info)
1271 {
1272         int ret = 0;
1273         int i, j;
1274         uint32_t *tmp;
1275         struct device_node *np = pdev->dev.of_node;
1276         struct device_node *child;
1277 
1278         if (!np)
1279                 return -ENODEV;
1280 
1281         info->dev = &pdev->dev;
1282         info->ops = (struct at91_pinctrl_mux_ops *)
1283                 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1284         at91_pinctrl_child_count(info, np);
1285 
1286         if (gpio_banks < 1) {
1287                 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1288                 return -EINVAL;
1289         }
1290 
1291         ret = at91_pinctrl_mux_mask(info, np);
1292         if (ret)
1293                 return ret;
1294 
1295         dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1296 
1297         dev_dbg(&pdev->dev, "mux-mask\n");
1298         tmp = info->mux_mask;
1299         for (i = 0; i < gpio_banks; i++) {
1300                 for (j = 0; j < info->nmux; j++, tmp++) {
1301                         dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1302                 }
1303         }
1304 
1305         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1306         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1307         info->functions = devm_kcalloc(&pdev->dev,
1308                                         info->nfunctions,
1309                                         sizeof(struct at91_pmx_func),
1310                                         GFP_KERNEL);
1311         if (!info->functions)
1312                 return -ENOMEM;
1313 
1314         info->groups = devm_kcalloc(&pdev->dev,
1315                                         info->ngroups,
1316                                         sizeof(struct at91_pin_group),
1317                                         GFP_KERNEL);
1318         if (!info->groups)
1319                 return -ENOMEM;
1320 
1321         dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1322         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1323         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1324 
1325         i = 0;
1326 
1327         for_each_child_of_node(np, child) {
1328                 if (of_device_is_compatible(child, gpio_compat))
1329                         continue;
1330                 ret = at91_pinctrl_parse_functions(child, info, i++);
1331                 if (ret) {
1332                         dev_err(&pdev->dev, "failed to parse function\n");
1333                         of_node_put(child);
1334                         return ret;
1335                 }
1336         }
1337 
1338         return 0;
1339 }
1340 
1341 static int at91_pinctrl_probe(struct platform_device *pdev)
1342 {
1343         struct at91_pinctrl *info;
1344         struct pinctrl_pin_desc *pdesc;
1345         int ret, i, j, k, ngpio_chips_enabled = 0;
1346 
1347         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1348         if (!info)
1349                 return -ENOMEM;
1350 
1351         ret = at91_pinctrl_probe_dt(pdev, info);
1352         if (ret)
1353                 return ret;
1354 
1355         /*
1356          * We need all the GPIO drivers to probe FIRST, or we will not be able
1357          * to obtain references to the struct gpio_chip * for them, and we
1358          * need this to proceed.
1359          */
1360         for (i = 0; i < gpio_banks; i++)
1361                 if (gpio_chips[i])
1362                         ngpio_chips_enabled++;
1363 
1364         if (ngpio_chips_enabled < info->nactive_banks) {
1365                 dev_warn(&pdev->dev,
1366                          "All GPIO chips are not registered yet (%d/%d)\n",
1367                          ngpio_chips_enabled, info->nactive_banks);
1368                 devm_kfree(&pdev->dev, info);
1369                 return -EPROBE_DEFER;
1370         }
1371 
1372         at91_pinctrl_desc.name = dev_name(&pdev->dev);
1373         at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1374         at91_pinctrl_desc.pins = pdesc =
1375                 devm_kcalloc(&pdev->dev,
1376                              at91_pinctrl_desc.npins, sizeof(*pdesc),
1377                              GFP_KERNEL);
1378 
1379         if (!at91_pinctrl_desc.pins)
1380                 return -ENOMEM;
1381 
1382         for (i = 0, k = 0; i < gpio_banks; i++) {
1383                 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1384                         pdesc->number = k;
1385                         pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1386                         pdesc++;
1387                 }
1388         }
1389 
1390         platform_set_drvdata(pdev, info);
1391         info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1392                                            info);
1393 
1394         if (IS_ERR(info->pctl)) {
1395                 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1396                 return PTR_ERR(info->pctl);
1397         }
1398 
1399         /* We will handle a range of GPIO pins */
1400         for (i = 0; i < gpio_banks; i++)
1401                 if (gpio_chips[i])
1402                         pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1403 
1404         dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1405 
1406         return 0;
1407 }
1408 
1409 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1410 {
1411         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1412         void __iomem *pio = at91_gpio->regbase;
1413         unsigned mask = 1 << offset;
1414         u32 osr;
1415 
1416         osr = readl_relaxed(pio + PIO_OSR);
1417         return !(osr & mask);
1418 }
1419 
1420 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1421 {
1422         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1423         void __iomem *pio = at91_gpio->regbase;
1424         unsigned mask = 1 << offset;
1425 
1426         writel_relaxed(mask, pio + PIO_ODR);
1427         return 0;
1428 }
1429 
1430 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1431 {
1432         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1433         void __iomem *pio = at91_gpio->regbase;
1434         unsigned mask = 1 << offset;
1435         u32 pdsr;
1436 
1437         pdsr = readl_relaxed(pio + PIO_PDSR);
1438         return (pdsr & mask) != 0;
1439 }
1440 
1441 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1442                                 int val)
1443 {
1444         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1445         void __iomem *pio = at91_gpio->regbase;
1446         unsigned mask = 1 << offset;
1447 
1448         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1449 }
1450 
1451 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1452                                       unsigned long *mask, unsigned long *bits)
1453 {
1454         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1455         void __iomem *pio = at91_gpio->regbase;
1456 
1457 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1458         /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1459         uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1460         uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1461 
1462         writel_relaxed(set_mask, pio + PIO_SODR);
1463         writel_relaxed(clear_mask, pio + PIO_CODR);
1464 }
1465 
1466 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1467                                 int val)
1468 {
1469         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1470         void __iomem *pio = at91_gpio->regbase;
1471         unsigned mask = 1 << offset;
1472 
1473         writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1474         writel_relaxed(mask, pio + PIO_OER);
1475 
1476         return 0;
1477 }
1478 
1479 #ifdef CONFIG_DEBUG_FS
1480 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1481 {
1482         enum at91_mux mode;
1483         int i;
1484         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1485         void __iomem *pio = at91_gpio->regbase;
1486 
1487         for (i = 0; i < chip->ngpio; i++) {
1488                 unsigned mask = pin_to_mask(i);
1489                 const char *gpio_label;
1490 
1491                 gpio_label = gpiochip_is_requested(chip, i);
1492                 if (!gpio_label)
1493                         continue;
1494                 mode = at91_gpio->ops->get_periph(pio, mask);
1495                 seq_printf(s, "[%s] GPIO%s%d: ",
1496                            gpio_label, chip->label, i);
1497                 if (mode == AT91_MUX_GPIO) {
1498                         seq_printf(s, "[gpio] ");
1499                         seq_printf(s, "%s ",
1500                                       readl_relaxed(pio + PIO_OSR) & mask ?
1501                                       "output" : "input");
1502                         seq_printf(s, "%s\n",
1503                                       readl_relaxed(pio + PIO_PDSR) & mask ?
1504                                       "set" : "clear");
1505                 } else {
1506                         seq_printf(s, "[periph %c]\n",
1507                                    mode + 'A' - 1);
1508                 }
1509         }
1510 }
1511 #else
1512 #define at91_gpio_dbg_show      NULL
1513 #endif
1514 
1515 /* Several AIC controller irqs are dispatched through this GPIO handler.
1516  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1517  * at91_set_gpio_input() then maybe enable its glitch filter.
1518  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1519  * handler.
1520  * First implementation always triggers on rising and falling edges
1521  * whereas the newer PIO3 can be additionally configured to trigger on
1522  * level, edge with any polarity.
1523  *
1524  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1525  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1526  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1527  */
1528 
1529 static void gpio_irq_mask(struct irq_data *d)
1530 {
1531         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1532         void __iomem    *pio = at91_gpio->regbase;
1533         unsigned        mask = 1 << d->hwirq;
1534 
1535         if (pio)
1536                 writel_relaxed(mask, pio + PIO_IDR);
1537 }
1538 
1539 static void gpio_irq_unmask(struct irq_data *d)
1540 {
1541         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1542         void __iomem    *pio = at91_gpio->regbase;
1543         unsigned        mask = 1 << d->hwirq;
1544 
1545         if (pio)
1546                 writel_relaxed(mask, pio + PIO_IER);
1547 }
1548 
1549 static int gpio_irq_type(struct irq_data *d, unsigned type)
1550 {
1551         switch (type) {
1552         case IRQ_TYPE_NONE:
1553         case IRQ_TYPE_EDGE_BOTH:
1554                 return 0;
1555         default:
1556                 return -EINVAL;
1557         }
1558 }
1559 
1560 /* Alternate irq type for PIO3 support */
1561 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1562 {
1563         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1564         void __iomem    *pio = at91_gpio->regbase;
1565         unsigned        mask = 1 << d->hwirq;
1566 
1567         switch (type) {
1568         case IRQ_TYPE_EDGE_RISING:
1569                 irq_set_handler_locked(d, handle_simple_irq);
1570                 writel_relaxed(mask, pio + PIO_ESR);
1571                 writel_relaxed(mask, pio + PIO_REHLSR);
1572                 break;
1573         case IRQ_TYPE_EDGE_FALLING:
1574                 irq_set_handler_locked(d, handle_simple_irq);
1575                 writel_relaxed(mask, pio + PIO_ESR);
1576                 writel_relaxed(mask, pio + PIO_FELLSR);
1577                 break;
1578         case IRQ_TYPE_LEVEL_LOW:
1579                 irq_set_handler_locked(d, handle_level_irq);
1580                 writel_relaxed(mask, pio + PIO_LSR);
1581                 writel_relaxed(mask, pio + PIO_FELLSR);
1582                 break;
1583         case IRQ_TYPE_LEVEL_HIGH:
1584                 irq_set_handler_locked(d, handle_level_irq);
1585                 writel_relaxed(mask, pio + PIO_LSR);
1586                 writel_relaxed(mask, pio + PIO_REHLSR);
1587                 break;
1588         case IRQ_TYPE_EDGE_BOTH:
1589                 /*
1590                  * disable additional interrupt modes:
1591                  * fall back to default behavior
1592                  */
1593                 irq_set_handler_locked(d, handle_simple_irq);
1594                 writel_relaxed(mask, pio + PIO_AIMDR);
1595                 return 0;
1596         case IRQ_TYPE_NONE:
1597         default:
1598                 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1599                 return -EINVAL;
1600         }
1601 
1602         /* enable additional interrupt modes */
1603         writel_relaxed(mask, pio + PIO_AIMER);
1604 
1605         return 0;
1606 }
1607 
1608 static void gpio_irq_ack(struct irq_data *d)
1609 {
1610         /* the interrupt is already cleared before by reading ISR */
1611 }
1612 
1613 #ifdef CONFIG_PM
1614 
1615 static u32 wakeups[MAX_GPIO_BANKS];
1616 static u32 backups[MAX_GPIO_BANKS];
1617 
1618 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1619 {
1620         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1621         unsigned        bank = at91_gpio->pioc_idx;
1622         unsigned mask = 1 << d->hwirq;
1623 
1624         if (unlikely(bank >= MAX_GPIO_BANKS))
1625                 return -EINVAL;
1626 
1627         if (state)
1628                 wakeups[bank] |= mask;
1629         else
1630                 wakeups[bank] &= ~mask;
1631 
1632         irq_set_irq_wake(at91_gpio->pioc_virq, state);
1633 
1634         return 0;
1635 }
1636 
1637 void at91_pinctrl_gpio_suspend(void)
1638 {
1639         int i;
1640 
1641         for (i = 0; i < gpio_banks; i++) {
1642                 void __iomem  *pio;
1643 
1644                 if (!gpio_chips[i])
1645                         continue;
1646 
1647                 pio = gpio_chips[i]->regbase;
1648 
1649                 backups[i] = readl_relaxed(pio + PIO_IMR);
1650                 writel_relaxed(backups[i], pio + PIO_IDR);
1651                 writel_relaxed(wakeups[i], pio + PIO_IER);
1652 
1653                 if (!wakeups[i])
1654                         clk_disable_unprepare(gpio_chips[i]->clock);
1655                 else
1656                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1657                                'A'+i, wakeups[i]);
1658         }
1659 }
1660 
1661 void at91_pinctrl_gpio_resume(void)
1662 {
1663         int i;
1664 
1665         for (i = 0; i < gpio_banks; i++) {
1666                 void __iomem  *pio;
1667 
1668                 if (!gpio_chips[i])
1669                         continue;
1670 
1671                 pio = gpio_chips[i]->regbase;
1672 
1673                 if (!wakeups[i])
1674                         clk_prepare_enable(gpio_chips[i]->clock);
1675 
1676                 writel_relaxed(wakeups[i], pio + PIO_IDR);
1677                 writel_relaxed(backups[i], pio + PIO_IER);
1678         }
1679 }
1680 
1681 #else
1682 #define gpio_irq_set_wake       NULL
1683 #endif /* CONFIG_PM */
1684 
1685 static void gpio_irq_handler(struct irq_desc *desc)
1686 {
1687         struct irq_chip *chip = irq_desc_get_chip(desc);
1688         struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1689         struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1690         void __iomem    *pio = at91_gpio->regbase;
1691         unsigned long   isr;
1692         int             n;
1693 
1694         chained_irq_enter(chip, desc);
1695         for (;;) {
1696                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1697                  * When there are none pending, we're finished unless we need
1698                  * to process multiple banks (like ID_PIOCDE on sam9263).
1699                  */
1700                 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1701                 if (!isr) {
1702                         if (!at91_gpio->next)
1703                                 break;
1704                         at91_gpio = at91_gpio->next;
1705                         pio = at91_gpio->regbase;
1706                         gpio_chip = &at91_gpio->chip;
1707                         continue;
1708                 }
1709 
1710                 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1711                         generic_handle_irq(irq_find_mapping(
1712                                            gpio_chip->irq.domain, n));
1713                 }
1714         }
1715         chained_irq_exit(chip, desc);
1716         /* now it may re-trigger */
1717 }
1718 
1719 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1720                                   struct at91_gpio_chip *at91_gpio)
1721 {
1722         struct gpio_chip        *gpiochip_prev = NULL;
1723         struct at91_gpio_chip   *prev = NULL;
1724         struct irq_data         *d = irq_get_irq_data(at91_gpio->pioc_virq);
1725         struct irq_chip         *gpio_irqchip;
1726         int ret, i;
1727 
1728         gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1729         if (!gpio_irqchip)
1730                 return -ENOMEM;
1731 
1732         at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1733 
1734         gpio_irqchip->name = "GPIO";
1735         gpio_irqchip->irq_ack = gpio_irq_ack;
1736         gpio_irqchip->irq_disable = gpio_irq_mask;
1737         gpio_irqchip->irq_mask = gpio_irq_mask;
1738         gpio_irqchip->irq_unmask = gpio_irq_unmask;
1739         gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
1740         gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1741 
1742         /* Disable irqs of this PIO controller */
1743         writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1744 
1745         /*
1746          * Let the generic code handle this edge IRQ, the the chained
1747          * handler will perform the actual work of handling the parent
1748          * interrupt.
1749          */
1750         ret = gpiochip_irqchip_add(&at91_gpio->chip,
1751                                    gpio_irqchip,
1752                                    0,
1753                                    handle_edge_irq,
1754                                    IRQ_TYPE_NONE);
1755         if (ret) {
1756                 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1757                         at91_gpio->pioc_idx);
1758                 return ret;
1759         }
1760 
1761         /* The top level handler handles one bank of GPIOs, except
1762          * on some SoC it can handle up to three...
1763          * We only set up the handler for the first of the list.
1764          */
1765         gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1766         if (!gpiochip_prev) {
1767                 /* Then register the chain on the parent IRQ */
1768                 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1769                                              gpio_irqchip,
1770                                              at91_gpio->pioc_virq,
1771                                              gpio_irq_handler);
1772                 return 0;
1773         }
1774 
1775         prev = gpiochip_get_data(gpiochip_prev);
1776 
1777         /* we can only have 2 banks before */
1778         for (i = 0; i < 2; i++) {
1779                 if (prev->next) {
1780                         prev = prev->next;
1781                 } else {
1782                         prev->next = at91_gpio;
1783                         return 0;
1784                 }
1785         }
1786 
1787         return -EINVAL;
1788 }
1789 
1790 /* This structure is replicated for each GPIO block allocated at probe time */
1791 static const struct gpio_chip at91_gpio_template = {
1792         .request                = gpiochip_generic_request,
1793         .free                   = gpiochip_generic_free,
1794         .get_direction          = at91_gpio_get_direction,
1795         .direction_input        = at91_gpio_direction_input,
1796         .get                    = at91_gpio_get,
1797         .direction_output       = at91_gpio_direction_output,
1798         .set                    = at91_gpio_set,
1799         .set_multiple           = at91_gpio_set_multiple,
1800         .dbg_show               = at91_gpio_dbg_show,
1801         .can_sleep              = false,
1802         .ngpio                  = MAX_NB_GPIO_PER_BANK,
1803 };
1804 
1805 static const struct of_device_id at91_gpio_of_match[] = {
1806         { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1807         { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1808         { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1809         { /* sentinel */ }
1810 };
1811 
1812 static int at91_gpio_probe(struct platform_device *pdev)
1813 {
1814         struct device_node *np = pdev->dev.of_node;
1815         struct resource *res;
1816         struct at91_gpio_chip *at91_chip = NULL;
1817         struct gpio_chip *chip;
1818         struct pinctrl_gpio_range *range;
1819         int ret = 0;
1820         int irq, i;
1821         int alias_idx = of_alias_get_id(np, "gpio");
1822         uint32_t ngpio;
1823         char **names;
1824 
1825         BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1826         if (gpio_chips[alias_idx]) {
1827                 ret = -EBUSY;
1828                 goto err;
1829         }
1830 
1831         irq = platform_get_irq(pdev, 0);
1832         if (irq < 0) {
1833                 ret = irq;
1834                 goto err;
1835         }
1836 
1837         at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1838         if (!at91_chip) {
1839                 ret = -ENOMEM;
1840                 goto err;
1841         }
1842 
1843         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1844         at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1845         if (IS_ERR(at91_chip->regbase)) {
1846                 ret = PTR_ERR(at91_chip->regbase);
1847                 goto err;
1848         }
1849 
1850         at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1851                 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1852         at91_chip->pioc_virq = irq;
1853         at91_chip->pioc_idx = alias_idx;
1854 
1855         at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1856         if (IS_ERR(at91_chip->clock)) {
1857                 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1858                 ret = PTR_ERR(at91_chip->clock);
1859                 goto err;
1860         }
1861 
1862         ret = clk_prepare_enable(at91_chip->clock);
1863         if (ret) {
1864                 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1865                 goto clk_enable_err;
1866         }
1867 
1868         at91_chip->chip = at91_gpio_template;
1869 
1870         chip = &at91_chip->chip;
1871         chip->of_node = np;
1872         chip->label = dev_name(&pdev->dev);
1873         chip->parent = &pdev->dev;
1874         chip->owner = THIS_MODULE;
1875         chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1876 
1877         if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1878                 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1879                         pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1880                                alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1881                 else
1882                         chip->ngpio = ngpio;
1883         }
1884 
1885         names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1886                              GFP_KERNEL);
1887 
1888         if (!names) {
1889                 ret = -ENOMEM;
1890                 goto clk_enable_err;
1891         }
1892 
1893         for (i = 0; i < chip->ngpio; i++)
1894                 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1895 
1896         chip->names = (const char *const *)names;
1897 
1898         range = &at91_chip->range;
1899         range->name = chip->label;
1900         range->id = alias_idx;
1901         range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1902 
1903         range->npins = chip->ngpio;
1904         range->gc = chip;
1905 
1906         ret = gpiochip_add_data(chip, at91_chip);
1907         if (ret)
1908                 goto gpiochip_add_err;
1909 
1910         gpio_chips[alias_idx] = at91_chip;
1911         gpio_banks = max(gpio_banks, alias_idx + 1);
1912 
1913         ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1914         if (ret)
1915                 goto irq_setup_err;
1916 
1917         dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1918 
1919         return 0;
1920 
1921 irq_setup_err:
1922         gpiochip_remove(chip);
1923 gpiochip_add_err:
1924 clk_enable_err:
1925         clk_disable_unprepare(at91_chip->clock);
1926 err:
1927         dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1928 
1929         return ret;
1930 }
1931 
1932 static struct platform_driver at91_gpio_driver = {
1933         .driver = {
1934                 .name = "gpio-at91",
1935                 .of_match_table = at91_gpio_of_match,
1936         },
1937         .probe = at91_gpio_probe,
1938 };
1939 
1940 static struct platform_driver at91_pinctrl_driver = {
1941         .driver = {
1942                 .name = "pinctrl-at91",
1943                 .of_match_table = at91_pinctrl_of_match,
1944         },
1945         .probe = at91_pinctrl_probe,
1946 };
1947 
1948 static struct platform_driver * const drivers[] = {
1949         &at91_gpio_driver,
1950         &at91_pinctrl_driver,
1951 };
1952 
1953 static int __init at91_pinctrl_init(void)
1954 {
1955         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1956 }
1957 arch_initcall(at91_pinctrl_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pinctrl/pinctrl-at91.c

DEFINITIONS
