This source file includes following definitions.
- GP_ALL
- GP_ALL
- GP_ASSIGN_LAST
- NOGP_ALL
- r8a77990_pin_to_pocctrl
- r8a77990_pinmux_get_bias
- r8a77990_pinmux_set_bias
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14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16
17 #include "core.h"
18 #include "sh_pfc.h"
19
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
21
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
43
44 #define CPU_ALL_NOGP(fn) \
45 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
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67
68 #define GPSR0_17 F_(SDA4, IP7_27_24)
69 #define GPSR0_16 F_(SCL4, IP7_23_20)
70 #define GPSR0_15 F_(D15, IP7_19_16)
71 #define GPSR0_14 F_(D14, IP7_15_12)
72 #define GPSR0_13 F_(D13, IP7_11_8)
73 #define GPSR0_12 F_(D12, IP7_7_4)
74 #define GPSR0_11 F_(D11, IP7_3_0)
75 #define GPSR0_10 F_(D10, IP6_31_28)
76 #define GPSR0_9 F_(D9, IP6_27_24)
77 #define GPSR0_8 F_(D8, IP6_23_20)
78 #define GPSR0_7 F_(D7, IP6_19_16)
79 #define GPSR0_6 F_(D6, IP6_15_12)
80 #define GPSR0_5 F_(D5, IP6_11_8)
81 #define GPSR0_4 F_(D4, IP6_7_4)
82 #define GPSR0_3 F_(D3, IP6_3_0)
83 #define GPSR0_2 F_(D2, IP5_31_28)
84 #define GPSR0_1 F_(D1, IP5_27_24)
85 #define GPSR0_0 F_(D0, IP5_23_20)
86
87
88 #define GPSR1_22 F_(WE0_N, IP5_19_16)
89 #define GPSR1_21 F_(CS0_N, IP5_15_12)
90 #define GPSR1_20 FM(CLKOUT)
91 #define GPSR1_19 F_(A19, IP5_11_8)
92 #define GPSR1_18 F_(A18, IP5_7_4)
93 #define GPSR1_17 F_(A17, IP5_3_0)
94 #define GPSR1_16 F_(A16, IP4_31_28)
95 #define GPSR1_15 F_(A15, IP4_27_24)
96 #define GPSR1_14 F_(A14, IP4_23_20)
97 #define GPSR1_13 F_(A13, IP4_19_16)
98 #define GPSR1_12 F_(A12, IP4_15_12)
99 #define GPSR1_11 F_(A11, IP4_11_8)
100 #define GPSR1_10 F_(A10, IP4_7_4)
101 #define GPSR1_9 F_(A9, IP4_3_0)
102 #define GPSR1_8 F_(A8, IP3_31_28)
103 #define GPSR1_7 F_(A7, IP3_27_24)
104 #define GPSR1_6 F_(A6, IP3_23_20)
105 #define GPSR1_5 F_(A5, IP3_19_16)
106 #define GPSR1_4 F_(A4, IP3_15_12)
107 #define GPSR1_3 F_(A3, IP3_11_8)
108 #define GPSR1_2 F_(A2, IP3_7_4)
109 #define GPSR1_1 F_(A1, IP3_3_0)
110 #define GPSR1_0 F_(A0, IP2_31_28)
111
112
113 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
114 #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
115 #define GPSR2_23 F_(RD_N, IP2_19_16)
116 #define GPSR2_22 F_(BS_N, IP2_15_12)
117 #define GPSR2_21 FM(AVB_PHY_INT)
118 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
119 #define GPSR2_19 FM(AVB_RD3)
120 #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
121 #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
122 #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
123 #define GPSR2_15 FM(AVB_RXC)
124 #define GPSR2_14 FM(AVB_RX_CTL)
125 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
126 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
127 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
128 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
129 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
130 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
131 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
132 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
133 #define GPSR2_5 FM(QSPI0_SSL)
134 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
135 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
136 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
137 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
138 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
139
140
141 #define GPSR3_15 F_(SD1_WP, IP11_7_4)
142 #define GPSR3_14 F_(SD1_CD, IP11_3_0)
143 #define GPSR3_13 F_(SD0_WP, IP10_31_28)
144 #define GPSR3_12 F_(SD0_CD, IP10_27_24)
145 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
146 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
147 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
148 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
149 #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
150 #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
151 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
152 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
153 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
154 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
155 #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
156 #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
157
158
159 #define GPSR4_10 F_(SD3_DS, IP10_23_20)
160 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
161 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
162 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
163 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
164 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
165 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
166 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
167 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
168 #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
169 #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
170
171
172 #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
173 #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
174 #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
175 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
176 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
177 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
178 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
179 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
180 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
181 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
182 #define GPSR5_9 F_(RX2_A, IP12_15_12)
183 #define GPSR5_8 F_(TX2_A, IP12_11_8)
184 #define GPSR5_7 F_(SCK2_A, IP12_7_4)
185 #define GPSR5_6 F_(TX1, IP12_3_0)
186 #define GPSR5_5 F_(RX1, IP11_31_28)
187 #define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
188 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
189 #define GPSR5_2 F_(TX0_A, IP11_15_12)
190 #define GPSR5_1 F_(RX0_A, IP11_11_8)
191 #define GPSR5_0 F_(SCK0_A, IP11_27_24)
192
193
194 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
195 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
196 #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
197 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
198 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
199 #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
200 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
201 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
202 #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
203 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
204 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
205 #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
206 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
207 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
208 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
209 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
210 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
211 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
212
213
214 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246
247
248 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280
281
282 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314
315
316 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348
349 #define PINMUX_GPSR \
350 \
351 \
352 \
353 \
354 \
355 \
356 \
357 GPSR2_25 \
358 GPSR2_24 \
359 GPSR2_23 \
360 GPSR1_22 GPSR2_22 \
361 GPSR1_21 GPSR2_21 \
362 GPSR1_20 GPSR2_20 \
363 GPSR1_19 GPSR2_19 GPSR5_19 \
364 GPSR1_18 GPSR2_18 GPSR5_18 \
365 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
366 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
367 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
368 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
369 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
370 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
371 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
372 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
373 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
374 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
375 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
376 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
377 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
378 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
379 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
380 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
381 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
382 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
383
384 #define PINMUX_IPSR \
385 \
386 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
387 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
388 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
390 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
391 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
392 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
393 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
394 \
395 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
396 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
397 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
398 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
399 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
400 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
401 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
402 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
403 \
404 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
405 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
406 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
407 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
408 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
409 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
410 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
411 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
412 \
413 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
414 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
415 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
416 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
417 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
418 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
419 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
420 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
421
422
423 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
424 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
425
426
427 #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
428 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
429 #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
430 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
431 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
432 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
433 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
434 #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
435 #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
436 #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
437 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
438 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
439 #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
440 #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
441 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
442 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
443 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
444 #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
445 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
446 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
447 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
448 #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
449
450
451 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
452 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
453 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
454 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
455 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
456 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
457 #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
458 #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
459 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
460 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
461 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
462 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
463 #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
464 #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
465 #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
466 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
467 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
468 #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
469 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
470
471 #define PINMUX_MOD_SELS \
472 \
473 MOD_SEL1_31 \
474 MOD_SEL0_30_29 MOD_SEL1_30 \
475 MOD_SEL1_29 \
476 MOD_SEL0_28 MOD_SEL1_28 \
477 MOD_SEL0_27_26 \
478 MOD_SEL1_26 \
479 MOD_SEL0_25 MOD_SEL1_25 \
480 MOD_SEL0_24 MOD_SEL1_24_23_22 \
481 MOD_SEL0_23 \
482 MOD_SEL0_22 \
483 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
484 MOD_SEL0_19_18_17 MOD_SEL1_18 \
485 MOD_SEL1_17 \
486 MOD_SEL0_16 MOD_SEL1_16 \
487 MOD_SEL0_15 MOD_SEL1_15 \
488 MOD_SEL0_14 MOD_SEL1_14_13 \
489 MOD_SEL0_13_12 \
490 MOD_SEL1_12_11 \
491 MOD_SEL0_11_10 \
492 MOD_SEL1_10_9 \
493 MOD_SEL0_9 \
494 MOD_SEL0_8 MOD_SEL1_8 \
495 MOD_SEL0_7 MOD_SEL1_7 \
496 MOD_SEL0_6_5 MOD_SEL1_6_5 \
497 MOD_SEL0_4 MOD_SEL1_4 \
498 MOD_SEL0_3 \
499 MOD_SEL0_2 \
500 MOD_SEL0_1_0
501
502
503
504
505
506 #define PINMUX_STATIC \
507 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
508 FM(AVB_TD3) \
509 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
510 FM(ASEBRK) \
511 FM(MLB_REF)
512
513 enum {
514 PINMUX_RESERVED = 0,
515
516 PINMUX_DATA_BEGIN,
517 GP_ALL(DATA),
518 PINMUX_DATA_END,
519
520 #define F_(x, y)
521 #define FM(x) FN_##x,
522 PINMUX_FUNCTION_BEGIN,
523 GP_ALL(FN),
524 PINMUX_GPSR
525 PINMUX_IPSR
526 PINMUX_MOD_SELS
527 PINMUX_FUNCTION_END,
528 #undef F_
529 #undef FM
530
531 #define F_(x, y)
532 #define FM(x) x##_MARK,
533 PINMUX_MARK_BEGIN,
534 PINMUX_GPSR
535 PINMUX_IPSR
536 PINMUX_MOD_SELS
537 PINMUX_STATIC
538 PINMUX_MARK_END,
539 #undef F_
540 #undef FM
541 };
542
543 static const u16 pinmux_data[] = {
544 PINMUX_DATA_GP_ALL(),
545
546 PINMUX_SINGLE(CLKOUT),
547 PINMUX_SINGLE(AVB_PHY_INT),
548 PINMUX_SINGLE(AVB_RD3),
549 PINMUX_SINGLE(AVB_RXC),
550 PINMUX_SINGLE(AVB_RX_CTL),
551 PINMUX_SINGLE(QSPI0_SSL),
552
553
554 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
555 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
556
557 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
558 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
559
560 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
561 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
562
563 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
564 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
565
566 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
567 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
568
569 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
570 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
571 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
572 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
573
574 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
575 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
576 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
577 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
578
579 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
580 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
581 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
582 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
583
584
585 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
586 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
587 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
588 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
589
590 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
591 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
592 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
593 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
594
595 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
596 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
597 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
598 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
599
600 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
601 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
602 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
603 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
604
605 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
606 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
607 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
608 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
609
610 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
611
612 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
613
614 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
615
616
617 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
618
619 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
620
621 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
622
623 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
624 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
625 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
626 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
627 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
628 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
629
630 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
631 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
632 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
633 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
634 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
635 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
636 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
637
638 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
639 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
640 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
641 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
642 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
643 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
644 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
645
646 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
647 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
648 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
649 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
650 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
651 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
652
653 PINMUX_IPSR_GPSR(IP2_31_28, A0),
654 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
655 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
656 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
657 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
658 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
659 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
660 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
661 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
662
663
664 PINMUX_IPSR_GPSR(IP3_3_0, A1),
665 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
666 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
667 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
668 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
669 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
670 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
671 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
672 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
673
674 PINMUX_IPSR_GPSR(IP3_7_4, A2),
675 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
676 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
677 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
678 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
679 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
680 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
681 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
682
683 PINMUX_IPSR_GPSR(IP3_11_8, A3),
684 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
685 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
686 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
687 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
688 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
689 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
690 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
691
692 PINMUX_IPSR_GPSR(IP3_15_12, A4),
693 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
694 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
695 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
696 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
697 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
698 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
699
700 PINMUX_IPSR_GPSR(IP3_19_16, A5),
701 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
702 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
703 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
704 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
705 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
706 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
707
708 PINMUX_IPSR_GPSR(IP3_23_20, A6),
709 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
710 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
711 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
712 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
713
714 PINMUX_IPSR_GPSR(IP3_27_24, A7),
715 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
716 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
717 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
718 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
719
720 PINMUX_IPSR_GPSR(IP3_31_28, A8),
721 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
722 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
723 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
724 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
725 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
726 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
727 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
728
729
730 PINMUX_IPSR_GPSR(IP4_3_0, A9),
731 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
732 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
733 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
734 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
735 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
736 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
737
738 PINMUX_IPSR_GPSR(IP4_7_4, A10),
739 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
740 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
741 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
742 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
743 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
744 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
745 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
746
747 PINMUX_IPSR_GPSR(IP4_11_8, A11),
748 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
749 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
750 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
751 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
752 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
753 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
754
755 PINMUX_IPSR_GPSR(IP4_15_12, A12),
756 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
757 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
758 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
759 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
760 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
761 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
762
763 PINMUX_IPSR_GPSR(IP4_19_16, A13),
764 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
765 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
766 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
767 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
768 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
769 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
770
771 PINMUX_IPSR_GPSR(IP4_23_20, A14),
772 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
773 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
774 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
775 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
776 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
777 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
778
779 PINMUX_IPSR_GPSR(IP4_27_24, A15),
780 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
781 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
782 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
783 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
784 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
785 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
786
787 PINMUX_IPSR_GPSR(IP4_31_28, A16),
788 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
789 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
790 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
791 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
792 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
793 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
794
795
796 PINMUX_IPSR_GPSR(IP5_3_0, A17),
797 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
798 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
799 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
800 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
801 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
802
803 PINMUX_IPSR_GPSR(IP5_7_4, A18),
804 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
805 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
806 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
807 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
808 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
809 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
810
811 PINMUX_IPSR_GPSR(IP5_11_8, A19),
812 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
813 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
814 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
815 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
816 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
817 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
818
819 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
820 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
821 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
822 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
823 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
824
825 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
826 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
827 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
828 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
829 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
830
831 PINMUX_IPSR_GPSR(IP5_23_20, D0),
832 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
833 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
834 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
835 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
836
837 PINMUX_IPSR_GPSR(IP5_27_24, D1),
838 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
839 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
840 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
841 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
842 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
843 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
844 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
845
846 PINMUX_IPSR_GPSR(IP5_31_28, D2),
847 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
848 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
849 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
850 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
851 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
852 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
853
854
855 PINMUX_IPSR_GPSR(IP6_3_0, D3),
856 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
857 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
858 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
859 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
860 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
861 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
862
863 PINMUX_IPSR_GPSR(IP6_7_4, D4),
864 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
865 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
866 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
867 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
868 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
869 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
870
871 PINMUX_IPSR_GPSR(IP6_11_8, D5),
872 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
873 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
874 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
875 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
876 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
877
878 PINMUX_IPSR_GPSR(IP6_15_12, D6),
879 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
880 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
881 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
882 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
883 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
884
885 PINMUX_IPSR_GPSR(IP6_19_16, D7),
886 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
887 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
888 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
889 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
890 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
891
892 PINMUX_IPSR_GPSR(IP6_23_20, D8),
893 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
894 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
895 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
896 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
897 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
898 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
899 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
900
901 PINMUX_IPSR_GPSR(IP6_27_24, D9),
902 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
903 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
904 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
905 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
906 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
907 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
908
909 PINMUX_IPSR_GPSR(IP6_31_28, D10),
910 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
911 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
912 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
913 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
914 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
915 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
916
917
918 PINMUX_IPSR_GPSR(IP7_3_0, D11),
919 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
920 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
921 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
922 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
923 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
924 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
925
926 PINMUX_IPSR_GPSR(IP7_7_4, D12),
927 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
928 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
929 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
930 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
931 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
932
933 PINMUX_IPSR_GPSR(IP7_11_8, D13),
934 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
935 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
936 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
937 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
938 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
939 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
940
941 PINMUX_IPSR_GPSR(IP7_15_12, D14),
942 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
943 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
944 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
945 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
946 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
947
948 PINMUX_IPSR_GPSR(IP7_19_16, D15),
949 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
950 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
951 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
952 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
953 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
954
955 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
956 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
957 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
958 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
959 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
960 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
961
962 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
963 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
964 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
965 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
966 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
967
968 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
969 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
970 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
971 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
972 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
973 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
974
975
976 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
977 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
978 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
979 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
980
981 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
982 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
983 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
984 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
985
986 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
987 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
988 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
989 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
990 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
991
992 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
993 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
994 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
995 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
996 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
997
998 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
999 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
1000 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
1001 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
1002 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
1003 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
1004
1005 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
1006 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
1009 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
1012 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
1013
1014
1015 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
1016 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
1017
1018 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
1019 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
1020
1021 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
1022 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
1023
1024 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
1025 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
1026
1027 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
1028 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
1029
1030 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
1031 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
1032
1033 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
1034 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
1035
1036 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1037 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1038
1039
1040 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1041 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1042
1043 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1044 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1045
1046 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1047 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1048
1049 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1050 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1051
1052 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1053 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1054
1055 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1056 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1057
1058 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1059 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
1060 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1061 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1062 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1063 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1064 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1065 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1066
1067 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1068 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
1069 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1070 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1071 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1072 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1073 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1074 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1075
1076
1077 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1078 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
1079 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1080 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1081 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1082
1083 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1084 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
1085 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1086 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1087 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1088
1089 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1090 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1091 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1092 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1093 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1094
1095 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1096 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1097 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1098 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1099 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1100
1101 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1102 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
1103 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1104 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1105 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1106 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1107
1108 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
1109 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
1110 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1111 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1112 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1113 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1114
1115 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1116 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1117 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1118 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1119 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1120 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1121 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
1122
1123 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1124 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1125 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1126 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1127
1128
1129 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1130 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1131 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1132 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1133
1134 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
1135 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1136 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1137 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1138 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1139 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1140 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1141
1142 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
1143 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1144 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1145 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1146 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1147 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1148
1149 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
1150 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1151 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1152 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1153 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1154 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1155
1156 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1157 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1158
1159 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1160 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1161 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
1162
1163 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1164 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1165 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
1166
1167 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1168 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1169 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1170
1171
1172 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1173 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1174 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1175 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1176 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1177 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1178
1179 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1180 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1181 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1182 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1183 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1184 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1185
1186 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1187 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1188 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1189
1190 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1191 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1192 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1193 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1194 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1195 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1196
1197 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1198 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1199 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1200 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1201 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1202 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1203
1204 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1205 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
1206 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1207 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1208
1209 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1210
1211 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1212
1213
1214 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1215
1216 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1217 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1218 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1219
1220 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1221 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1222 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1223 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1224
1225 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1226 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1227
1228 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1229 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1230
1231 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1232 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1233 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1234 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1235
1236 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1237 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1238 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1239
1240 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1241 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1242 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1243 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1244 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1245
1246
1247 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1248 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1249 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1250 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1251
1252 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1253 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1254 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1255 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1256
1257 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1258 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1259 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1260 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1261 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1262 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1263
1264 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1265 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1266 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1267 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1268 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1269 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1270 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1271
1272 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1273 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1274 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1275 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1276 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1277 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1278 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1279
1280 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1281
1282 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1283 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1284
1285 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1286 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1287
1288
1289
1290
1291
1292
1293
1294
1295 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1296 PINMUX_STATIC
1297 #undef FM
1298 };
1299
1300
1301
1302
1303 enum {
1304 GP_ASSIGN_LAST(),
1305 NOGP_ALL(),
1306 };
1307
1308 static const struct sh_pfc_pin pinmux_pins[] = {
1309 PINMUX_GPIO_GP_ALL(),
1310 PINMUX_NOGP_ALL(),
1311 };
1312
1313
1314 static const unsigned int audio_clk_a_pins[] = {
1315
1316 RCAR_GP_PIN(6, 8),
1317 };
1318
1319 static const unsigned int audio_clk_a_mux[] = {
1320 AUDIO_CLKA_MARK,
1321 };
1322
1323 static const unsigned int audio_clk_b_a_pins[] = {
1324
1325 RCAR_GP_PIN(5, 7),
1326 };
1327
1328 static const unsigned int audio_clk_b_a_mux[] = {
1329 AUDIO_CLKB_A_MARK,
1330 };
1331
1332 static const unsigned int audio_clk_b_b_pins[] = {
1333
1334 RCAR_GP_PIN(6, 7),
1335 };
1336
1337 static const unsigned int audio_clk_b_b_mux[] = {
1338 AUDIO_CLKB_B_MARK,
1339 };
1340
1341 static const unsigned int audio_clk_b_c_pins[] = {
1342
1343 RCAR_GP_PIN(6, 13),
1344 };
1345
1346 static const unsigned int audio_clk_b_c_mux[] = {
1347 AUDIO_CLKB_C_MARK,
1348 };
1349
1350 static const unsigned int audio_clk_c_a_pins[] = {
1351
1352 RCAR_GP_PIN(5, 16),
1353 };
1354
1355 static const unsigned int audio_clk_c_a_mux[] = {
1356 AUDIO_CLKC_A_MARK,
1357 };
1358
1359 static const unsigned int audio_clk_c_b_pins[] = {
1360
1361 RCAR_GP_PIN(6, 3),
1362 };
1363
1364 static const unsigned int audio_clk_c_b_mux[] = {
1365 AUDIO_CLKC_B_MARK,
1366 };
1367
1368 static const unsigned int audio_clk_c_c_pins[] = {
1369
1370 RCAR_GP_PIN(6, 14),
1371 };
1372
1373 static const unsigned int audio_clk_c_c_mux[] = {
1374 AUDIO_CLKC_C_MARK,
1375 };
1376
1377 static const unsigned int audio_clkout_a_pins[] = {
1378
1379 RCAR_GP_PIN(5, 3),
1380 };
1381
1382 static const unsigned int audio_clkout_a_mux[] = {
1383 AUDIO_CLKOUT_A_MARK,
1384 };
1385
1386 static const unsigned int audio_clkout_b_pins[] = {
1387
1388 RCAR_GP_PIN(5, 13),
1389 };
1390
1391 static const unsigned int audio_clkout_b_mux[] = {
1392 AUDIO_CLKOUT_B_MARK,
1393 };
1394
1395 static const unsigned int audio_clkout1_a_pins[] = {
1396
1397 RCAR_GP_PIN(5, 4),
1398 };
1399
1400 static const unsigned int audio_clkout1_a_mux[] = {
1401 AUDIO_CLKOUT1_A_MARK,
1402 };
1403
1404 static const unsigned int audio_clkout1_b_pins[] = {
1405
1406 RCAR_GP_PIN(5, 5),
1407 };
1408
1409 static const unsigned int audio_clkout1_b_mux[] = {
1410 AUDIO_CLKOUT1_B_MARK,
1411 };
1412
1413 static const unsigned int audio_clkout1_c_pins[] = {
1414
1415 RCAR_GP_PIN(6, 7),
1416 };
1417
1418 static const unsigned int audio_clkout1_c_mux[] = {
1419 AUDIO_CLKOUT1_C_MARK,
1420 };
1421
1422 static const unsigned int audio_clkout2_a_pins[] = {
1423
1424 RCAR_GP_PIN(5, 8),
1425 };
1426
1427 static const unsigned int audio_clkout2_a_mux[] = {
1428 AUDIO_CLKOUT2_A_MARK,
1429 };
1430
1431 static const unsigned int audio_clkout2_b_pins[] = {
1432
1433 RCAR_GP_PIN(6, 4),
1434 };
1435
1436 static const unsigned int audio_clkout2_b_mux[] = {
1437 AUDIO_CLKOUT2_B_MARK,
1438 };
1439
1440 static const unsigned int audio_clkout2_c_pins[] = {
1441
1442 RCAR_GP_PIN(6, 15),
1443 };
1444
1445 static const unsigned int audio_clkout2_c_mux[] = {
1446 AUDIO_CLKOUT2_C_MARK,
1447 };
1448
1449 static const unsigned int audio_clkout3_a_pins[] = {
1450
1451 RCAR_GP_PIN(5, 9),
1452 };
1453
1454 static const unsigned int audio_clkout3_a_mux[] = {
1455 AUDIO_CLKOUT3_A_MARK,
1456 };
1457
1458 static const unsigned int audio_clkout3_b_pins[] = {
1459
1460 RCAR_GP_PIN(5, 6),
1461 };
1462
1463 static const unsigned int audio_clkout3_b_mux[] = {
1464 AUDIO_CLKOUT3_B_MARK,
1465 };
1466
1467 static const unsigned int audio_clkout3_c_pins[] = {
1468
1469 RCAR_GP_PIN(6, 16),
1470 };
1471
1472 static const unsigned int audio_clkout3_c_mux[] = {
1473 AUDIO_CLKOUT3_C_MARK,
1474 };
1475
1476
1477 static const unsigned int avb_link_pins[] = {
1478
1479 RCAR_GP_PIN(2, 23),
1480 };
1481
1482 static const unsigned int avb_link_mux[] = {
1483 AVB_LINK_MARK,
1484 };
1485
1486 static const unsigned int avb_magic_pins[] = {
1487
1488 RCAR_GP_PIN(2, 22),
1489 };
1490
1491 static const unsigned int avb_magic_mux[] = {
1492 AVB_MAGIC_MARK,
1493 };
1494
1495 static const unsigned int avb_phy_int_pins[] = {
1496
1497 RCAR_GP_PIN(2, 21),
1498 };
1499
1500 static const unsigned int avb_phy_int_mux[] = {
1501 AVB_PHY_INT_MARK,
1502 };
1503
1504 static const unsigned int avb_mii_pins[] = {
1505
1506
1507
1508
1509
1510 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1511 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1512 RCAR_GP_PIN(2, 20),
1513 };
1514
1515 static const unsigned int avb_mii_mux[] = {
1516 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1517 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1518 AVB_TXCREFCLK_MARK,
1519 };
1520
1521 static const unsigned int avb_avtp_pps_pins[] = {
1522
1523 RCAR_GP_PIN(1, 2),
1524 };
1525
1526 static const unsigned int avb_avtp_pps_mux[] = {
1527 AVB_AVTP_PPS_MARK,
1528 };
1529
1530 static const unsigned int avb_avtp_match_a_pins[] = {
1531
1532 RCAR_GP_PIN(2, 24),
1533 };
1534
1535 static const unsigned int avb_avtp_match_a_mux[] = {
1536 AVB_AVTP_MATCH_A_MARK,
1537 };
1538
1539 static const unsigned int avb_avtp_capture_a_pins[] = {
1540
1541 RCAR_GP_PIN(2, 25),
1542 };
1543
1544 static const unsigned int avb_avtp_capture_a_mux[] = {
1545 AVB_AVTP_CAPTURE_A_MARK,
1546 };
1547
1548
1549 static const unsigned int can0_data_pins[] = {
1550
1551 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1552 };
1553
1554 static const unsigned int can0_data_mux[] = {
1555 CAN0_TX_MARK, CAN0_RX_MARK,
1556 };
1557
1558 static const unsigned int can1_data_pins[] = {
1559
1560 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1561 };
1562
1563 static const unsigned int can1_data_mux[] = {
1564 CAN1_TX_MARK, CAN1_RX_MARK,
1565 };
1566
1567
1568 static const unsigned int can_clk_pins[] = {
1569
1570 RCAR_GP_PIN(0, 14),
1571 };
1572
1573 static const unsigned int can_clk_mux[] = {
1574 CAN_CLK_MARK,
1575 };
1576
1577
1578 static const unsigned int canfd0_data_pins[] = {
1579
1580 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1581 };
1582
1583 static const unsigned int canfd0_data_mux[] = {
1584 CANFD0_TX_MARK, CANFD0_RX_MARK,
1585 };
1586
1587 static const unsigned int canfd1_data_pins[] = {
1588
1589 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1590 };
1591
1592 static const unsigned int canfd1_data_mux[] = {
1593 CANFD1_TX_MARK, CANFD1_RX_MARK,
1594 };
1595
1596
1597 static const unsigned int drif0_ctrl_a_pins[] = {
1598
1599 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1600 };
1601
1602 static const unsigned int drif0_ctrl_a_mux[] = {
1603 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1604 };
1605
1606 static const unsigned int drif0_data0_a_pins[] = {
1607
1608 RCAR_GP_PIN(5, 17),
1609 };
1610
1611 static const unsigned int drif0_data0_a_mux[] = {
1612 RIF0_D0_A_MARK,
1613 };
1614
1615 static const unsigned int drif0_data1_a_pins[] = {
1616
1617 RCAR_GP_PIN(5, 18),
1618 };
1619
1620 static const unsigned int drif0_data1_a_mux[] = {
1621 RIF0_D1_A_MARK,
1622 };
1623
1624 static const unsigned int drif0_ctrl_b_pins[] = {
1625
1626 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1627 };
1628
1629 static const unsigned int drif0_ctrl_b_mux[] = {
1630 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1631 };
1632
1633 static const unsigned int drif0_data0_b_pins[] = {
1634
1635 RCAR_GP_PIN(3, 13),
1636 };
1637
1638 static const unsigned int drif0_data0_b_mux[] = {
1639 RIF0_D0_B_MARK,
1640 };
1641
1642 static const unsigned int drif0_data1_b_pins[] = {
1643
1644 RCAR_GP_PIN(3, 14),
1645 };
1646
1647 static const unsigned int drif0_data1_b_mux[] = {
1648 RIF0_D1_B_MARK,
1649 };
1650
1651
1652 static const unsigned int drif1_ctrl_pins[] = {
1653
1654 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1655 };
1656
1657 static const unsigned int drif1_ctrl_mux[] = {
1658 RIF1_CLK_MARK, RIF1_SYNC_MARK,
1659 };
1660
1661 static const unsigned int drif1_data0_pins[] = {
1662
1663 RCAR_GP_PIN(5, 2),
1664 };
1665
1666 static const unsigned int drif1_data0_mux[] = {
1667 RIF1_D0_MARK,
1668 };
1669
1670 static const unsigned int drif1_data1_pins[] = {
1671
1672 RCAR_GP_PIN(5, 3),
1673 };
1674
1675 static const unsigned int drif1_data1_mux[] = {
1676 RIF1_D1_MARK,
1677 };
1678
1679
1680 static const unsigned int drif2_ctrl_a_pins[] = {
1681
1682 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1683 };
1684
1685 static const unsigned int drif2_ctrl_a_mux[] = {
1686 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1687 };
1688
1689 static const unsigned int drif2_data0_a_pins[] = {
1690
1691 RCAR_GP_PIN(2, 8),
1692 };
1693
1694 static const unsigned int drif2_data0_a_mux[] = {
1695 RIF2_D0_A_MARK,
1696 };
1697
1698 static const unsigned int drif2_data1_a_pins[] = {
1699
1700 RCAR_GP_PIN(2, 9),
1701 };
1702
1703 static const unsigned int drif2_data1_a_mux[] = {
1704 RIF2_D1_A_MARK,
1705 };
1706
1707 static const unsigned int drif2_ctrl_b_pins[] = {
1708
1709 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1710 };
1711
1712 static const unsigned int drif2_ctrl_b_mux[] = {
1713 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1714 };
1715
1716 static const unsigned int drif2_data0_b_pins[] = {
1717
1718 RCAR_GP_PIN(1, 6),
1719 };
1720
1721 static const unsigned int drif2_data0_b_mux[] = {
1722 RIF2_D0_B_MARK,
1723 };
1724
1725 static const unsigned int drif2_data1_b_pins[] = {
1726
1727 RCAR_GP_PIN(1, 7),
1728 };
1729
1730 static const unsigned int drif2_data1_b_mux[] = {
1731 RIF2_D1_B_MARK,
1732 };
1733
1734
1735 static const unsigned int drif3_ctrl_a_pins[] = {
1736
1737 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1738 };
1739
1740 static const unsigned int drif3_ctrl_a_mux[] = {
1741 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1742 };
1743
1744 static const unsigned int drif3_data0_a_pins[] = {
1745
1746 RCAR_GP_PIN(2, 12),
1747 };
1748
1749 static const unsigned int drif3_data0_a_mux[] = {
1750 RIF3_D0_A_MARK,
1751 };
1752
1753 static const unsigned int drif3_data1_a_pins[] = {
1754
1755 RCAR_GP_PIN(2, 13),
1756 };
1757
1758 static const unsigned int drif3_data1_a_mux[] = {
1759 RIF3_D1_A_MARK,
1760 };
1761
1762 static const unsigned int drif3_ctrl_b_pins[] = {
1763
1764 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1765 };
1766
1767 static const unsigned int drif3_ctrl_b_mux[] = {
1768 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1769 };
1770
1771 static const unsigned int drif3_data0_b_pins[] = {
1772
1773 RCAR_GP_PIN(0, 10),
1774 };
1775
1776 static const unsigned int drif3_data0_b_mux[] = {
1777 RIF3_D0_B_MARK,
1778 };
1779
1780 static const unsigned int drif3_data1_b_pins[] = {
1781
1782 RCAR_GP_PIN(0, 11),
1783 };
1784
1785 static const unsigned int drif3_data1_b_mux[] = {
1786 RIF3_D1_B_MARK,
1787 };
1788
1789
1790 static const unsigned int du_rgb666_pins[] = {
1791
1792 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1793 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1794 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1795 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1796 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1797 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1798 };
1799 static const unsigned int du_rgb666_mux[] = {
1800 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1801 DU_DR3_MARK, DU_DR2_MARK,
1802 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1803 DU_DG3_MARK, DU_DG2_MARK,
1804 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1805 DU_DB3_MARK, DU_DB2_MARK,
1806 };
1807 static const unsigned int du_rgb888_pins[] = {
1808
1809 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1810 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1811 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1812 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1813 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1814 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1815 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1816 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1817 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1818 };
1819 static const unsigned int du_rgb888_mux[] = {
1820 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1821 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1822 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1823 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1824 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1825 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1826 };
1827 static const unsigned int du_clk_in_0_pins[] = {
1828
1829 RCAR_GP_PIN(0, 16),
1830 };
1831 static const unsigned int du_clk_in_0_mux[] = {
1832 DU_DOTCLKIN0_MARK
1833 };
1834 static const unsigned int du_clk_in_1_pins[] = {
1835
1836 RCAR_GP_PIN(1, 1),
1837 };
1838 static const unsigned int du_clk_in_1_mux[] = {
1839 DU_DOTCLKIN1_MARK
1840 };
1841 static const unsigned int du_clk_out_0_pins[] = {
1842
1843 RCAR_GP_PIN(1, 3),
1844 };
1845 static const unsigned int du_clk_out_0_mux[] = {
1846 DU_DOTCLKOUT0_MARK
1847 };
1848 static const unsigned int du_sync_pins[] = {
1849
1850 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1851 };
1852 static const unsigned int du_sync_mux[] = {
1853 DU_VSYNC_MARK, DU_HSYNC_MARK
1854 };
1855 static const unsigned int du_disp_cde_pins[] = {
1856
1857 RCAR_GP_PIN(1, 1),
1858 };
1859 static const unsigned int du_disp_cde_mux[] = {
1860 DU_DISP_CDE_MARK,
1861 };
1862 static const unsigned int du_cde_pins[] = {
1863
1864 RCAR_GP_PIN(1, 0),
1865 };
1866 static const unsigned int du_cde_mux[] = {
1867 DU_CDE_MARK,
1868 };
1869 static const unsigned int du_disp_pins[] = {
1870
1871 RCAR_GP_PIN(1, 2),
1872 };
1873 static const unsigned int du_disp_mux[] = {
1874 DU_DISP_MARK,
1875 };
1876
1877
1878 static const unsigned int hscif0_data_a_pins[] = {
1879
1880 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1881 };
1882
1883 static const unsigned int hscif0_data_a_mux[] = {
1884 HRX0_A_MARK, HTX0_A_MARK,
1885 };
1886
1887 static const unsigned int hscif0_clk_a_pins[] = {
1888
1889 RCAR_GP_PIN(5, 7),
1890 };
1891
1892 static const unsigned int hscif0_clk_a_mux[] = {
1893 HSCK0_A_MARK,
1894 };
1895
1896 static const unsigned int hscif0_ctrl_a_pins[] = {
1897
1898 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1899 };
1900
1901 static const unsigned int hscif0_ctrl_a_mux[] = {
1902 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1903 };
1904
1905 static const unsigned int hscif0_data_b_pins[] = {
1906
1907 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1908 };
1909
1910 static const unsigned int hscif0_data_b_mux[] = {
1911 HRX0_B_MARK, HTX0_B_MARK,
1912 };
1913
1914 static const unsigned int hscif0_clk_b_pins[] = {
1915
1916 RCAR_GP_PIN(6, 13),
1917 };
1918
1919 static const unsigned int hscif0_clk_b_mux[] = {
1920 HSCK0_B_MARK,
1921 };
1922
1923
1924 static const unsigned int hscif1_data_a_pins[] = {
1925
1926 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1927 };
1928
1929 static const unsigned int hscif1_data_a_mux[] = {
1930 HRX1_A_MARK, HTX1_A_MARK,
1931 };
1932
1933 static const unsigned int hscif1_clk_a_pins[] = {
1934
1935 RCAR_GP_PIN(5, 0),
1936 };
1937
1938 static const unsigned int hscif1_clk_a_mux[] = {
1939 HSCK1_A_MARK,
1940 };
1941
1942 static const unsigned int hscif1_data_b_pins[] = {
1943
1944 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1945 };
1946
1947 static const unsigned int hscif1_data_b_mux[] = {
1948 HRX1_B_MARK, HTX1_B_MARK,
1949 };
1950
1951 static const unsigned int hscif1_clk_b_pins[] = {
1952
1953 RCAR_GP_PIN(3, 0),
1954 };
1955
1956 static const unsigned int hscif1_clk_b_mux[] = {
1957 HSCK1_B_MARK,
1958 };
1959
1960 static const unsigned int hscif1_ctrl_b_pins[] = {
1961
1962 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1963 };
1964
1965 static const unsigned int hscif1_ctrl_b_mux[] = {
1966 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1967 };
1968
1969
1970 static const unsigned int hscif2_data_a_pins[] = {
1971
1972 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1973 };
1974
1975 static const unsigned int hscif2_data_a_mux[] = {
1976 HRX2_A_MARK, HTX2_A_MARK,
1977 };
1978
1979 static const unsigned int hscif2_clk_a_pins[] = {
1980
1981 RCAR_GP_PIN(6, 14),
1982 };
1983
1984 static const unsigned int hscif2_clk_a_mux[] = {
1985 HSCK2_A_MARK,
1986 };
1987
1988 static const unsigned int hscif2_ctrl_a_pins[] = {
1989
1990 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1991 };
1992
1993 static const unsigned int hscif2_ctrl_a_mux[] = {
1994 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1995 };
1996
1997 static const unsigned int hscif2_data_b_pins[] = {
1998
1999 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2000 };
2001
2002 static const unsigned int hscif2_data_b_mux[] = {
2003 HRX2_B_MARK, HTX2_B_MARK,
2004 };
2005
2006
2007 static const unsigned int hscif3_data_a_pins[] = {
2008
2009 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2010 };
2011
2012 static const unsigned int hscif3_data_a_mux[] = {
2013 HRX3_A_MARK, HTX3_A_MARK,
2014 };
2015
2016 static const unsigned int hscif3_data_b_pins[] = {
2017
2018 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2019 };
2020
2021 static const unsigned int hscif3_data_b_mux[] = {
2022 HRX3_B_MARK, HTX3_B_MARK,
2023 };
2024
2025 static const unsigned int hscif3_clk_b_pins[] = {
2026
2027 RCAR_GP_PIN(0, 4),
2028 };
2029
2030 static const unsigned int hscif3_clk_b_mux[] = {
2031 HSCK3_B_MARK,
2032 };
2033
2034 static const unsigned int hscif3_data_c_pins[] = {
2035
2036 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2037 };
2038
2039 static const unsigned int hscif3_data_c_mux[] = {
2040 HRX3_C_MARK, HTX3_C_MARK,
2041 };
2042
2043 static const unsigned int hscif3_clk_c_pins[] = {
2044
2045 RCAR_GP_PIN(2, 11),
2046 };
2047
2048 static const unsigned int hscif3_clk_c_mux[] = {
2049 HSCK3_C_MARK,
2050 };
2051
2052 static const unsigned int hscif3_ctrl_c_pins[] = {
2053
2054 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2055 };
2056
2057 static const unsigned int hscif3_ctrl_c_mux[] = {
2058 HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2059 };
2060
2061 static const unsigned int hscif3_data_d_pins[] = {
2062
2063 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2064 };
2065
2066 static const unsigned int hscif3_data_d_mux[] = {
2067 HRX3_D_MARK, HTX3_D_MARK,
2068 };
2069
2070 static const unsigned int hscif3_data_e_pins[] = {
2071
2072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2073 };
2074
2075 static const unsigned int hscif3_data_e_mux[] = {
2076 HRX3_E_MARK, HTX3_E_MARK,
2077 };
2078
2079 static const unsigned int hscif3_ctrl_e_pins[] = {
2080
2081 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2082 };
2083
2084 static const unsigned int hscif3_ctrl_e_mux[] = {
2085 HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2086 };
2087
2088
2089 static const unsigned int hscif4_data_a_pins[] = {
2090
2091 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2092 };
2093
2094 static const unsigned int hscif4_data_a_mux[] = {
2095 HRX4_A_MARK, HTX4_A_MARK,
2096 };
2097
2098 static const unsigned int hscif4_clk_a_pins[] = {
2099
2100 RCAR_GP_PIN(2, 0),
2101 };
2102
2103 static const unsigned int hscif4_clk_a_mux[] = {
2104 HSCK4_A_MARK,
2105 };
2106
2107 static const unsigned int hscif4_ctrl_a_pins[] = {
2108
2109 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2110 };
2111
2112 static const unsigned int hscif4_ctrl_a_mux[] = {
2113 HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2114 };
2115
2116 static const unsigned int hscif4_data_b_pins[] = {
2117
2118 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2119 };
2120
2121 static const unsigned int hscif4_data_b_mux[] = {
2122 HRX4_B_MARK, HTX4_B_MARK,
2123 };
2124
2125 static const unsigned int hscif4_clk_b_pins[] = {
2126
2127 RCAR_GP_PIN(2, 6),
2128 };
2129
2130 static const unsigned int hscif4_clk_b_mux[] = {
2131 HSCK4_B_MARK,
2132 };
2133
2134 static const unsigned int hscif4_data_c_pins[] = {
2135
2136 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2137 };
2138
2139 static const unsigned int hscif4_data_c_mux[] = {
2140 HRX4_C_MARK, HTX4_C_MARK,
2141 };
2142
2143 static const unsigned int hscif4_data_d_pins[] = {
2144
2145 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2146 };
2147
2148 static const unsigned int hscif4_data_d_mux[] = {
2149 HRX4_D_MARK, HTX4_D_MARK,
2150 };
2151
2152 static const unsigned int hscif4_data_e_pins[] = {
2153
2154 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2155 };
2156
2157 static const unsigned int hscif4_data_e_mux[] = {
2158 HRX4_E_MARK, HTX4_E_MARK,
2159 };
2160
2161
2162 static const unsigned int i2c1_a_pins[] = {
2163
2164 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2165 };
2166
2167 static const unsigned int i2c1_a_mux[] = {
2168 SCL1_A_MARK, SDA1_A_MARK,
2169 };
2170
2171 static const unsigned int i2c1_b_pins[] = {
2172
2173 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2174 };
2175
2176 static const unsigned int i2c1_b_mux[] = {
2177 SCL1_B_MARK, SDA1_B_MARK,
2178 };
2179
2180 static const unsigned int i2c1_c_pins[] = {
2181
2182 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2183 };
2184
2185 static const unsigned int i2c1_c_mux[] = {
2186 SCL1_C_MARK, SDA1_C_MARK,
2187 };
2188
2189 static const unsigned int i2c1_d_pins[] = {
2190
2191 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2192 };
2193
2194 static const unsigned int i2c1_d_mux[] = {
2195 SCL1_D_MARK, SDA1_D_MARK,
2196 };
2197
2198 static const unsigned int i2c2_a_pins[] = {
2199
2200 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2201 };
2202
2203 static const unsigned int i2c2_a_mux[] = {
2204 SCL2_A_MARK, SDA2_A_MARK,
2205 };
2206
2207 static const unsigned int i2c2_b_pins[] = {
2208
2209 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2210 };
2211
2212 static const unsigned int i2c2_b_mux[] = {
2213 SCL2_B_MARK, SDA2_B_MARK,
2214 };
2215
2216 static const unsigned int i2c2_c_pins[] = {
2217
2218 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2219 };
2220
2221 static const unsigned int i2c2_c_mux[] = {
2222 SCL2_C_MARK, SDA2_C_MARK,
2223 };
2224
2225 static const unsigned int i2c2_d_pins[] = {
2226
2227 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2228 };
2229
2230 static const unsigned int i2c2_d_mux[] = {
2231 SCL2_D_MARK, SDA2_D_MARK,
2232 };
2233
2234 static const unsigned int i2c2_e_pins[] = {
2235
2236 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2237 };
2238
2239 static const unsigned int i2c2_e_mux[] = {
2240 SCL2_E_MARK, SDA2_E_MARK,
2241 };
2242
2243 static const unsigned int i2c4_pins[] = {
2244
2245 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2246 };
2247
2248 static const unsigned int i2c4_mux[] = {
2249 SCL4_MARK, SDA4_MARK,
2250 };
2251
2252 static const unsigned int i2c5_pins[] = {
2253
2254 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2255 };
2256
2257 static const unsigned int i2c5_mux[] = {
2258 SCL5_MARK, SDA5_MARK,
2259 };
2260
2261 static const unsigned int i2c6_a_pins[] = {
2262
2263 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2264 };
2265
2266 static const unsigned int i2c6_a_mux[] = {
2267 SCL6_A_MARK, SDA6_A_MARK,
2268 };
2269
2270 static const unsigned int i2c6_b_pins[] = {
2271
2272 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2273 };
2274
2275 static const unsigned int i2c6_b_mux[] = {
2276 SCL6_B_MARK, SDA6_B_MARK,
2277 };
2278
2279 static const unsigned int i2c7_a_pins[] = {
2280
2281 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2282 };
2283
2284 static const unsigned int i2c7_a_mux[] = {
2285 SCL7_A_MARK, SDA7_A_MARK,
2286 };
2287
2288 static const unsigned int i2c7_b_pins[] = {
2289
2290 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2291 };
2292
2293 static const unsigned int i2c7_b_mux[] = {
2294 SCL7_B_MARK, SDA7_B_MARK,
2295 };
2296
2297
2298 static const unsigned int intc_ex_irq0_pins[] = {
2299
2300 RCAR_GP_PIN(1, 0),
2301 };
2302 static const unsigned int intc_ex_irq0_mux[] = {
2303 IRQ0_MARK,
2304 };
2305 static const unsigned int intc_ex_irq1_pins[] = {
2306
2307 RCAR_GP_PIN(1, 1),
2308 };
2309 static const unsigned int intc_ex_irq1_mux[] = {
2310 IRQ1_MARK,
2311 };
2312 static const unsigned int intc_ex_irq2_pins[] = {
2313
2314 RCAR_GP_PIN(1, 2),
2315 };
2316 static const unsigned int intc_ex_irq2_mux[] = {
2317 IRQ2_MARK,
2318 };
2319 static const unsigned int intc_ex_irq3_pins[] = {
2320
2321 RCAR_GP_PIN(1, 9),
2322 };
2323 static const unsigned int intc_ex_irq3_mux[] = {
2324 IRQ3_MARK,
2325 };
2326 static const unsigned int intc_ex_irq4_pins[] = {
2327
2328 RCAR_GP_PIN(1, 10),
2329 };
2330 static const unsigned int intc_ex_irq4_mux[] = {
2331 IRQ4_MARK,
2332 };
2333 static const unsigned int intc_ex_irq5_pins[] = {
2334
2335 RCAR_GP_PIN(0, 7),
2336 };
2337 static const unsigned int intc_ex_irq5_mux[] = {
2338 IRQ5_MARK,
2339 };
2340
2341
2342 static const unsigned int msiof0_clk_pins[] = {
2343
2344 RCAR_GP_PIN(5, 10),
2345 };
2346
2347 static const unsigned int msiof0_clk_mux[] = {
2348 MSIOF0_SCK_MARK,
2349 };
2350
2351 static const unsigned int msiof0_sync_pins[] = {
2352
2353 RCAR_GP_PIN(5, 13),
2354 };
2355
2356 static const unsigned int msiof0_sync_mux[] = {
2357 MSIOF0_SYNC_MARK,
2358 };
2359
2360 static const unsigned int msiof0_ss1_pins[] = {
2361
2362 RCAR_GP_PIN(5, 14),
2363 };
2364
2365 static const unsigned int msiof0_ss1_mux[] = {
2366 MSIOF0_SS1_MARK,
2367 };
2368
2369 static const unsigned int msiof0_ss2_pins[] = {
2370
2371 RCAR_GP_PIN(5, 15),
2372 };
2373
2374 static const unsigned int msiof0_ss2_mux[] = {
2375 MSIOF0_SS2_MARK,
2376 };
2377
2378 static const unsigned int msiof0_txd_pins[] = {
2379
2380 RCAR_GP_PIN(5, 12),
2381 };
2382
2383 static const unsigned int msiof0_txd_mux[] = {
2384 MSIOF0_TXD_MARK,
2385 };
2386
2387 static const unsigned int msiof0_rxd_pins[] = {
2388
2389 RCAR_GP_PIN(5, 11),
2390 };
2391
2392 static const unsigned int msiof0_rxd_mux[] = {
2393 MSIOF0_RXD_MARK,
2394 };
2395
2396
2397 static const unsigned int msiof1_clk_pins[] = {
2398
2399 RCAR_GP_PIN(1, 19),
2400 };
2401
2402 static const unsigned int msiof1_clk_mux[] = {
2403 MSIOF1_SCK_MARK,
2404 };
2405
2406 static const unsigned int msiof1_sync_pins[] = {
2407
2408 RCAR_GP_PIN(1, 16),
2409 };
2410
2411 static const unsigned int msiof1_sync_mux[] = {
2412 MSIOF1_SYNC_MARK,
2413 };
2414
2415 static const unsigned int msiof1_ss1_pins[] = {
2416
2417 RCAR_GP_PIN(1, 14),
2418 };
2419
2420 static const unsigned int msiof1_ss1_mux[] = {
2421 MSIOF1_SS1_MARK,
2422 };
2423
2424 static const unsigned int msiof1_ss2_pins[] = {
2425
2426 RCAR_GP_PIN(1, 15),
2427 };
2428
2429 static const unsigned int msiof1_ss2_mux[] = {
2430 MSIOF1_SS2_MARK,
2431 };
2432
2433 static const unsigned int msiof1_txd_pins[] = {
2434
2435 RCAR_GP_PIN(1, 18),
2436 };
2437
2438 static const unsigned int msiof1_txd_mux[] = {
2439 MSIOF1_TXD_MARK,
2440 };
2441
2442 static const unsigned int msiof1_rxd_pins[] = {
2443
2444 RCAR_GP_PIN(1, 17),
2445 };
2446
2447 static const unsigned int msiof1_rxd_mux[] = {
2448 MSIOF1_RXD_MARK,
2449 };
2450
2451
2452 static const unsigned int msiof2_clk_a_pins[] = {
2453
2454 RCAR_GP_PIN(0, 8),
2455 };
2456
2457 static const unsigned int msiof2_clk_a_mux[] = {
2458 MSIOF2_SCK_A_MARK,
2459 };
2460
2461 static const unsigned int msiof2_sync_a_pins[] = {
2462
2463 RCAR_GP_PIN(0, 9),
2464 };
2465
2466 static const unsigned int msiof2_sync_a_mux[] = {
2467 MSIOF2_SYNC_A_MARK,
2468 };
2469
2470 static const unsigned int msiof2_ss1_a_pins[] = {
2471
2472 RCAR_GP_PIN(0, 15),
2473 };
2474
2475 static const unsigned int msiof2_ss1_a_mux[] = {
2476 MSIOF2_SS1_A_MARK,
2477 };
2478
2479 static const unsigned int msiof2_ss2_a_pins[] = {
2480
2481 RCAR_GP_PIN(0, 14),
2482 };
2483
2484 static const unsigned int msiof2_ss2_a_mux[] = {
2485 MSIOF2_SS2_A_MARK,
2486 };
2487
2488 static const unsigned int msiof2_txd_a_pins[] = {
2489
2490 RCAR_GP_PIN(0, 11),
2491 };
2492
2493 static const unsigned int msiof2_txd_a_mux[] = {
2494 MSIOF2_TXD_A_MARK,
2495 };
2496
2497 static const unsigned int msiof2_rxd_a_pins[] = {
2498
2499 RCAR_GP_PIN(0, 10),
2500 };
2501
2502 static const unsigned int msiof2_rxd_a_mux[] = {
2503 MSIOF2_RXD_A_MARK,
2504 };
2505
2506 static const unsigned int msiof2_clk_b_pins[] = {
2507
2508 RCAR_GP_PIN(1, 13),
2509 };
2510
2511 static const unsigned int msiof2_clk_b_mux[] = {
2512 MSIOF2_SCK_B_MARK,
2513 };
2514
2515 static const unsigned int msiof2_sync_b_pins[] = {
2516
2517 RCAR_GP_PIN(1, 10),
2518 };
2519
2520 static const unsigned int msiof2_sync_b_mux[] = {
2521 MSIOF2_SYNC_B_MARK,
2522 };
2523
2524 static const unsigned int msiof2_ss1_b_pins[] = {
2525
2526 RCAR_GP_PIN(1, 16),
2527 };
2528
2529 static const unsigned int msiof2_ss1_b_mux[] = {
2530 MSIOF2_SS1_B_MARK,
2531 };
2532
2533 static const unsigned int msiof2_ss2_b_pins[] = {
2534
2535 RCAR_GP_PIN(1, 12),
2536 };
2537
2538 static const unsigned int msiof2_ss2_b_mux[] = {
2539 MSIOF2_SS2_B_MARK,
2540 };
2541
2542 static const unsigned int msiof2_txd_b_pins[] = {
2543
2544 RCAR_GP_PIN(1, 15),
2545 };
2546
2547 static const unsigned int msiof2_txd_b_mux[] = {
2548 MSIOF2_TXD_B_MARK,
2549 };
2550
2551 static const unsigned int msiof2_rxd_b_pins[] = {
2552
2553 RCAR_GP_PIN(1, 14),
2554 };
2555
2556 static const unsigned int msiof2_rxd_b_mux[] = {
2557 MSIOF2_RXD_B_MARK,
2558 };
2559
2560
2561 static const unsigned int msiof3_clk_a_pins[] = {
2562
2563 RCAR_GP_PIN(0, 0),
2564 };
2565
2566 static const unsigned int msiof3_clk_a_mux[] = {
2567 MSIOF3_SCK_A_MARK,
2568 };
2569
2570 static const unsigned int msiof3_sync_a_pins[] = {
2571
2572 RCAR_GP_PIN(0, 1),
2573 };
2574
2575 static const unsigned int msiof3_sync_a_mux[] = {
2576 MSIOF3_SYNC_A_MARK,
2577 };
2578
2579 static const unsigned int msiof3_ss1_a_pins[] = {
2580
2581 RCAR_GP_PIN(0, 15),
2582 };
2583
2584 static const unsigned int msiof3_ss1_a_mux[] = {
2585 MSIOF3_SS1_A_MARK,
2586 };
2587
2588 static const unsigned int msiof3_ss2_a_pins[] = {
2589
2590 RCAR_GP_PIN(0, 4),
2591 };
2592
2593 static const unsigned int msiof3_ss2_a_mux[] = {
2594 MSIOF3_SS2_A_MARK,
2595 };
2596
2597 static const unsigned int msiof3_txd_a_pins[] = {
2598
2599 RCAR_GP_PIN(0, 3),
2600 };
2601
2602 static const unsigned int msiof3_txd_a_mux[] = {
2603 MSIOF3_TXD_A_MARK,
2604 };
2605
2606 static const unsigned int msiof3_rxd_a_pins[] = {
2607
2608 RCAR_GP_PIN(0, 2),
2609 };
2610
2611 static const unsigned int msiof3_rxd_a_mux[] = {
2612 MSIOF3_RXD_A_MARK,
2613 };
2614
2615 static const unsigned int msiof3_clk_b_pins[] = {
2616
2617 RCAR_GP_PIN(1, 5),
2618 };
2619
2620 static const unsigned int msiof3_clk_b_mux[] = {
2621 MSIOF3_SCK_B_MARK,
2622 };
2623
2624 static const unsigned int msiof3_sync_b_pins[] = {
2625
2626 RCAR_GP_PIN(1, 4),
2627 };
2628
2629 static const unsigned int msiof3_sync_b_mux[] = {
2630 MSIOF3_SYNC_B_MARK,
2631 };
2632
2633 static const unsigned int msiof3_ss1_b_pins[] = {
2634
2635 RCAR_GP_PIN(1, 0),
2636 };
2637
2638 static const unsigned int msiof3_ss1_b_mux[] = {
2639 MSIOF3_SS1_B_MARK,
2640 };
2641
2642 static const unsigned int msiof3_txd_b_pins[] = {
2643
2644 RCAR_GP_PIN(1, 7),
2645 };
2646
2647 static const unsigned int msiof3_txd_b_mux[] = {
2648 MSIOF3_TXD_B_MARK,
2649 };
2650
2651 static const unsigned int msiof3_rxd_b_pins[] = {
2652
2653 RCAR_GP_PIN(1, 6),
2654 };
2655
2656 static const unsigned int msiof3_rxd_b_mux[] = {
2657 MSIOF3_RXD_B_MARK,
2658 };
2659
2660
2661 static const unsigned int pwm0_a_pins[] = {
2662
2663 RCAR_GP_PIN(2, 22),
2664 };
2665
2666 static const unsigned int pwm0_a_mux[] = {
2667 PWM0_A_MARK,
2668 };
2669
2670 static const unsigned int pwm0_b_pins[] = {
2671
2672 RCAR_GP_PIN(6, 3),
2673 };
2674
2675 static const unsigned int pwm0_b_mux[] = {
2676 PWM0_B_MARK,
2677 };
2678
2679
2680 static const unsigned int pwm1_a_pins[] = {
2681
2682 RCAR_GP_PIN(2, 23),
2683 };
2684
2685 static const unsigned int pwm1_a_mux[] = {
2686 PWM1_A_MARK,
2687 };
2688
2689 static const unsigned int pwm1_b_pins[] = {
2690
2691 RCAR_GP_PIN(6, 4),
2692 };
2693
2694 static const unsigned int pwm1_b_mux[] = {
2695 PWM1_B_MARK,
2696 };
2697
2698
2699 static const unsigned int pwm2_a_pins[] = {
2700
2701 RCAR_GP_PIN(1, 0),
2702 };
2703
2704 static const unsigned int pwm2_a_mux[] = {
2705 PWM2_A_MARK,
2706 };
2707
2708 static const unsigned int pwm2_b_pins[] = {
2709
2710 RCAR_GP_PIN(1, 4),
2711 };
2712
2713 static const unsigned int pwm2_b_mux[] = {
2714 PWM2_B_MARK,
2715 };
2716
2717 static const unsigned int pwm2_c_pins[] = {
2718
2719 RCAR_GP_PIN(6, 5),
2720 };
2721
2722 static const unsigned int pwm2_c_mux[] = {
2723 PWM2_C_MARK,
2724 };
2725
2726
2727 static const unsigned int pwm3_a_pins[] = {
2728
2729 RCAR_GP_PIN(1, 1),
2730 };
2731
2732 static const unsigned int pwm3_a_mux[] = {
2733 PWM3_A_MARK,
2734 };
2735
2736 static const unsigned int pwm3_b_pins[] = {
2737
2738 RCAR_GP_PIN(1, 5),
2739 };
2740
2741 static const unsigned int pwm3_b_mux[] = {
2742 PWM3_B_MARK,
2743 };
2744
2745 static const unsigned int pwm3_c_pins[] = {
2746
2747 RCAR_GP_PIN(6, 6),
2748 };
2749
2750 static const unsigned int pwm3_c_mux[] = {
2751 PWM3_C_MARK,
2752 };
2753
2754
2755 static const unsigned int pwm4_a_pins[] = {
2756
2757 RCAR_GP_PIN(1, 3),
2758 };
2759
2760 static const unsigned int pwm4_a_mux[] = {
2761 PWM4_A_MARK,
2762 };
2763
2764 static const unsigned int pwm4_b_pins[] = {
2765
2766 RCAR_GP_PIN(6, 7),
2767 };
2768
2769 static const unsigned int pwm4_b_mux[] = {
2770 PWM4_B_MARK,
2771 };
2772
2773
2774 static const unsigned int pwm5_a_pins[] = {
2775
2776 RCAR_GP_PIN(2, 24),
2777 };
2778
2779 static const unsigned int pwm5_a_mux[] = {
2780 PWM5_A_MARK,
2781 };
2782
2783 static const unsigned int pwm5_b_pins[] = {
2784
2785 RCAR_GP_PIN(6, 10),
2786 };
2787
2788 static const unsigned int pwm5_b_mux[] = {
2789 PWM5_B_MARK,
2790 };
2791
2792
2793 static const unsigned int pwm6_a_pins[] = {
2794
2795 RCAR_GP_PIN(2, 25),
2796 };
2797
2798 static const unsigned int pwm6_a_mux[] = {
2799 PWM6_A_MARK,
2800 };
2801
2802 static const unsigned int pwm6_b_pins[] = {
2803
2804 RCAR_GP_PIN(6, 11),
2805 };
2806
2807 static const unsigned int pwm6_b_mux[] = {
2808 PWM6_B_MARK,
2809 };
2810
2811
2812 static const unsigned int scif0_data_a_pins[] = {
2813
2814 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2815 };
2816
2817 static const unsigned int scif0_data_a_mux[] = {
2818 RX0_A_MARK, TX0_A_MARK,
2819 };
2820
2821 static const unsigned int scif0_clk_a_pins[] = {
2822
2823 RCAR_GP_PIN(5, 0),
2824 };
2825
2826 static const unsigned int scif0_clk_a_mux[] = {
2827 SCK0_A_MARK,
2828 };
2829
2830 static const unsigned int scif0_ctrl_a_pins[] = {
2831
2832 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2833 };
2834
2835 static const unsigned int scif0_ctrl_a_mux[] = {
2836 RTS0_N_A_MARK, CTS0_N_A_MARK,
2837 };
2838
2839 static const unsigned int scif0_data_b_pins[] = {
2840
2841 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2842 };
2843
2844 static const unsigned int scif0_data_b_mux[] = {
2845 RX0_B_MARK, TX0_B_MARK,
2846 };
2847
2848 static const unsigned int scif0_clk_b_pins[] = {
2849
2850 RCAR_GP_PIN(5, 18),
2851 };
2852
2853 static const unsigned int scif0_clk_b_mux[] = {
2854 SCK0_B_MARK,
2855 };
2856
2857
2858 static const unsigned int scif1_data_pins[] = {
2859
2860 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2861 };
2862
2863 static const unsigned int scif1_data_mux[] = {
2864 RX1_MARK, TX1_MARK,
2865 };
2866
2867 static const unsigned int scif1_clk_pins[] = {
2868
2869 RCAR_GP_PIN(5, 16),
2870 };
2871
2872 static const unsigned int scif1_clk_mux[] = {
2873 SCK1_MARK,
2874 };
2875
2876 static const unsigned int scif1_ctrl_pins[] = {
2877
2878 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2879 };
2880
2881 static const unsigned int scif1_ctrl_mux[] = {
2882 RTS1_N_MARK, CTS1_N_MARK,
2883 };
2884
2885
2886 static const unsigned int scif2_data_a_pins[] = {
2887
2888 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2889 };
2890
2891 static const unsigned int scif2_data_a_mux[] = {
2892 RX2_A_MARK, TX2_A_MARK,
2893 };
2894
2895 static const unsigned int scif2_clk_a_pins[] = {
2896
2897 RCAR_GP_PIN(5, 7),
2898 };
2899
2900 static const unsigned int scif2_clk_a_mux[] = {
2901 SCK2_A_MARK,
2902 };
2903
2904 static const unsigned int scif2_data_b_pins[] = {
2905
2906 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2907 };
2908
2909 static const unsigned int scif2_data_b_mux[] = {
2910 RX2_B_MARK, TX2_B_MARK,
2911 };
2912
2913
2914 static const unsigned int scif3_data_a_pins[] = {
2915
2916 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2917 };
2918
2919 static const unsigned int scif3_data_a_mux[] = {
2920 RX3_A_MARK, TX3_A_MARK,
2921 };
2922
2923 static const unsigned int scif3_clk_a_pins[] = {
2924
2925 RCAR_GP_PIN(0, 1),
2926 };
2927
2928 static const unsigned int scif3_clk_a_mux[] = {
2929 SCK3_A_MARK,
2930 };
2931
2932 static const unsigned int scif3_ctrl_a_pins[] = {
2933
2934 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
2935 };
2936
2937 static const unsigned int scif3_ctrl_a_mux[] = {
2938 RTS3_N_A_MARK, CTS3_N_A_MARK,
2939 };
2940
2941 static const unsigned int scif3_data_b_pins[] = {
2942
2943 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2944 };
2945
2946 static const unsigned int scif3_data_b_mux[] = {
2947 RX3_B_MARK, TX3_B_MARK,
2948 };
2949
2950 static const unsigned int scif3_data_c_pins[] = {
2951
2952 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2953 };
2954
2955 static const unsigned int scif3_data_c_mux[] = {
2956 RX3_C_MARK, TX3_C_MARK,
2957 };
2958
2959 static const unsigned int scif3_clk_c_pins[] = {
2960
2961 RCAR_GP_PIN(2, 24),
2962 };
2963
2964 static const unsigned int scif3_clk_c_mux[] = {
2965 SCK3_C_MARK,
2966 };
2967
2968
2969 static const unsigned int scif4_data_a_pins[] = {
2970
2971 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2972 };
2973
2974 static const unsigned int scif4_data_a_mux[] = {
2975 RX4_A_MARK, TX4_A_MARK,
2976 };
2977
2978 static const unsigned int scif4_clk_a_pins[] = {
2979
2980 RCAR_GP_PIN(1, 5),
2981 };
2982
2983 static const unsigned int scif4_clk_a_mux[] = {
2984 SCK4_A_MARK,
2985 };
2986
2987 static const unsigned int scif4_ctrl_a_pins[] = {
2988
2989 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
2990 };
2991
2992 static const unsigned int scif4_ctrl_a_mux[] = {
2993 RTS4_N_A_MARK, CTS4_N_A_MARK,
2994 };
2995
2996 static const unsigned int scif4_data_b_pins[] = {
2997
2998 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
2999 };
3000
3001 static const unsigned int scif4_data_b_mux[] = {
3002 RX4_B_MARK, TX4_B_MARK,
3003 };
3004
3005 static const unsigned int scif4_clk_b_pins[] = {
3006
3007 RCAR_GP_PIN(0, 8),
3008 };
3009
3010 static const unsigned int scif4_clk_b_mux[] = {
3011 SCK4_B_MARK,
3012 };
3013
3014 static const unsigned int scif4_data_c_pins[] = {
3015
3016 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3017 };
3018
3019 static const unsigned int scif4_data_c_mux[] = {
3020 RX4_C_MARK, TX4_C_MARK,
3021 };
3022
3023 static const unsigned int scif4_ctrl_c_pins[] = {
3024
3025 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3026 };
3027
3028 static const unsigned int scif4_ctrl_c_mux[] = {
3029 RTS4_N_C_MARK, CTS4_N_C_MARK,
3030 };
3031
3032
3033 static const unsigned int scif5_data_a_pins[] = {
3034
3035 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3036 };
3037
3038 static const unsigned int scif5_data_a_mux[] = {
3039 RX5_A_MARK, TX5_A_MARK,
3040 };
3041
3042 static const unsigned int scif5_clk_a_pins[] = {
3043
3044 RCAR_GP_PIN(1, 13),
3045 };
3046
3047 static const unsigned int scif5_clk_a_mux[] = {
3048 SCK5_A_MARK,
3049 };
3050
3051 static const unsigned int scif5_data_b_pins[] = {
3052
3053 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3054 };
3055
3056 static const unsigned int scif5_data_b_mux[] = {
3057 RX5_B_MARK, TX5_B_MARK,
3058 };
3059
3060 static const unsigned int scif5_data_c_pins[] = {
3061
3062 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3063 };
3064
3065 static const unsigned int scif5_data_c_mux[] = {
3066 RX5_C_MARK, TX5_C_MARK,
3067 };
3068
3069
3070 static const unsigned int scif_clk_a_pins[] = {
3071
3072 RCAR_GP_PIN(5, 3),
3073 };
3074
3075 static const unsigned int scif_clk_a_mux[] = {
3076 SCIF_CLK_A_MARK,
3077 };
3078
3079 static const unsigned int scif_clk_b_pins[] = {
3080
3081 RCAR_GP_PIN(5, 7),
3082 };
3083
3084 static const unsigned int scif_clk_b_mux[] = {
3085 SCIF_CLK_B_MARK,
3086 };
3087
3088
3089 static const unsigned int sdhi0_data1_pins[] = {
3090
3091 RCAR_GP_PIN(3, 2),
3092 };
3093
3094 static const unsigned int sdhi0_data1_mux[] = {
3095 SD0_DAT0_MARK,
3096 };
3097
3098 static const unsigned int sdhi0_data4_pins[] = {
3099
3100 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3101 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3102 };
3103
3104 static const unsigned int sdhi0_data4_mux[] = {
3105 SD0_DAT0_MARK, SD0_DAT1_MARK,
3106 SD0_DAT2_MARK, SD0_DAT3_MARK,
3107 };
3108
3109 static const unsigned int sdhi0_ctrl_pins[] = {
3110
3111 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3112 };
3113
3114 static const unsigned int sdhi0_ctrl_mux[] = {
3115 SD0_CLK_MARK, SD0_CMD_MARK,
3116 };
3117
3118 static const unsigned int sdhi0_cd_pins[] = {
3119
3120 RCAR_GP_PIN(3, 12),
3121 };
3122
3123 static const unsigned int sdhi0_cd_mux[] = {
3124 SD0_CD_MARK,
3125 };
3126
3127 static const unsigned int sdhi0_wp_pins[] = {
3128
3129 RCAR_GP_PIN(3, 13),
3130 };
3131
3132 static const unsigned int sdhi0_wp_mux[] = {
3133 SD0_WP_MARK,
3134 };
3135
3136
3137 static const unsigned int sdhi1_data1_pins[] = {
3138
3139 RCAR_GP_PIN(3, 8),
3140 };
3141
3142 static const unsigned int sdhi1_data1_mux[] = {
3143 SD1_DAT0_MARK,
3144 };
3145
3146 static const unsigned int sdhi1_data4_pins[] = {
3147
3148 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3149 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3150 };
3151
3152 static const unsigned int sdhi1_data4_mux[] = {
3153 SD1_DAT0_MARK, SD1_DAT1_MARK,
3154 SD1_DAT2_MARK, SD1_DAT3_MARK,
3155 };
3156
3157 static const unsigned int sdhi1_ctrl_pins[] = {
3158
3159 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3160 };
3161
3162 static const unsigned int sdhi1_ctrl_mux[] = {
3163 SD1_CLK_MARK, SD1_CMD_MARK,
3164 };
3165
3166 static const unsigned int sdhi1_cd_pins[] = {
3167
3168 RCAR_GP_PIN(3, 14),
3169 };
3170
3171 static const unsigned int sdhi1_cd_mux[] = {
3172 SD1_CD_MARK,
3173 };
3174
3175 static const unsigned int sdhi1_wp_pins[] = {
3176
3177 RCAR_GP_PIN(3, 15),
3178 };
3179
3180 static const unsigned int sdhi1_wp_mux[] = {
3181 SD1_WP_MARK,
3182 };
3183
3184
3185 static const unsigned int sdhi3_data1_pins[] = {
3186
3187 RCAR_GP_PIN(4, 2),
3188 };
3189
3190 static const unsigned int sdhi3_data1_mux[] = {
3191 SD3_DAT0_MARK,
3192 };
3193
3194 static const unsigned int sdhi3_data4_pins[] = {
3195
3196 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3197 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3198 };
3199
3200 static const unsigned int sdhi3_data4_mux[] = {
3201 SD3_DAT0_MARK, SD3_DAT1_MARK,
3202 SD3_DAT2_MARK, SD3_DAT3_MARK,
3203 };
3204
3205 static const unsigned int sdhi3_data8_pins[] = {
3206
3207 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3208 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3209 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3210 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3211 };
3212
3213 static const unsigned int sdhi3_data8_mux[] = {
3214 SD3_DAT0_MARK, SD3_DAT1_MARK,
3215 SD3_DAT2_MARK, SD3_DAT3_MARK,
3216 SD3_DAT4_MARK, SD3_DAT5_MARK,
3217 SD3_DAT6_MARK, SD3_DAT7_MARK,
3218 };
3219
3220 static const unsigned int sdhi3_ctrl_pins[] = {
3221
3222 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3223 };
3224
3225 static const unsigned int sdhi3_ctrl_mux[] = {
3226 SD3_CLK_MARK, SD3_CMD_MARK,
3227 };
3228
3229 static const unsigned int sdhi3_cd_pins[] = {
3230
3231 RCAR_GP_PIN(3, 12),
3232 };
3233
3234 static const unsigned int sdhi3_cd_mux[] = {
3235 SD3_CD_MARK,
3236 };
3237
3238 static const unsigned int sdhi3_wp_pins[] = {
3239
3240 RCAR_GP_PIN(3, 13),
3241 };
3242
3243 static const unsigned int sdhi3_wp_mux[] = {
3244 SD3_WP_MARK,
3245 };
3246
3247 static const unsigned int sdhi3_ds_pins[] = {
3248
3249 RCAR_GP_PIN(4, 10),
3250 };
3251
3252 static const unsigned int sdhi3_ds_mux[] = {
3253 SD3_DS_MARK,
3254 };
3255
3256
3257 static const unsigned int ssi0_data_pins[] = {
3258
3259 RCAR_GP_PIN(6, 2),
3260 };
3261
3262 static const unsigned int ssi0_data_mux[] = {
3263 SSI_SDATA0_MARK,
3264 };
3265
3266 static const unsigned int ssi01239_ctrl_pins[] = {
3267
3268 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3269 };
3270
3271 static const unsigned int ssi01239_ctrl_mux[] = {
3272 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3273 };
3274
3275 static const unsigned int ssi1_data_pins[] = {
3276
3277 RCAR_GP_PIN(6, 3),
3278 };
3279
3280 static const unsigned int ssi1_data_mux[] = {
3281 SSI_SDATA1_MARK,
3282 };
3283
3284 static const unsigned int ssi1_ctrl_pins[] = {
3285
3286 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3287 };
3288
3289 static const unsigned int ssi1_ctrl_mux[] = {
3290 SSI_SCK1_MARK, SSI_WS1_MARK,
3291 };
3292
3293 static const unsigned int ssi2_data_pins[] = {
3294
3295 RCAR_GP_PIN(6, 4),
3296 };
3297
3298 static const unsigned int ssi2_data_mux[] = {
3299 SSI_SDATA2_MARK,
3300 };
3301
3302 static const unsigned int ssi2_ctrl_a_pins[] = {
3303
3304 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3305 };
3306
3307 static const unsigned int ssi2_ctrl_a_mux[] = {
3308 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3309 };
3310
3311 static const unsigned int ssi2_ctrl_b_pins[] = {
3312
3313 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3314 };
3315
3316 static const unsigned int ssi2_ctrl_b_mux[] = {
3317 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3318 };
3319
3320 static const unsigned int ssi3_data_pins[] = {
3321
3322 RCAR_GP_PIN(6, 7),
3323 };
3324
3325 static const unsigned int ssi3_data_mux[] = {
3326 SSI_SDATA3_MARK,
3327 };
3328
3329 static const unsigned int ssi349_ctrl_pins[] = {
3330
3331 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3332 };
3333
3334 static const unsigned int ssi349_ctrl_mux[] = {
3335 SSI_SCK349_MARK, SSI_WS349_MARK,
3336 };
3337
3338 static const unsigned int ssi4_data_pins[] = {
3339
3340 RCAR_GP_PIN(6, 10),
3341 };
3342
3343 static const unsigned int ssi4_data_mux[] = {
3344 SSI_SDATA4_MARK,
3345 };
3346
3347 static const unsigned int ssi4_ctrl_pins[] = {
3348
3349 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3350 };
3351
3352 static const unsigned int ssi4_ctrl_mux[] = {
3353 SSI_SCK4_MARK, SSI_WS4_MARK,
3354 };
3355
3356 static const unsigned int ssi5_data_pins[] = {
3357
3358 RCAR_GP_PIN(6, 13),
3359 };
3360
3361 static const unsigned int ssi5_data_mux[] = {
3362 SSI_SDATA5_MARK,
3363 };
3364
3365 static const unsigned int ssi5_ctrl_pins[] = {
3366
3367 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3368 };
3369
3370 static const unsigned int ssi5_ctrl_mux[] = {
3371 SSI_SCK5_MARK, SSI_WS5_MARK,
3372 };
3373
3374 static const unsigned int ssi6_data_pins[] = {
3375
3376 RCAR_GP_PIN(6, 16),
3377 };
3378
3379 static const unsigned int ssi6_data_mux[] = {
3380 SSI_SDATA6_MARK,
3381 };
3382
3383 static const unsigned int ssi6_ctrl_pins[] = {
3384
3385 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3386 };
3387
3388 static const unsigned int ssi6_ctrl_mux[] = {
3389 SSI_SCK6_MARK, SSI_WS6_MARK,
3390 };
3391
3392 static const unsigned int ssi7_data_pins[] = {
3393
3394 RCAR_GP_PIN(5, 12),
3395 };
3396
3397 static const unsigned int ssi7_data_mux[] = {
3398 SSI_SDATA7_MARK,
3399 };
3400
3401 static const unsigned int ssi78_ctrl_pins[] = {
3402
3403 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3404 };
3405
3406 static const unsigned int ssi78_ctrl_mux[] = {
3407 SSI_SCK78_MARK, SSI_WS78_MARK,
3408 };
3409
3410 static const unsigned int ssi8_data_pins[] = {
3411
3412 RCAR_GP_PIN(5, 13),
3413 };
3414
3415 static const unsigned int ssi8_data_mux[] = {
3416 SSI_SDATA8_MARK,
3417 };
3418
3419 static const unsigned int ssi9_data_pins[] = {
3420
3421 RCAR_GP_PIN(5, 16),
3422 };
3423
3424 static const unsigned int ssi9_data_mux[] = {
3425 SSI_SDATA9_MARK,
3426 };
3427
3428 static const unsigned int ssi9_ctrl_a_pins[] = {
3429
3430 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3431 };
3432
3433 static const unsigned int ssi9_ctrl_a_mux[] = {
3434 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3435 };
3436
3437 static const unsigned int ssi9_ctrl_b_pins[] = {
3438
3439 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3440 };
3441
3442 static const unsigned int ssi9_ctrl_b_mux[] = {
3443 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3444 };
3445
3446
3447 static const unsigned int tmu_tclk1_a_pins[] = {
3448
3449 RCAR_GP_PIN(3, 12),
3450 };
3451
3452 static const unsigned int tmu_tclk1_a_mux[] = {
3453 TCLK1_A_MARK,
3454 };
3455
3456 static const unsigned int tmu_tclk1_b_pins[] = {
3457
3458 RCAR_GP_PIN(5, 17),
3459 };
3460
3461 static const unsigned int tmu_tclk1_b_mux[] = {
3462 TCLK1_B_MARK,
3463 };
3464
3465 static const unsigned int tmu_tclk2_a_pins[] = {
3466
3467 RCAR_GP_PIN(3, 13),
3468 };
3469
3470 static const unsigned int tmu_tclk2_a_mux[] = {
3471 TCLK2_A_MARK,
3472 };
3473
3474 static const unsigned int tmu_tclk2_b_pins[] = {
3475
3476 RCAR_GP_PIN(5, 18),
3477 };
3478
3479 static const unsigned int tmu_tclk2_b_mux[] = {
3480 TCLK2_B_MARK,
3481 };
3482
3483
3484 static const unsigned int usb0_a_pins[] = {
3485
3486 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3487 };
3488
3489 static const unsigned int usb0_a_mux[] = {
3490 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3491 };
3492
3493 static const unsigned int usb0_b_pins[] = {
3494
3495 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3496 };
3497
3498 static const unsigned int usb0_b_mux[] = {
3499 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3500 };
3501
3502 static const unsigned int usb0_id_pins[] = {
3503
3504 RCAR_GP_PIN(5, 0)
3505 };
3506
3507 static const unsigned int usb0_id_mux[] = {
3508 USB0_ID_MARK,
3509 };
3510
3511
3512 static const unsigned int usb30_pins[] = {
3513
3514 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3515 };
3516
3517 static const unsigned int usb30_mux[] = {
3518 USB30_PWEN_MARK, USB30_OVC_MARK,
3519 };
3520
3521 static const unsigned int usb30_id_pins[] = {
3522
3523 RCAR_GP_PIN(5, 0),
3524 };
3525
3526 static const unsigned int usb30_id_mux[] = {
3527 USB3HS0_ID_MARK,
3528 };
3529
3530
3531 static const unsigned int vin4_data18_a_pins[] = {
3532 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3533 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3534 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3535 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3536 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3537 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3538 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3539 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3540 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3541 };
3542
3543 static const unsigned int vin4_data18_a_mux[] = {
3544 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3545 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3546 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3547 VI4_DATA10_MARK, VI4_DATA11_MARK,
3548 VI4_DATA12_MARK, VI4_DATA13_MARK,
3549 VI4_DATA14_MARK, VI4_DATA15_MARK,
3550 VI4_DATA18_MARK, VI4_DATA19_MARK,
3551 VI4_DATA20_MARK, VI4_DATA21_MARK,
3552 VI4_DATA22_MARK, VI4_DATA23_MARK,
3553 };
3554
3555 static const union vin_data vin4_data_a_pins = {
3556 .data24 = {
3557 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3558 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3559 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3560 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3561 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3562 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3563 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3564 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3565 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3566 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3567 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3568 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3569 },
3570 };
3571
3572 static const union vin_data vin4_data_a_mux = {
3573 .data24 = {
3574 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3575 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3576 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3577 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3578 VI4_DATA8_MARK, VI4_DATA9_MARK,
3579 VI4_DATA10_MARK, VI4_DATA11_MARK,
3580 VI4_DATA12_MARK, VI4_DATA13_MARK,
3581 VI4_DATA14_MARK, VI4_DATA15_MARK,
3582 VI4_DATA16_MARK, VI4_DATA17_MARK,
3583 VI4_DATA18_MARK, VI4_DATA19_MARK,
3584 VI4_DATA20_MARK, VI4_DATA21_MARK,
3585 VI4_DATA22_MARK, VI4_DATA23_MARK,
3586 },
3587 };
3588
3589 static const unsigned int vin4_data18_b_pins[] = {
3590 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3591 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3592 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3593 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3594 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3595 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3596 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3597 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3598 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3599 };
3600
3601 static const unsigned int vin4_data18_b_mux[] = {
3602 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3603 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3604 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3605 VI4_DATA10_MARK, VI4_DATA11_MARK,
3606 VI4_DATA12_MARK, VI4_DATA13_MARK,
3607 VI4_DATA14_MARK, VI4_DATA15_MARK,
3608 VI4_DATA18_MARK, VI4_DATA19_MARK,
3609 VI4_DATA20_MARK, VI4_DATA21_MARK,
3610 VI4_DATA22_MARK, VI4_DATA23_MARK,
3611 };
3612
3613 static const union vin_data vin4_data_b_pins = {
3614 .data24 = {
3615 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3616 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3617 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3618 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3619 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3620 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3621 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3622 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3623 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3624 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3625 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3626 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3627 },
3628 };
3629
3630 static const union vin_data vin4_data_b_mux = {
3631 .data24 = {
3632 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3633 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3634 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3635 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3636 VI4_DATA8_MARK, VI4_DATA9_MARK,
3637 VI4_DATA10_MARK, VI4_DATA11_MARK,
3638 VI4_DATA12_MARK, VI4_DATA13_MARK,
3639 VI4_DATA14_MARK, VI4_DATA15_MARK,
3640 VI4_DATA16_MARK, VI4_DATA17_MARK,
3641 VI4_DATA18_MARK, VI4_DATA19_MARK,
3642 VI4_DATA20_MARK, VI4_DATA21_MARK,
3643 VI4_DATA22_MARK, VI4_DATA23_MARK,
3644 },
3645 };
3646
3647 static const unsigned int vin4_sync_pins[] = {
3648
3649 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3650 };
3651
3652 static const unsigned int vin4_sync_mux[] = {
3653 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3654 };
3655
3656 static const unsigned int vin4_field_pins[] = {
3657 RCAR_GP_PIN(2, 23),
3658 };
3659
3660 static const unsigned int vin4_field_mux[] = {
3661 VI4_FIELD_MARK,
3662 };
3663
3664 static const unsigned int vin4_clkenb_pins[] = {
3665 RCAR_GP_PIN(1, 2),
3666 };
3667
3668 static const unsigned int vin4_clkenb_mux[] = {
3669 VI4_CLKENB_MARK,
3670 };
3671
3672 static const unsigned int vin4_clk_pins[] = {
3673 RCAR_GP_PIN(2, 22),
3674 };
3675
3676 static const unsigned int vin4_clk_mux[] = {
3677 VI4_CLK_MARK,
3678 };
3679
3680
3681 static const union vin_data16 vin5_data_a_pins = {
3682 .data16 = {
3683 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3684 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3685 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3686 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3687 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3688 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3689 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3690 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3691 },
3692 };
3693
3694 static const union vin_data16 vin5_data_a_mux = {
3695 .data16 = {
3696 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3697 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3698 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3699 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3700 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3701 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3702 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3703 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3704 },
3705 };
3706
3707 static const unsigned int vin5_data8_b_pins[] = {
3708 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3709 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
3710 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3711 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3712 };
3713
3714 static const unsigned int vin5_data8_b_mux[] = {
3715 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
3716 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
3717 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
3718 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
3719 };
3720
3721 static const unsigned int vin5_sync_a_pins[] = {
3722
3723 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3724 };
3725
3726 static const unsigned int vin5_sync_a_mux[] = {
3727 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3728 };
3729
3730 static const unsigned int vin5_field_a_pins[] = {
3731 RCAR_GP_PIN(1, 10),
3732 };
3733
3734 static const unsigned int vin5_field_a_mux[] = {
3735 VI5_FIELD_A_MARK,
3736 };
3737
3738 static const unsigned int vin5_clkenb_a_pins[] = {
3739 RCAR_GP_PIN(0, 1),
3740 };
3741
3742 static const unsigned int vin5_clkenb_a_mux[] = {
3743 VI5_CLKENB_A_MARK,
3744 };
3745
3746 static const unsigned int vin5_clk_a_pins[] = {
3747 RCAR_GP_PIN(1, 0),
3748 };
3749
3750 static const unsigned int vin5_clk_a_mux[] = {
3751 VI5_CLK_A_MARK,
3752 };
3753
3754 static const unsigned int vin5_clk_b_pins[] = {
3755 RCAR_GP_PIN(2, 22),
3756 };
3757
3758 static const unsigned int vin5_clk_b_mux[] = {
3759 VI5_CLK_B_MARK,
3760 };
3761
3762 static const struct {
3763 struct sh_pfc_pin_group common[247];
3764 struct sh_pfc_pin_group automotive[21];
3765 } pinmux_groups = {
3766 .common = {
3767 SH_PFC_PIN_GROUP(audio_clk_a),
3768 SH_PFC_PIN_GROUP(audio_clk_b_a),
3769 SH_PFC_PIN_GROUP(audio_clk_b_b),
3770 SH_PFC_PIN_GROUP(audio_clk_b_c),
3771 SH_PFC_PIN_GROUP(audio_clk_c_a),
3772 SH_PFC_PIN_GROUP(audio_clk_c_b),
3773 SH_PFC_PIN_GROUP(audio_clk_c_c),
3774 SH_PFC_PIN_GROUP(audio_clkout_a),
3775 SH_PFC_PIN_GROUP(audio_clkout_b),
3776 SH_PFC_PIN_GROUP(audio_clkout1_a),
3777 SH_PFC_PIN_GROUP(audio_clkout1_b),
3778 SH_PFC_PIN_GROUP(audio_clkout1_c),
3779 SH_PFC_PIN_GROUP(audio_clkout2_a),
3780 SH_PFC_PIN_GROUP(audio_clkout2_b),
3781 SH_PFC_PIN_GROUP(audio_clkout2_c),
3782 SH_PFC_PIN_GROUP(audio_clkout3_a),
3783 SH_PFC_PIN_GROUP(audio_clkout3_b),
3784 SH_PFC_PIN_GROUP(audio_clkout3_c),
3785 SH_PFC_PIN_GROUP(avb_link),
3786 SH_PFC_PIN_GROUP(avb_magic),
3787 SH_PFC_PIN_GROUP(avb_phy_int),
3788 SH_PFC_PIN_GROUP(avb_mii),
3789 SH_PFC_PIN_GROUP(avb_avtp_pps),
3790 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3791 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3792 SH_PFC_PIN_GROUP(can0_data),
3793 SH_PFC_PIN_GROUP(can1_data),
3794 SH_PFC_PIN_GROUP(can_clk),
3795 SH_PFC_PIN_GROUP(canfd0_data),
3796 SH_PFC_PIN_GROUP(canfd1_data),
3797 SH_PFC_PIN_GROUP(du_rgb666),
3798 SH_PFC_PIN_GROUP(du_rgb888),
3799 SH_PFC_PIN_GROUP(du_clk_in_0),
3800 SH_PFC_PIN_GROUP(du_clk_in_1),
3801 SH_PFC_PIN_GROUP(du_clk_out_0),
3802 SH_PFC_PIN_GROUP(du_sync),
3803 SH_PFC_PIN_GROUP(du_disp_cde),
3804 SH_PFC_PIN_GROUP(du_cde),
3805 SH_PFC_PIN_GROUP(du_disp),
3806 SH_PFC_PIN_GROUP(hscif0_data_a),
3807 SH_PFC_PIN_GROUP(hscif0_clk_a),
3808 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3809 SH_PFC_PIN_GROUP(hscif0_data_b),
3810 SH_PFC_PIN_GROUP(hscif0_clk_b),
3811 SH_PFC_PIN_GROUP(hscif1_data_a),
3812 SH_PFC_PIN_GROUP(hscif1_clk_a),
3813 SH_PFC_PIN_GROUP(hscif1_data_b),
3814 SH_PFC_PIN_GROUP(hscif1_clk_b),
3815 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3816 SH_PFC_PIN_GROUP(hscif2_data_a),
3817 SH_PFC_PIN_GROUP(hscif2_clk_a),
3818 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3819 SH_PFC_PIN_GROUP(hscif2_data_b),
3820 SH_PFC_PIN_GROUP(hscif3_data_a),
3821 SH_PFC_PIN_GROUP(hscif3_data_b),
3822 SH_PFC_PIN_GROUP(hscif3_clk_b),
3823 SH_PFC_PIN_GROUP(hscif3_data_c),
3824 SH_PFC_PIN_GROUP(hscif3_clk_c),
3825 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3826 SH_PFC_PIN_GROUP(hscif3_data_d),
3827 SH_PFC_PIN_GROUP(hscif3_data_e),
3828 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3829 SH_PFC_PIN_GROUP(hscif4_data_a),
3830 SH_PFC_PIN_GROUP(hscif4_clk_a),
3831 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3832 SH_PFC_PIN_GROUP(hscif4_data_b),
3833 SH_PFC_PIN_GROUP(hscif4_clk_b),
3834 SH_PFC_PIN_GROUP(hscif4_data_c),
3835 SH_PFC_PIN_GROUP(hscif4_data_d),
3836 SH_PFC_PIN_GROUP(hscif4_data_e),
3837 SH_PFC_PIN_GROUP(i2c1_a),
3838 SH_PFC_PIN_GROUP(i2c1_b),
3839 SH_PFC_PIN_GROUP(i2c1_c),
3840 SH_PFC_PIN_GROUP(i2c1_d),
3841 SH_PFC_PIN_GROUP(i2c2_a),
3842 SH_PFC_PIN_GROUP(i2c2_b),
3843 SH_PFC_PIN_GROUP(i2c2_c),
3844 SH_PFC_PIN_GROUP(i2c2_d),
3845 SH_PFC_PIN_GROUP(i2c2_e),
3846 SH_PFC_PIN_GROUP(i2c4),
3847 SH_PFC_PIN_GROUP(i2c5),
3848 SH_PFC_PIN_GROUP(i2c6_a),
3849 SH_PFC_PIN_GROUP(i2c6_b),
3850 SH_PFC_PIN_GROUP(i2c7_a),
3851 SH_PFC_PIN_GROUP(i2c7_b),
3852 SH_PFC_PIN_GROUP(intc_ex_irq0),
3853 SH_PFC_PIN_GROUP(intc_ex_irq1),
3854 SH_PFC_PIN_GROUP(intc_ex_irq2),
3855 SH_PFC_PIN_GROUP(intc_ex_irq3),
3856 SH_PFC_PIN_GROUP(intc_ex_irq4),
3857 SH_PFC_PIN_GROUP(intc_ex_irq5),
3858 SH_PFC_PIN_GROUP(msiof0_clk),
3859 SH_PFC_PIN_GROUP(msiof0_sync),
3860 SH_PFC_PIN_GROUP(msiof0_ss1),
3861 SH_PFC_PIN_GROUP(msiof0_ss2),
3862 SH_PFC_PIN_GROUP(msiof0_txd),
3863 SH_PFC_PIN_GROUP(msiof0_rxd),
3864 SH_PFC_PIN_GROUP(msiof1_clk),
3865 SH_PFC_PIN_GROUP(msiof1_sync),
3866 SH_PFC_PIN_GROUP(msiof1_ss1),
3867 SH_PFC_PIN_GROUP(msiof1_ss2),
3868 SH_PFC_PIN_GROUP(msiof1_txd),
3869 SH_PFC_PIN_GROUP(msiof1_rxd),
3870 SH_PFC_PIN_GROUP(msiof2_clk_a),
3871 SH_PFC_PIN_GROUP(msiof2_sync_a),
3872 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3873 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3874 SH_PFC_PIN_GROUP(msiof2_txd_a),
3875 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3876 SH_PFC_PIN_GROUP(msiof2_clk_b),
3877 SH_PFC_PIN_GROUP(msiof2_sync_b),
3878 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3879 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3880 SH_PFC_PIN_GROUP(msiof2_txd_b),
3881 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3882 SH_PFC_PIN_GROUP(msiof3_clk_a),
3883 SH_PFC_PIN_GROUP(msiof3_sync_a),
3884 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3885 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3886 SH_PFC_PIN_GROUP(msiof3_txd_a),
3887 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3888 SH_PFC_PIN_GROUP(msiof3_clk_b),
3889 SH_PFC_PIN_GROUP(msiof3_sync_b),
3890 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3891 SH_PFC_PIN_GROUP(msiof3_txd_b),
3892 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3893 SH_PFC_PIN_GROUP(pwm0_a),
3894 SH_PFC_PIN_GROUP(pwm0_b),
3895 SH_PFC_PIN_GROUP(pwm1_a),
3896 SH_PFC_PIN_GROUP(pwm1_b),
3897 SH_PFC_PIN_GROUP(pwm2_a),
3898 SH_PFC_PIN_GROUP(pwm2_b),
3899 SH_PFC_PIN_GROUP(pwm2_c),
3900 SH_PFC_PIN_GROUP(pwm3_a),
3901 SH_PFC_PIN_GROUP(pwm3_b),
3902 SH_PFC_PIN_GROUP(pwm3_c),
3903 SH_PFC_PIN_GROUP(pwm4_a),
3904 SH_PFC_PIN_GROUP(pwm4_b),
3905 SH_PFC_PIN_GROUP(pwm5_a),
3906 SH_PFC_PIN_GROUP(pwm5_b),
3907 SH_PFC_PIN_GROUP(pwm6_a),
3908 SH_PFC_PIN_GROUP(pwm6_b),
3909 SH_PFC_PIN_GROUP(scif0_data_a),
3910 SH_PFC_PIN_GROUP(scif0_clk_a),
3911 SH_PFC_PIN_GROUP(scif0_ctrl_a),
3912 SH_PFC_PIN_GROUP(scif0_data_b),
3913 SH_PFC_PIN_GROUP(scif0_clk_b),
3914 SH_PFC_PIN_GROUP(scif1_data),
3915 SH_PFC_PIN_GROUP(scif1_clk),
3916 SH_PFC_PIN_GROUP(scif1_ctrl),
3917 SH_PFC_PIN_GROUP(scif2_data_a),
3918 SH_PFC_PIN_GROUP(scif2_clk_a),
3919 SH_PFC_PIN_GROUP(scif2_data_b),
3920 SH_PFC_PIN_GROUP(scif3_data_a),
3921 SH_PFC_PIN_GROUP(scif3_clk_a),
3922 SH_PFC_PIN_GROUP(scif3_ctrl_a),
3923 SH_PFC_PIN_GROUP(scif3_data_b),
3924 SH_PFC_PIN_GROUP(scif3_data_c),
3925 SH_PFC_PIN_GROUP(scif3_clk_c),
3926 SH_PFC_PIN_GROUP(scif4_data_a),
3927 SH_PFC_PIN_GROUP(scif4_clk_a),
3928 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3929 SH_PFC_PIN_GROUP(scif4_data_b),
3930 SH_PFC_PIN_GROUP(scif4_clk_b),
3931 SH_PFC_PIN_GROUP(scif4_data_c),
3932 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3933 SH_PFC_PIN_GROUP(scif5_data_a),
3934 SH_PFC_PIN_GROUP(scif5_clk_a),
3935 SH_PFC_PIN_GROUP(scif5_data_b),
3936 SH_PFC_PIN_GROUP(scif5_data_c),
3937 SH_PFC_PIN_GROUP(scif_clk_a),
3938 SH_PFC_PIN_GROUP(scif_clk_b),
3939 SH_PFC_PIN_GROUP(sdhi0_data1),
3940 SH_PFC_PIN_GROUP(sdhi0_data4),
3941 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3942 SH_PFC_PIN_GROUP(sdhi0_cd),
3943 SH_PFC_PIN_GROUP(sdhi0_wp),
3944 SH_PFC_PIN_GROUP(sdhi1_data1),
3945 SH_PFC_PIN_GROUP(sdhi1_data4),
3946 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3947 SH_PFC_PIN_GROUP(sdhi1_cd),
3948 SH_PFC_PIN_GROUP(sdhi1_wp),
3949 SH_PFC_PIN_GROUP(sdhi3_data1),
3950 SH_PFC_PIN_GROUP(sdhi3_data4),
3951 SH_PFC_PIN_GROUP(sdhi3_data8),
3952 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3953 SH_PFC_PIN_GROUP(sdhi3_cd),
3954 SH_PFC_PIN_GROUP(sdhi3_wp),
3955 SH_PFC_PIN_GROUP(sdhi3_ds),
3956 SH_PFC_PIN_GROUP(ssi0_data),
3957 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3958 SH_PFC_PIN_GROUP(ssi1_data),
3959 SH_PFC_PIN_GROUP(ssi1_ctrl),
3960 SH_PFC_PIN_GROUP(ssi2_data),
3961 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3962 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3963 SH_PFC_PIN_GROUP(ssi3_data),
3964 SH_PFC_PIN_GROUP(ssi349_ctrl),
3965 SH_PFC_PIN_GROUP(ssi4_data),
3966 SH_PFC_PIN_GROUP(ssi4_ctrl),
3967 SH_PFC_PIN_GROUP(ssi5_data),
3968 SH_PFC_PIN_GROUP(ssi5_ctrl),
3969 SH_PFC_PIN_GROUP(ssi6_data),
3970 SH_PFC_PIN_GROUP(ssi6_ctrl),
3971 SH_PFC_PIN_GROUP(ssi7_data),
3972 SH_PFC_PIN_GROUP(ssi78_ctrl),
3973 SH_PFC_PIN_GROUP(ssi8_data),
3974 SH_PFC_PIN_GROUP(ssi9_data),
3975 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3976 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3977 SH_PFC_PIN_GROUP(tmu_tclk1_a),
3978 SH_PFC_PIN_GROUP(tmu_tclk1_b),
3979 SH_PFC_PIN_GROUP(tmu_tclk2_a),
3980 SH_PFC_PIN_GROUP(tmu_tclk2_b),
3981 SH_PFC_PIN_GROUP(usb0_a),
3982 SH_PFC_PIN_GROUP(usb0_b),
3983 SH_PFC_PIN_GROUP(usb0_id),
3984 SH_PFC_PIN_GROUP(usb30),
3985 SH_PFC_PIN_GROUP(usb30_id),
3986 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
3987 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
3988 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
3989 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
3990 SH_PFC_PIN_GROUP(vin4_data18_a),
3991 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
3992 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
3993 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
3994 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
3995 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
3996 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
3997 SH_PFC_PIN_GROUP(vin4_data18_b),
3998 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
3999 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4000 SH_PFC_PIN_GROUP(vin4_sync),
4001 SH_PFC_PIN_GROUP(vin4_field),
4002 SH_PFC_PIN_GROUP(vin4_clkenb),
4003 SH_PFC_PIN_GROUP(vin4_clk),
4004 VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
4005 VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
4006 VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
4007 VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
4008 SH_PFC_PIN_GROUP(vin5_data8_b),
4009 SH_PFC_PIN_GROUP(vin5_sync_a),
4010 SH_PFC_PIN_GROUP(vin5_field_a),
4011 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4012 SH_PFC_PIN_GROUP(vin5_clk_a),
4013 SH_PFC_PIN_GROUP(vin5_clk_b),
4014 },
4015 .automotive = {
4016 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4017 SH_PFC_PIN_GROUP(drif0_data0_a),
4018 SH_PFC_PIN_GROUP(drif0_data1_a),
4019 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4020 SH_PFC_PIN_GROUP(drif0_data0_b),
4021 SH_PFC_PIN_GROUP(drif0_data1_b),
4022 SH_PFC_PIN_GROUP(drif1_ctrl),
4023 SH_PFC_PIN_GROUP(drif1_data0),
4024 SH_PFC_PIN_GROUP(drif1_data1),
4025 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4026 SH_PFC_PIN_GROUP(drif2_data0_a),
4027 SH_PFC_PIN_GROUP(drif2_data1_a),
4028 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4029 SH_PFC_PIN_GROUP(drif2_data0_b),
4030 SH_PFC_PIN_GROUP(drif2_data1_b),
4031 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4032 SH_PFC_PIN_GROUP(drif3_data0_a),
4033 SH_PFC_PIN_GROUP(drif3_data1_a),
4034 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4035 SH_PFC_PIN_GROUP(drif3_data0_b),
4036 SH_PFC_PIN_GROUP(drif3_data1_b),
4037 }
4038 };
4039
4040 static const char * const audio_clk_groups[] = {
4041 "audio_clk_a",
4042 "audio_clk_b_a",
4043 "audio_clk_b_b",
4044 "audio_clk_b_c",
4045 "audio_clk_c_a",
4046 "audio_clk_c_b",
4047 "audio_clk_c_c",
4048 "audio_clkout_a",
4049 "audio_clkout_b",
4050 "audio_clkout1_a",
4051 "audio_clkout1_b",
4052 "audio_clkout1_c",
4053 "audio_clkout2_a",
4054 "audio_clkout2_b",
4055 "audio_clkout2_c",
4056 "audio_clkout3_a",
4057 "audio_clkout3_b",
4058 "audio_clkout3_c",
4059 };
4060
4061 static const char * const avb_groups[] = {
4062 "avb_link",
4063 "avb_magic",
4064 "avb_phy_int",
4065 "avb_mii",
4066 "avb_avtp_pps",
4067 "avb_avtp_match_a",
4068 "avb_avtp_capture_a",
4069 };
4070
4071 static const char * const can0_groups[] = {
4072 "can0_data",
4073 };
4074
4075 static const char * const can1_groups[] = {
4076 "can1_data",
4077 };
4078
4079 static const char * const can_clk_groups[] = {
4080 "can_clk",
4081 };
4082
4083 static const char * const canfd0_groups[] = {
4084 "canfd0_data",
4085 };
4086
4087 static const char * const canfd1_groups[] = {
4088 "canfd1_data",
4089 };
4090
4091 static const char * const drif0_groups[] = {
4092 "drif0_ctrl_a",
4093 "drif0_data0_a",
4094 "drif0_data1_a",
4095 "drif0_ctrl_b",
4096 "drif0_data0_b",
4097 "drif0_data1_b",
4098 };
4099
4100 static const char * const drif1_groups[] = {
4101 "drif1_ctrl",
4102 "drif1_data0",
4103 "drif1_data1",
4104 };
4105
4106 static const char * const drif2_groups[] = {
4107 "drif2_ctrl_a",
4108 "drif2_data0_a",
4109 "drif2_data1_a",
4110 "drif2_ctrl_b",
4111 "drif2_data0_b",
4112 "drif2_data1_b",
4113 };
4114
4115 static const char * const drif3_groups[] = {
4116 "drif3_ctrl_a",
4117 "drif3_data0_a",
4118 "drif3_data1_a",
4119 "drif3_ctrl_b",
4120 "drif3_data0_b",
4121 "drif3_data1_b",
4122 };
4123
4124 static const char * const du_groups[] = {
4125 "du_rgb666",
4126 "du_rgb888",
4127 "du_clk_in_0",
4128 "du_clk_in_1",
4129 "du_clk_out_0",
4130 "du_sync",
4131 "du_disp_cde",
4132 "du_cde",
4133 "du_disp",
4134 };
4135
4136 static const char * const hscif0_groups[] = {
4137 "hscif0_data_a",
4138 "hscif0_clk_a",
4139 "hscif0_ctrl_a",
4140 "hscif0_data_b",
4141 "hscif0_clk_b",
4142 };
4143
4144 static const char * const hscif1_groups[] = {
4145 "hscif1_data_a",
4146 "hscif1_clk_a",
4147 "hscif1_data_b",
4148 "hscif1_clk_b",
4149 "hscif1_ctrl_b",
4150 };
4151
4152 static const char * const hscif2_groups[] = {
4153 "hscif2_data_a",
4154 "hscif2_clk_a",
4155 "hscif2_ctrl_a",
4156 "hscif2_data_b",
4157 };
4158
4159 static const char * const hscif3_groups[] = {
4160 "hscif3_data_a",
4161 "hscif3_data_b",
4162 "hscif3_clk_b",
4163 "hscif3_data_c",
4164 "hscif3_clk_c",
4165 "hscif3_ctrl_c",
4166 "hscif3_data_d",
4167 "hscif3_data_e",
4168 "hscif3_ctrl_e",
4169 };
4170
4171 static const char * const hscif4_groups[] = {
4172 "hscif4_data_a",
4173 "hscif4_clk_a",
4174 "hscif4_ctrl_a",
4175 "hscif4_data_b",
4176 "hscif4_clk_b",
4177 "hscif4_data_c",
4178 "hscif4_data_d",
4179 "hscif4_data_e",
4180 };
4181
4182 static const char * const i2c1_groups[] = {
4183 "i2c1_a",
4184 "i2c1_b",
4185 "i2c1_c",
4186 "i2c1_d",
4187 };
4188
4189 static const char * const i2c2_groups[] = {
4190 "i2c2_a",
4191 "i2c2_b",
4192 "i2c2_c",
4193 "i2c2_d",
4194 "i2c2_e",
4195 };
4196
4197 static const char * const i2c4_groups[] = {
4198 "i2c4",
4199 };
4200
4201 static const char * const i2c5_groups[] = {
4202 "i2c5",
4203 };
4204
4205 static const char * const i2c6_groups[] = {
4206 "i2c6_a",
4207 "i2c6_b",
4208 };
4209
4210 static const char * const i2c7_groups[] = {
4211 "i2c7_a",
4212 "i2c7_b",
4213 };
4214
4215 static const char * const intc_ex_groups[] = {
4216 "intc_ex_irq0",
4217 "intc_ex_irq1",
4218 "intc_ex_irq2",
4219 "intc_ex_irq3",
4220 "intc_ex_irq4",
4221 "intc_ex_irq5",
4222 };
4223
4224 static const char * const msiof0_groups[] = {
4225 "msiof0_clk",
4226 "msiof0_sync",
4227 "msiof0_ss1",
4228 "msiof0_ss2",
4229 "msiof0_txd",
4230 "msiof0_rxd",
4231 };
4232
4233 static const char * const msiof1_groups[] = {
4234 "msiof1_clk",
4235 "msiof1_sync",
4236 "msiof1_ss1",
4237 "msiof1_ss2",
4238 "msiof1_txd",
4239 "msiof1_rxd",
4240 };
4241
4242 static const char * const msiof2_groups[] = {
4243 "msiof2_clk_a",
4244 "msiof2_sync_a",
4245 "msiof2_ss1_a",
4246 "msiof2_ss2_a",
4247 "msiof2_txd_a",
4248 "msiof2_rxd_a",
4249 "msiof2_clk_b",
4250 "msiof2_sync_b",
4251 "msiof2_ss1_b",
4252 "msiof2_ss2_b",
4253 "msiof2_txd_b",
4254 "msiof2_rxd_b",
4255 };
4256
4257 static const char * const msiof3_groups[] = {
4258 "msiof3_clk_a",
4259 "msiof3_sync_a",
4260 "msiof3_ss1_a",
4261 "msiof3_ss2_a",
4262 "msiof3_txd_a",
4263 "msiof3_rxd_a",
4264 "msiof3_clk_b",
4265 "msiof3_sync_b",
4266 "msiof3_ss1_b",
4267 "msiof3_txd_b",
4268 "msiof3_rxd_b",
4269 };
4270
4271 static const char * const pwm0_groups[] = {
4272 "pwm0_a",
4273 "pwm0_b",
4274 };
4275
4276 static const char * const pwm1_groups[] = {
4277 "pwm1_a",
4278 "pwm1_b",
4279 };
4280
4281 static const char * const pwm2_groups[] = {
4282 "pwm2_a",
4283 "pwm2_b",
4284 "pwm2_c",
4285 };
4286
4287 static const char * const pwm3_groups[] = {
4288 "pwm3_a",
4289 "pwm3_b",
4290 "pwm3_c",
4291 };
4292
4293 static const char * const pwm4_groups[] = {
4294 "pwm4_a",
4295 "pwm4_b",
4296 };
4297
4298 static const char * const pwm5_groups[] = {
4299 "pwm5_a",
4300 "pwm5_b",
4301 };
4302
4303 static const char * const pwm6_groups[] = {
4304 "pwm6_a",
4305 "pwm6_b",
4306 };
4307
4308 static const char * const scif0_groups[] = {
4309 "scif0_data_a",
4310 "scif0_clk_a",
4311 "scif0_ctrl_a",
4312 "scif0_data_b",
4313 "scif0_clk_b",
4314 };
4315
4316 static const char * const scif1_groups[] = {
4317 "scif1_data",
4318 "scif1_clk",
4319 "scif1_ctrl",
4320 };
4321
4322 static const char * const scif2_groups[] = {
4323 "scif2_data_a",
4324 "scif2_clk_a",
4325 "scif2_data_b",
4326 };
4327
4328 static const char * const scif3_groups[] = {
4329 "scif3_data_a",
4330 "scif3_clk_a",
4331 "scif3_ctrl_a",
4332 "scif3_data_b",
4333 "scif3_data_c",
4334 "scif3_clk_c",
4335 };
4336
4337 static const char * const scif4_groups[] = {
4338 "scif4_data_a",
4339 "scif4_clk_a",
4340 "scif4_ctrl_a",
4341 "scif4_data_b",
4342 "scif4_clk_b",
4343 "scif4_data_c",
4344 "scif4_ctrl_c",
4345 };
4346
4347 static const char * const scif5_groups[] = {
4348 "scif5_data_a",
4349 "scif5_clk_a",
4350 "scif5_data_b",
4351 "scif5_data_c",
4352 };
4353
4354 static const char * const scif_clk_groups[] = {
4355 "scif_clk_a",
4356 "scif_clk_b",
4357 };
4358
4359 static const char * const sdhi0_groups[] = {
4360 "sdhi0_data1",
4361 "sdhi0_data4",
4362 "sdhi0_ctrl",
4363 "sdhi0_cd",
4364 "sdhi0_wp",
4365 };
4366
4367 static const char * const sdhi1_groups[] = {
4368 "sdhi1_data1",
4369 "sdhi1_data4",
4370 "sdhi1_ctrl",
4371 "sdhi1_cd",
4372 "sdhi1_wp",
4373 };
4374
4375 static const char * const sdhi3_groups[] = {
4376 "sdhi3_data1",
4377 "sdhi3_data4",
4378 "sdhi3_data8",
4379 "sdhi3_ctrl",
4380 "sdhi3_cd",
4381 "sdhi3_wp",
4382 "sdhi3_ds",
4383 };
4384
4385 static const char * const ssi_groups[] = {
4386 "ssi0_data",
4387 "ssi01239_ctrl",
4388 "ssi1_data",
4389 "ssi1_ctrl",
4390 "ssi2_data",
4391 "ssi2_ctrl_a",
4392 "ssi2_ctrl_b",
4393 "ssi3_data",
4394 "ssi349_ctrl",
4395 "ssi4_data",
4396 "ssi4_ctrl",
4397 "ssi5_data",
4398 "ssi5_ctrl",
4399 "ssi6_data",
4400 "ssi6_ctrl",
4401 "ssi7_data",
4402 "ssi78_ctrl",
4403 "ssi8_data",
4404 "ssi9_data",
4405 "ssi9_ctrl_a",
4406 "ssi9_ctrl_b",
4407 };
4408
4409 static const char * const tmu_groups[] = {
4410 "tmu_tclk1_a",
4411 "tmu_tclk1_b",
4412 "tmu_tclk2_a",
4413 "tmu_tclk2_b",
4414 };
4415
4416 static const char * const usb0_groups[] = {
4417 "usb0_a",
4418 "usb0_b",
4419 "usb0_id",
4420 };
4421
4422 static const char * const usb30_groups[] = {
4423 "usb30",
4424 "usb30_id",
4425 };
4426
4427 static const char * const vin4_groups[] = {
4428 "vin4_data8_a",
4429 "vin4_data10_a",
4430 "vin4_data12_a",
4431 "vin4_data16_a",
4432 "vin4_data18_a",
4433 "vin4_data20_a",
4434 "vin4_data24_a",
4435 "vin4_data8_b",
4436 "vin4_data10_b",
4437 "vin4_data12_b",
4438 "vin4_data16_b",
4439 "vin4_data18_b",
4440 "vin4_data20_b",
4441 "vin4_data24_b",
4442 "vin4_sync",
4443 "vin4_field",
4444 "vin4_clkenb",
4445 "vin4_clk",
4446 };
4447
4448 static const char * const vin5_groups[] = {
4449 "vin5_data8_a",
4450 "vin5_data10_a",
4451 "vin5_data12_a",
4452 "vin5_data16_a",
4453 "vin5_data8_b",
4454 "vin5_sync_a",
4455 "vin5_field_a",
4456 "vin5_clkenb_a",
4457 "vin5_clk_a",
4458 "vin5_clk_b",
4459 };
4460
4461 static const struct {
4462 struct sh_pfc_function common[47];
4463 struct sh_pfc_function automotive[4];
4464 } pinmux_functions = {
4465 .common = {
4466 SH_PFC_FUNCTION(audio_clk),
4467 SH_PFC_FUNCTION(avb),
4468 SH_PFC_FUNCTION(can0),
4469 SH_PFC_FUNCTION(can1),
4470 SH_PFC_FUNCTION(can_clk),
4471 SH_PFC_FUNCTION(canfd0),
4472 SH_PFC_FUNCTION(canfd1),
4473 SH_PFC_FUNCTION(du),
4474 SH_PFC_FUNCTION(hscif0),
4475 SH_PFC_FUNCTION(hscif1),
4476 SH_PFC_FUNCTION(hscif2),
4477 SH_PFC_FUNCTION(hscif3),
4478 SH_PFC_FUNCTION(hscif4),
4479 SH_PFC_FUNCTION(i2c1),
4480 SH_PFC_FUNCTION(i2c2),
4481 SH_PFC_FUNCTION(i2c4),
4482 SH_PFC_FUNCTION(i2c5),
4483 SH_PFC_FUNCTION(i2c6),
4484 SH_PFC_FUNCTION(i2c7),
4485 SH_PFC_FUNCTION(intc_ex),
4486 SH_PFC_FUNCTION(msiof0),
4487 SH_PFC_FUNCTION(msiof1),
4488 SH_PFC_FUNCTION(msiof2),
4489 SH_PFC_FUNCTION(msiof3),
4490 SH_PFC_FUNCTION(pwm0),
4491 SH_PFC_FUNCTION(pwm1),
4492 SH_PFC_FUNCTION(pwm2),
4493 SH_PFC_FUNCTION(pwm3),
4494 SH_PFC_FUNCTION(pwm4),
4495 SH_PFC_FUNCTION(pwm5),
4496 SH_PFC_FUNCTION(pwm6),
4497 SH_PFC_FUNCTION(scif0),
4498 SH_PFC_FUNCTION(scif1),
4499 SH_PFC_FUNCTION(scif2),
4500 SH_PFC_FUNCTION(scif3),
4501 SH_PFC_FUNCTION(scif4),
4502 SH_PFC_FUNCTION(scif5),
4503 SH_PFC_FUNCTION(scif_clk),
4504 SH_PFC_FUNCTION(sdhi0),
4505 SH_PFC_FUNCTION(sdhi1),
4506 SH_PFC_FUNCTION(sdhi3),
4507 SH_PFC_FUNCTION(ssi),
4508 SH_PFC_FUNCTION(tmu),
4509 SH_PFC_FUNCTION(usb0),
4510 SH_PFC_FUNCTION(usb30),
4511 SH_PFC_FUNCTION(vin4),
4512 SH_PFC_FUNCTION(vin5),
4513 },
4514 .automotive = {
4515 SH_PFC_FUNCTION(drif0),
4516 SH_PFC_FUNCTION(drif1),
4517 SH_PFC_FUNCTION(drif2),
4518 SH_PFC_FUNCTION(drif3),
4519 }
4520 };
4521
4522 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4523 #define F_(x, y) FN_##y
4524 #define FM(x) FN_##x
4525 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4526 0, 0,
4527 0, 0,
4528 0, 0,
4529 0, 0,
4530 0, 0,
4531 0, 0,
4532 0, 0,
4533 0, 0,
4534 0, 0,
4535 0, 0,
4536 0, 0,
4537 0, 0,
4538 0, 0,
4539 0, 0,
4540 GP_0_17_FN, GPSR0_17,
4541 GP_0_16_FN, GPSR0_16,
4542 GP_0_15_FN, GPSR0_15,
4543 GP_0_14_FN, GPSR0_14,
4544 GP_0_13_FN, GPSR0_13,
4545 GP_0_12_FN, GPSR0_12,
4546 GP_0_11_FN, GPSR0_11,
4547 GP_0_10_FN, GPSR0_10,
4548 GP_0_9_FN, GPSR0_9,
4549 GP_0_8_FN, GPSR0_8,
4550 GP_0_7_FN, GPSR0_7,
4551 GP_0_6_FN, GPSR0_6,
4552 GP_0_5_FN, GPSR0_5,
4553 GP_0_4_FN, GPSR0_4,
4554 GP_0_3_FN, GPSR0_3,
4555 GP_0_2_FN, GPSR0_2,
4556 GP_0_1_FN, GPSR0_1,
4557 GP_0_0_FN, GPSR0_0, ))
4558 },
4559 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4560 0, 0,
4561 0, 0,
4562 0, 0,
4563 0, 0,
4564 0, 0,
4565 0, 0,
4566 0, 0,
4567 0, 0,
4568 0, 0,
4569 GP_1_22_FN, GPSR1_22,
4570 GP_1_21_FN, GPSR1_21,
4571 GP_1_20_FN, GPSR1_20,
4572 GP_1_19_FN, GPSR1_19,
4573 GP_1_18_FN, GPSR1_18,
4574 GP_1_17_FN, GPSR1_17,
4575 GP_1_16_FN, GPSR1_16,
4576 GP_1_15_FN, GPSR1_15,
4577 GP_1_14_FN, GPSR1_14,
4578 GP_1_13_FN, GPSR1_13,
4579 GP_1_12_FN, GPSR1_12,
4580 GP_1_11_FN, GPSR1_11,
4581 GP_1_10_FN, GPSR1_10,
4582 GP_1_9_FN, GPSR1_9,
4583 GP_1_8_FN, GPSR1_8,
4584 GP_1_7_FN, GPSR1_7,
4585 GP_1_6_FN, GPSR1_6,
4586 GP_1_5_FN, GPSR1_5,
4587 GP_1_4_FN, GPSR1_4,
4588 GP_1_3_FN, GPSR1_3,
4589 GP_1_2_FN, GPSR1_2,
4590 GP_1_1_FN, GPSR1_1,
4591 GP_1_0_FN, GPSR1_0, ))
4592 },
4593 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4594 0, 0,
4595 0, 0,
4596 0, 0,
4597 0, 0,
4598 0, 0,
4599 0, 0,
4600 GP_2_25_FN, GPSR2_25,
4601 GP_2_24_FN, GPSR2_24,
4602 GP_2_23_FN, GPSR2_23,
4603 GP_2_22_FN, GPSR2_22,
4604 GP_2_21_FN, GPSR2_21,
4605 GP_2_20_FN, GPSR2_20,
4606 GP_2_19_FN, GPSR2_19,
4607 GP_2_18_FN, GPSR2_18,
4608 GP_2_17_FN, GPSR2_17,
4609 GP_2_16_FN, GPSR2_16,
4610 GP_2_15_FN, GPSR2_15,
4611 GP_2_14_FN, GPSR2_14,
4612 GP_2_13_FN, GPSR2_13,
4613 GP_2_12_FN, GPSR2_12,
4614 GP_2_11_FN, GPSR2_11,
4615 GP_2_10_FN, GPSR2_10,
4616 GP_2_9_FN, GPSR2_9,
4617 GP_2_8_FN, GPSR2_8,
4618 GP_2_7_FN, GPSR2_7,
4619 GP_2_6_FN, GPSR2_6,
4620 GP_2_5_FN, GPSR2_5,
4621 GP_2_4_FN, GPSR2_4,
4622 GP_2_3_FN, GPSR2_3,
4623 GP_2_2_FN, GPSR2_2,
4624 GP_2_1_FN, GPSR2_1,
4625 GP_2_0_FN, GPSR2_0, ))
4626 },
4627 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4628 0, 0,
4629 0, 0,
4630 0, 0,
4631 0, 0,
4632 0, 0,
4633 0, 0,
4634 0, 0,
4635 0, 0,
4636 0, 0,
4637 0, 0,
4638 0, 0,
4639 0, 0,
4640 0, 0,
4641 0, 0,
4642 0, 0,
4643 0, 0,
4644 GP_3_15_FN, GPSR3_15,
4645 GP_3_14_FN, GPSR3_14,
4646 GP_3_13_FN, GPSR3_13,
4647 GP_3_12_FN, GPSR3_12,
4648 GP_3_11_FN, GPSR3_11,
4649 GP_3_10_FN, GPSR3_10,
4650 GP_3_9_FN, GPSR3_9,
4651 GP_3_8_FN, GPSR3_8,
4652 GP_3_7_FN, GPSR3_7,
4653 GP_3_6_FN, GPSR3_6,
4654 GP_3_5_FN, GPSR3_5,
4655 GP_3_4_FN, GPSR3_4,
4656 GP_3_3_FN, GPSR3_3,
4657 GP_3_2_FN, GPSR3_2,
4658 GP_3_1_FN, GPSR3_1,
4659 GP_3_0_FN, GPSR3_0, ))
4660 },
4661 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4662 0, 0,
4663 0, 0,
4664 0, 0,
4665 0, 0,
4666 0, 0,
4667 0, 0,
4668 0, 0,
4669 0, 0,
4670 0, 0,
4671 0, 0,
4672 0, 0,
4673 0, 0,
4674 0, 0,
4675 0, 0,
4676 0, 0,
4677 0, 0,
4678 0, 0,
4679 0, 0,
4680 0, 0,
4681 0, 0,
4682 0, 0,
4683 GP_4_10_FN, GPSR4_10,
4684 GP_4_9_FN, GPSR4_9,
4685 GP_4_8_FN, GPSR4_8,
4686 GP_4_7_FN, GPSR4_7,
4687 GP_4_6_FN, GPSR4_6,
4688 GP_4_5_FN, GPSR4_5,
4689 GP_4_4_FN, GPSR4_4,
4690 GP_4_3_FN, GPSR4_3,
4691 GP_4_2_FN, GPSR4_2,
4692 GP_4_1_FN, GPSR4_1,
4693 GP_4_0_FN, GPSR4_0, ))
4694 },
4695 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 0, 0,
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 0, 0,
4706 0, 0,
4707 0, 0,
4708 GP_5_19_FN, GPSR5_19,
4709 GP_5_18_FN, GPSR5_18,
4710 GP_5_17_FN, GPSR5_17,
4711 GP_5_16_FN, GPSR5_16,
4712 GP_5_15_FN, GPSR5_15,
4713 GP_5_14_FN, GPSR5_14,
4714 GP_5_13_FN, GPSR5_13,
4715 GP_5_12_FN, GPSR5_12,
4716 GP_5_11_FN, GPSR5_11,
4717 GP_5_10_FN, GPSR5_10,
4718 GP_5_9_FN, GPSR5_9,
4719 GP_5_8_FN, GPSR5_8,
4720 GP_5_7_FN, GPSR5_7,
4721 GP_5_6_FN, GPSR5_6,
4722 GP_5_5_FN, GPSR5_5,
4723 GP_5_4_FN, GPSR5_4,
4724 GP_5_3_FN, GPSR5_3,
4725 GP_5_2_FN, GPSR5_2,
4726 GP_5_1_FN, GPSR5_1,
4727 GP_5_0_FN, GPSR5_0, ))
4728 },
4729 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4730 0, 0,
4731 0, 0,
4732 0, 0,
4733 0, 0,
4734 0, 0,
4735 0, 0,
4736 0, 0,
4737 0, 0,
4738 0, 0,
4739 0, 0,
4740 0, 0,
4741 0, 0,
4742 0, 0,
4743 0, 0,
4744 GP_6_17_FN, GPSR6_17,
4745 GP_6_16_FN, GPSR6_16,
4746 GP_6_15_FN, GPSR6_15,
4747 GP_6_14_FN, GPSR6_14,
4748 GP_6_13_FN, GPSR6_13,
4749 GP_6_12_FN, GPSR6_12,
4750 GP_6_11_FN, GPSR6_11,
4751 GP_6_10_FN, GPSR6_10,
4752 GP_6_9_FN, GPSR6_9,
4753 GP_6_8_FN, GPSR6_8,
4754 GP_6_7_FN, GPSR6_7,
4755 GP_6_6_FN, GPSR6_6,
4756 GP_6_5_FN, GPSR6_5,
4757 GP_6_4_FN, GPSR6_4,
4758 GP_6_3_FN, GPSR6_3,
4759 GP_6_2_FN, GPSR6_2,
4760 GP_6_1_FN, GPSR6_1,
4761 GP_6_0_FN, GPSR6_0, ))
4762 },
4763 #undef F_
4764 #undef FM
4765
4766 #define F_(x, y) x,
4767 #define FM(x) FN_##x,
4768 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4769 IP0_31_28
4770 IP0_27_24
4771 IP0_23_20
4772 IP0_19_16
4773 IP0_15_12
4774 IP0_11_8
4775 IP0_7_4
4776 IP0_3_0 ))
4777 },
4778 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4779 IP1_31_28
4780 IP1_27_24
4781 IP1_23_20
4782 IP1_19_16
4783 IP1_15_12
4784 IP1_11_8
4785 IP1_7_4
4786 IP1_3_0 ))
4787 },
4788 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4789 IP2_31_28
4790 IP2_27_24
4791 IP2_23_20
4792 IP2_19_16
4793 IP2_15_12
4794 IP2_11_8
4795 IP2_7_4
4796 IP2_3_0 ))
4797 },
4798 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4799 IP3_31_28
4800 IP3_27_24
4801 IP3_23_20
4802 IP3_19_16
4803 IP3_15_12
4804 IP3_11_8
4805 IP3_7_4
4806 IP3_3_0 ))
4807 },
4808 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4809 IP4_31_28
4810 IP4_27_24
4811 IP4_23_20
4812 IP4_19_16
4813 IP4_15_12
4814 IP4_11_8
4815 IP4_7_4
4816 IP4_3_0 ))
4817 },
4818 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4819 IP5_31_28
4820 IP5_27_24
4821 IP5_23_20
4822 IP5_19_16
4823 IP5_15_12
4824 IP5_11_8
4825 IP5_7_4
4826 IP5_3_0 ))
4827 },
4828 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4829 IP6_31_28
4830 IP6_27_24
4831 IP6_23_20
4832 IP6_19_16
4833 IP6_15_12
4834 IP6_11_8
4835 IP6_7_4
4836 IP6_3_0 ))
4837 },
4838 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4839 IP7_31_28
4840 IP7_27_24
4841 IP7_23_20
4842 IP7_19_16
4843 IP7_15_12
4844 IP7_11_8
4845 IP7_7_4
4846 IP7_3_0 ))
4847 },
4848 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4849 IP8_31_28
4850 IP8_27_24
4851 IP8_23_20
4852 IP8_19_16
4853 IP8_15_12
4854 IP8_11_8
4855 IP8_7_4
4856 IP8_3_0 ))
4857 },
4858 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4859 IP9_31_28
4860 IP9_27_24
4861 IP9_23_20
4862 IP9_19_16
4863 IP9_15_12
4864 IP9_11_8
4865 IP9_7_4
4866 IP9_3_0 ))
4867 },
4868 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4869 IP10_31_28
4870 IP10_27_24
4871 IP10_23_20
4872 IP10_19_16
4873 IP10_15_12
4874 IP10_11_8
4875 IP10_7_4
4876 IP10_3_0 ))
4877 },
4878 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4879 IP11_31_28
4880 IP11_27_24
4881 IP11_23_20
4882 IP11_19_16
4883 IP11_15_12
4884 IP11_11_8
4885 IP11_7_4
4886 IP11_3_0 ))
4887 },
4888 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4889 IP12_31_28
4890 IP12_27_24
4891 IP12_23_20
4892 IP12_19_16
4893 IP12_15_12
4894 IP12_11_8
4895 IP12_7_4
4896 IP12_3_0 ))
4897 },
4898 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4899 IP13_31_28
4900 IP13_27_24
4901 IP13_23_20
4902 IP13_19_16
4903 IP13_15_12
4904 IP13_11_8
4905 IP13_7_4
4906 IP13_3_0 ))
4907 },
4908 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4909 IP14_31_28
4910 IP14_27_24
4911 IP14_23_20
4912 IP14_19_16
4913 IP14_15_12
4914 IP14_11_8
4915 IP14_7_4
4916 IP14_3_0 ))
4917 },
4918 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
4919 IP15_31_28
4920 IP15_27_24
4921 IP15_23_20
4922 IP15_19_16
4923 IP15_15_12
4924 IP15_11_8
4925 IP15_7_4
4926 IP15_3_0 ))
4927 },
4928 #undef F_
4929 #undef FM
4930
4931 #define F_(x, y) x,
4932 #define FM(x) FN_##x,
4933 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4934 GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
4935 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
4936 GROUP(
4937
4938 0, 0,
4939 MOD_SEL0_30_29
4940 MOD_SEL0_28
4941 MOD_SEL0_27_26
4942 MOD_SEL0_25
4943 MOD_SEL0_24
4944 MOD_SEL0_23
4945 MOD_SEL0_22
4946 MOD_SEL0_21_20
4947 MOD_SEL0_19_18_17
4948 MOD_SEL0_16
4949 MOD_SEL0_15
4950 MOD_SEL0_14
4951 MOD_SEL0_13_12
4952 MOD_SEL0_11_10
4953 MOD_SEL0_9
4954 MOD_SEL0_8
4955 MOD_SEL0_7
4956 MOD_SEL0_6_5
4957 MOD_SEL0_4
4958 MOD_SEL0_3
4959 MOD_SEL0_2
4960 MOD_SEL0_1_0 ))
4961 },
4962 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4963 GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
4964 1, 2, 2, 2, 1, 1, 2, 1, 4),
4965 GROUP(
4966 MOD_SEL1_31
4967 MOD_SEL1_30
4968 MOD_SEL1_29
4969 MOD_SEL1_28
4970
4971 0, 0,
4972 MOD_SEL1_26
4973 MOD_SEL1_25
4974 MOD_SEL1_24_23_22
4975 MOD_SEL1_21_20_19
4976 MOD_SEL1_18
4977 MOD_SEL1_17
4978 MOD_SEL1_16
4979 MOD_SEL1_15
4980 MOD_SEL1_14_13
4981 MOD_SEL1_12_11
4982 MOD_SEL1_10_9
4983 MOD_SEL1_8
4984 MOD_SEL1_7
4985 MOD_SEL1_6_5
4986 MOD_SEL1_4
4987
4988 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
4989 },
4990 { },
4991 };
4992
4993 enum ioctrl_regs {
4994 POCCTRL0,
4995 TDSELCTRL,
4996 };
4997
4998 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4999 [POCCTRL0] = { 0xe6060380, },
5000 [TDSELCTRL] = { 0xe60603c0, },
5001 { },
5002 };
5003
5004 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5005 u32 *pocctrl)
5006 {
5007 int bit = -EINVAL;
5008
5009 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5010
5011 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5012 bit = pin & 0x1f;
5013
5014 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5015 bit = (pin & 0x1f) + 19;
5016
5017 return bit;
5018 }
5019
5020 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5021 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5022 [0] = RCAR_GP_PIN(2, 23),
5023 [1] = RCAR_GP_PIN(2, 22),
5024 [2] = RCAR_GP_PIN(2, 21),
5025 [3] = PIN_AVB_MDC,
5026 [4] = PIN_AVB_MDIO,
5027 [5] = RCAR_GP_PIN(2, 20),
5028 [6] = PIN_AVB_TD3,
5029 [7] = PIN_AVB_TD2,
5030 [8] = PIN_AVB_TD1,
5031 [9] = PIN_AVB_TD0,
5032 [10] = PIN_AVB_TXC,
5033 [11] = PIN_AVB_TX_CTL,
5034 [12] = RCAR_GP_PIN(2, 19),
5035 [13] = RCAR_GP_PIN(2, 18),
5036 [14] = RCAR_GP_PIN(2, 17),
5037 [15] = RCAR_GP_PIN(2, 16),
5038 [16] = RCAR_GP_PIN(2, 15),
5039 [17] = RCAR_GP_PIN(2, 14),
5040 [18] = RCAR_GP_PIN(2, 13),
5041 [19] = RCAR_GP_PIN(2, 12),
5042 [20] = RCAR_GP_PIN(2, 11),
5043 [21] = RCAR_GP_PIN(2, 10),
5044 [22] = RCAR_GP_PIN(2, 9),
5045 [23] = RCAR_GP_PIN(2, 8),
5046 [24] = RCAR_GP_PIN(2, 7),
5047 [25] = RCAR_GP_PIN(2, 6),
5048 [26] = RCAR_GP_PIN(2, 5),
5049 [27] = RCAR_GP_PIN(2, 4),
5050 [28] = RCAR_GP_PIN(2, 3),
5051 [29] = RCAR_GP_PIN(2, 2),
5052 [30] = RCAR_GP_PIN(2, 1),
5053 [31] = RCAR_GP_PIN(2, 0),
5054 } },
5055 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5056 [0] = RCAR_GP_PIN(0, 4),
5057 [1] = RCAR_GP_PIN(0, 3),
5058 [2] = RCAR_GP_PIN(0, 2),
5059 [3] = RCAR_GP_PIN(0, 1),
5060 [4] = RCAR_GP_PIN(0, 0),
5061 [5] = RCAR_GP_PIN(1, 22),
5062 [6] = RCAR_GP_PIN(1, 21),
5063 [7] = RCAR_GP_PIN(1, 20),
5064 [8] = RCAR_GP_PIN(1, 19),
5065 [9] = RCAR_GP_PIN(1, 18),
5066 [10] = RCAR_GP_PIN(1, 17),
5067 [11] = RCAR_GP_PIN(1, 16),
5068 [12] = RCAR_GP_PIN(1, 15),
5069 [13] = RCAR_GP_PIN(1, 14),
5070 [14] = RCAR_GP_PIN(1, 13),
5071 [15] = RCAR_GP_PIN(1, 12),
5072 [16] = RCAR_GP_PIN(1, 11),
5073 [17] = RCAR_GP_PIN(1, 10),
5074 [18] = RCAR_GP_PIN(1, 9),
5075 [19] = RCAR_GP_PIN(1, 8),
5076 [20] = RCAR_GP_PIN(1, 7),
5077 [21] = RCAR_GP_PIN(1, 6),
5078 [22] = RCAR_GP_PIN(1, 5),
5079 [23] = RCAR_GP_PIN(1, 4),
5080 [24] = RCAR_GP_PIN(1, 3),
5081 [25] = RCAR_GP_PIN(1, 2),
5082 [26] = RCAR_GP_PIN(1, 1),
5083 [27] = RCAR_GP_PIN(1, 0),
5084 [28] = SH_PFC_PIN_NONE,
5085 [29] = SH_PFC_PIN_NONE,
5086 [30] = RCAR_GP_PIN(2, 25),
5087 [31] = RCAR_GP_PIN(2, 24),
5088 } },
5089 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5090 [0] = RCAR_GP_PIN(3, 1),
5091 [1] = RCAR_GP_PIN(3, 0),
5092 [2] = PIN_ASEBRK,
5093 [3] = SH_PFC_PIN_NONE,
5094 [4] = PIN_TDI,
5095 [5] = PIN_TMS,
5096 [6] = PIN_TCK,
5097 [7] = PIN_TRST_N,
5098 [8] = SH_PFC_PIN_NONE,
5099 [9] = SH_PFC_PIN_NONE,
5100 [10] = SH_PFC_PIN_NONE,
5101 [11] = SH_PFC_PIN_NONE,
5102 [12] = SH_PFC_PIN_NONE,
5103 [13] = SH_PFC_PIN_NONE,
5104 [14] = SH_PFC_PIN_NONE,
5105 [15] = PIN_FSCLKST_N,
5106 [16] = RCAR_GP_PIN(0, 17),
5107 [17] = RCAR_GP_PIN(0, 16),
5108 [18] = SH_PFC_PIN_NONE,
5109 [19] = SH_PFC_PIN_NONE,
5110 [20] = PIN_PRESETOUT_N,
5111 [21] = RCAR_GP_PIN(0, 15),
5112 [22] = RCAR_GP_PIN(0, 14),
5113 [23] = RCAR_GP_PIN(0, 13),
5114 [24] = RCAR_GP_PIN(0, 12),
5115 [25] = RCAR_GP_PIN(0, 11),
5116 [26] = RCAR_GP_PIN(0, 10),
5117 [27] = RCAR_GP_PIN(0, 9),
5118 [28] = RCAR_GP_PIN(0, 8),
5119 [29] = RCAR_GP_PIN(0, 7),
5120 [30] = RCAR_GP_PIN(0, 6),
5121 [31] = RCAR_GP_PIN(0, 5),
5122 } },
5123 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5124 [0] = RCAR_GP_PIN(5, 0),
5125 [1] = RCAR_GP_PIN(5, 4),
5126 [2] = RCAR_GP_PIN(5, 3),
5127 [3] = RCAR_GP_PIN(5, 2),
5128 [4] = RCAR_GP_PIN(5, 1),
5129 [5] = SH_PFC_PIN_NONE,
5130 [6] = SH_PFC_PIN_NONE,
5131 [7] = RCAR_GP_PIN(3, 15),
5132 [8] = RCAR_GP_PIN(3, 14),
5133 [9] = RCAR_GP_PIN(3, 13),
5134 [10] = RCAR_GP_PIN(3, 12),
5135 [11] = RCAR_GP_PIN(4, 10),
5136 [12] = RCAR_GP_PIN(4, 9),
5137 [13] = RCAR_GP_PIN(4, 8),
5138 [14] = RCAR_GP_PIN(4, 7),
5139 [15] = RCAR_GP_PIN(4, 6),
5140 [16] = RCAR_GP_PIN(4, 5),
5141 [17] = RCAR_GP_PIN(4, 4),
5142 [18] = RCAR_GP_PIN(4, 3),
5143 [19] = RCAR_GP_PIN(4, 2),
5144 [20] = RCAR_GP_PIN(4, 1),
5145 [21] = RCAR_GP_PIN(4, 0),
5146 [22] = RCAR_GP_PIN(3, 11),
5147 [23] = RCAR_GP_PIN(3, 10),
5148 [24] = RCAR_GP_PIN(3, 9),
5149 [25] = RCAR_GP_PIN(3, 8),
5150 [26] = RCAR_GP_PIN(3, 7),
5151 [27] = RCAR_GP_PIN(3, 6),
5152 [28] = RCAR_GP_PIN(3, 5),
5153 [29] = RCAR_GP_PIN(3, 4),
5154 [30] = RCAR_GP_PIN(3, 3),
5155 [31] = RCAR_GP_PIN(3, 2),
5156 } },
5157 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5158 [0] = RCAR_GP_PIN(6, 8),
5159 [1] = RCAR_GP_PIN(6, 16),
5160 [2] = RCAR_GP_PIN(6, 15),
5161 [3] = RCAR_GP_PIN(6, 14),
5162 [4] = RCAR_GP_PIN(6, 13),
5163 [5] = RCAR_GP_PIN(6, 12),
5164 [6] = RCAR_GP_PIN(6, 11),
5165 [7] = RCAR_GP_PIN(6, 10),
5166 [8] = RCAR_GP_PIN(6, 7),
5167 [9] = RCAR_GP_PIN(6, 6),
5168 [10] = RCAR_GP_PIN(6, 5),
5169 [11] = RCAR_GP_PIN(6, 4),
5170 [12] = RCAR_GP_PIN(6, 3),
5171 [13] = RCAR_GP_PIN(6, 2),
5172 [14] = RCAR_GP_PIN(6, 1),
5173 [15] = RCAR_GP_PIN(6, 0),
5174 [16] = PIN_MLB_REF,
5175 [17] = RCAR_GP_PIN(5, 19),
5176 [18] = RCAR_GP_PIN(5, 18),
5177 [19] = RCAR_GP_PIN(5, 17),
5178 [20] = RCAR_GP_PIN(5, 16),
5179 [21] = RCAR_GP_PIN(5, 15),
5180 [22] = RCAR_GP_PIN(5, 14),
5181 [23] = RCAR_GP_PIN(5, 13),
5182 [24] = RCAR_GP_PIN(5, 12),
5183 [25] = RCAR_GP_PIN(5, 11),
5184 [26] = RCAR_GP_PIN(5, 10),
5185 [27] = RCAR_GP_PIN(5, 9),
5186 [28] = RCAR_GP_PIN(5, 8),
5187 [29] = RCAR_GP_PIN(5, 7),
5188 [30] = RCAR_GP_PIN(5, 6),
5189 [31] = RCAR_GP_PIN(5, 5),
5190 } },
5191 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5192 [0] = SH_PFC_PIN_NONE,
5193 [1] = SH_PFC_PIN_NONE,
5194 [2] = SH_PFC_PIN_NONE,
5195 [3] = SH_PFC_PIN_NONE,
5196 [4] = SH_PFC_PIN_NONE,
5197 [5] = SH_PFC_PIN_NONE,
5198 [6] = SH_PFC_PIN_NONE,
5199 [7] = SH_PFC_PIN_NONE,
5200 [8] = SH_PFC_PIN_NONE,
5201 [9] = SH_PFC_PIN_NONE,
5202 [10] = SH_PFC_PIN_NONE,
5203 [11] = SH_PFC_PIN_NONE,
5204 [12] = SH_PFC_PIN_NONE,
5205 [13] = SH_PFC_PIN_NONE,
5206 [14] = SH_PFC_PIN_NONE,
5207 [15] = SH_PFC_PIN_NONE,
5208 [16] = SH_PFC_PIN_NONE,
5209 [17] = SH_PFC_PIN_NONE,
5210 [18] = SH_PFC_PIN_NONE,
5211 [19] = SH_PFC_PIN_NONE,
5212 [20] = SH_PFC_PIN_NONE,
5213 [21] = SH_PFC_PIN_NONE,
5214 [22] = SH_PFC_PIN_NONE,
5215 [23] = SH_PFC_PIN_NONE,
5216 [24] = SH_PFC_PIN_NONE,
5217 [25] = SH_PFC_PIN_NONE,
5218 [26] = SH_PFC_PIN_NONE,
5219 [27] = SH_PFC_PIN_NONE,
5220 [28] = SH_PFC_PIN_NONE,
5221 [29] = SH_PFC_PIN_NONE,
5222 [30] = RCAR_GP_PIN(6, 9),
5223 [31] = RCAR_GP_PIN(6, 17),
5224 } },
5225 { },
5226 };
5227
5228 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
5229 unsigned int pin)
5230 {
5231 const struct pinmux_bias_reg *reg;
5232 unsigned int bit;
5233
5234 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5235 if (!reg)
5236 return PIN_CONFIG_BIAS_DISABLE;
5237
5238 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5239 return PIN_CONFIG_BIAS_DISABLE;
5240 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5241 return PIN_CONFIG_BIAS_PULL_UP;
5242 else
5243 return PIN_CONFIG_BIAS_PULL_DOWN;
5244 }
5245
5246 static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5247 unsigned int bias)
5248 {
5249 const struct pinmux_bias_reg *reg;
5250 u32 enable, updown;
5251 unsigned int bit;
5252
5253 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5254 if (!reg)
5255 return;
5256
5257 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5258 if (bias != PIN_CONFIG_BIAS_DISABLE)
5259 enable |= BIT(bit);
5260
5261 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5262 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5263 updown |= BIT(bit);
5264
5265 sh_pfc_write(pfc, reg->pud, updown);
5266 sh_pfc_write(pfc, reg->puen, enable);
5267 }
5268
5269 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
5270 .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5271 .get_bias = r8a77990_pinmux_get_bias,
5272 .set_bias = r8a77990_pinmux_set_bias,
5273 };
5274
5275 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
5276 const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5277 .name = "r8a774c0_pfc",
5278 .ops = &r8a77990_pinmux_ops,
5279 .unlock_reg = 0xe6060000,
5280
5281 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5282
5283 .pins = pinmux_pins,
5284 .nr_pins = ARRAY_SIZE(pinmux_pins),
5285 .groups = pinmux_groups.common,
5286 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5287 .functions = pinmux_functions.common,
5288 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5289
5290 .cfg_regs = pinmux_config_regs,
5291 .bias_regs = pinmux_bias_regs,
5292 .ioctrl_regs = pinmux_ioctrl_regs,
5293
5294 .pinmux_data = pinmux_data,
5295 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5296 };
5297 #endif
5298
5299 #ifdef CONFIG_PINCTRL_PFC_R8A77990
5300 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5301 .name = "r8a77990_pfc",
5302 .ops = &r8a77990_pinmux_ops,
5303 .unlock_reg = 0xe6060000,
5304
5305 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5306
5307 .pins = pinmux_pins,
5308 .nr_pins = ARRAY_SIZE(pinmux_pins),
5309 .groups = pinmux_groups.common,
5310 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5311 ARRAY_SIZE(pinmux_groups.automotive),
5312 .functions = pinmux_functions.common,
5313 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5314 ARRAY_SIZE(pinmux_functions.automotive),
5315
5316 .cfg_regs = pinmux_config_regs,
5317 .bias_regs = pinmux_bias_regs,
5318 .ioctrl_regs = pinmux_ioctrl_regs,
5319
5320 .pinmux_data = pinmux_data,
5321 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5322 };
5323 #endif