This source file includes following definitions.
- pctl_readl
- pctl_writel
- irqd_to_bank
- gpio_readl
- gpio_writel
- gpio_mask_writel
- gpio_enable
- gpio_disable
- pistachio_pinctrl_get_groups_count
- pistachio_pinctrl_get_group_name
- pistachio_pinctrl_get_group_pins
- pistachio_pinmux_get_functions_count
- pistachio_pinmux_get_function_name
- pistachio_pinmux_get_function_groups
- pistachio_pinmux_enable
- pistachio_pinconf_get
- pistachio_pinconf_set
- pistachio_gpio_get_direction
- pistachio_gpio_get
- pistachio_gpio_set
- pistachio_gpio_direction_input
- pistachio_gpio_direction_output
- pistachio_gpio_irq_ack
- pistachio_gpio_irq_mask
- pistachio_gpio_irq_unmask
- pistachio_gpio_irq_startup
- pistachio_gpio_irq_set_type
- pistachio_gpio_irq_handler
- pistachio_gpio_register
- pistachio_pinctrl_probe
- pistachio_pinctrl_register
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9 #include <linux/gpio/driver.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/irq.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22
23 #include "pinctrl-utils.h"
24
25 #define PADS_SCHMITT_EN0 0x000
26 #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
27 #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32)
28
29 #define PADS_PU_PD0 0x040
30 #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16))
31 #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16))
32 #define PADS_PU_PD_MASK 0x3
33 #define PADS_PU_PD_HIGHZ 0x0
34 #define PADS_PU_PD_UP 0x1
35 #define PADS_PU_PD_DOWN 0x2
36 #define PADS_PU_PD_BUS 0x3
37
38 #define PADS_FUNCTION_SELECT0 0x0c0
39 #define PADS_FUNCTION_SELECT1 0x0c4
40 #define PADS_FUNCTION_SELECT2 0x0c8
41 #define PADS_SCENARIO_SELECT 0x0f8
42
43 #define PADS_SLEW_RATE0 0x100
44 #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
45 #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32)
46
47 #define PADS_DRIVE_STRENGTH0 0x120
48 #define PADS_DRIVE_STRENGTH_REG(pin) \
49 (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
50 #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16))
51 #define PADS_DRIVE_STRENGTH_MASK 0x3
52 #define PADS_DRIVE_STRENGTH_2MA 0x0
53 #define PADS_DRIVE_STRENGTH_4MA 0x1
54 #define PADS_DRIVE_STRENGTH_8MA 0x2
55 #define PADS_DRIVE_STRENGTH_12MA 0x3
56
57 #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
58
59 #define GPIO_BIT_EN 0x00
60 #define GPIO_OUTPUT_EN 0x04
61 #define GPIO_OUTPUT 0x08
62 #define GPIO_INPUT 0x0c
63 #define GPIO_INPUT_POLARITY 0x10
64 #define GPIO_INTERRUPT_TYPE 0x14
65 #define GPIO_INTERRUPT_TYPE_LEVEL 0x0
66 #define GPIO_INTERRUPT_TYPE_EDGE 0x1
67 #define GPIO_INTERRUPT_EDGE 0x18
68 #define GPIO_INTERRUPT_EDGE_SINGLE 0x0
69 #define GPIO_INTERRUPT_EDGE_DUAL 0x1
70 #define GPIO_INTERRUPT_EN 0x1c
71 #define GPIO_INTERRUPT_STATUS 0x20
72
73 struct pistachio_function {
74 const char *name;
75 const char * const *groups;
76 unsigned int ngroups;
77 const int *scenarios;
78 unsigned int nscenarios;
79 unsigned int scenario_reg;
80 unsigned int scenario_shift;
81 unsigned int scenario_mask;
82 };
83
84 struct pistachio_pin_group {
85 const char *name;
86 unsigned int pin;
87 int mux_option[3];
88 int mux_reg;
89 int mux_shift;
90 int mux_mask;
91 };
92
93 struct pistachio_gpio_bank {
94 struct pistachio_pinctrl *pctl;
95 void __iomem *base;
96 unsigned int pin_base;
97 unsigned int npins;
98 struct gpio_chip gpio_chip;
99 struct irq_chip irq_chip;
100 };
101
102 struct pistachio_pinctrl {
103 struct device *dev;
104 void __iomem *base;
105 struct pinctrl_dev *pctldev;
106 const struct pinctrl_pin_desc *pins;
107 unsigned int npins;
108 const struct pistachio_function *functions;
109 unsigned int nfunctions;
110 const struct pistachio_pin_group *groups;
111 unsigned int ngroups;
112 struct pistachio_gpio_bank *gpio_banks;
113 unsigned int nbanks;
114 };
115
116 #define PISTACHIO_PIN_MFIO(p) (p)
117 #define PISTACHIO_PIN_TCK 90
118 #define PISTACHIO_PIN_TRSTN 91
119 #define PISTACHIO_PIN_TDI 92
120 #define PISTACHIO_PIN_TMS 93
121 #define PISTACHIO_PIN_TDO 94
122 #define PISTACHIO_PIN_JTAG_COMPLY 95
123 #define PISTACHIO_PIN_SAFE_MODE 96
124 #define PISTACHIO_PIN_POR_DISABLE 97
125 #define PISTACHIO_PIN_RESETN 98
126
127 #define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p)
128
129 static const struct pinctrl_pin_desc pistachio_pins[] = {
130 MFIO_PIN_DESC(0),
131 MFIO_PIN_DESC(1),
132 MFIO_PIN_DESC(2),
133 MFIO_PIN_DESC(3),
134 MFIO_PIN_DESC(4),
135 MFIO_PIN_DESC(5),
136 MFIO_PIN_DESC(6),
137 MFIO_PIN_DESC(7),
138 MFIO_PIN_DESC(8),
139 MFIO_PIN_DESC(9),
140 MFIO_PIN_DESC(10),
141 MFIO_PIN_DESC(11),
142 MFIO_PIN_DESC(12),
143 MFIO_PIN_DESC(13),
144 MFIO_PIN_DESC(14),
145 MFIO_PIN_DESC(15),
146 MFIO_PIN_DESC(16),
147 MFIO_PIN_DESC(17),
148 MFIO_PIN_DESC(18),
149 MFIO_PIN_DESC(19),
150 MFIO_PIN_DESC(20),
151 MFIO_PIN_DESC(21),
152 MFIO_PIN_DESC(22),
153 MFIO_PIN_DESC(23),
154 MFIO_PIN_DESC(24),
155 MFIO_PIN_DESC(25),
156 MFIO_PIN_DESC(26),
157 MFIO_PIN_DESC(27),
158 MFIO_PIN_DESC(28),
159 MFIO_PIN_DESC(29),
160 MFIO_PIN_DESC(30),
161 MFIO_PIN_DESC(31),
162 MFIO_PIN_DESC(32),
163 MFIO_PIN_DESC(33),
164 MFIO_PIN_DESC(34),
165 MFIO_PIN_DESC(35),
166 MFIO_PIN_DESC(36),
167 MFIO_PIN_DESC(37),
168 MFIO_PIN_DESC(38),
169 MFIO_PIN_DESC(39),
170 MFIO_PIN_DESC(40),
171 MFIO_PIN_DESC(41),
172 MFIO_PIN_DESC(42),
173 MFIO_PIN_DESC(43),
174 MFIO_PIN_DESC(44),
175 MFIO_PIN_DESC(45),
176 MFIO_PIN_DESC(46),
177 MFIO_PIN_DESC(47),
178 MFIO_PIN_DESC(48),
179 MFIO_PIN_DESC(49),
180 MFIO_PIN_DESC(50),
181 MFIO_PIN_DESC(51),
182 MFIO_PIN_DESC(52),
183 MFIO_PIN_DESC(53),
184 MFIO_PIN_DESC(54),
185 MFIO_PIN_DESC(55),
186 MFIO_PIN_DESC(56),
187 MFIO_PIN_DESC(57),
188 MFIO_PIN_DESC(58),
189 MFIO_PIN_DESC(59),
190 MFIO_PIN_DESC(60),
191 MFIO_PIN_DESC(61),
192 MFIO_PIN_DESC(62),
193 MFIO_PIN_DESC(63),
194 MFIO_PIN_DESC(64),
195 MFIO_PIN_DESC(65),
196 MFIO_PIN_DESC(66),
197 MFIO_PIN_DESC(67),
198 MFIO_PIN_DESC(68),
199 MFIO_PIN_DESC(69),
200 MFIO_PIN_DESC(70),
201 MFIO_PIN_DESC(71),
202 MFIO_PIN_DESC(72),
203 MFIO_PIN_DESC(73),
204 MFIO_PIN_DESC(74),
205 MFIO_PIN_DESC(75),
206 MFIO_PIN_DESC(76),
207 MFIO_PIN_DESC(77),
208 MFIO_PIN_DESC(78),
209 MFIO_PIN_DESC(79),
210 MFIO_PIN_DESC(80),
211 MFIO_PIN_DESC(81),
212 MFIO_PIN_DESC(82),
213 MFIO_PIN_DESC(83),
214 MFIO_PIN_DESC(84),
215 MFIO_PIN_DESC(85),
216 MFIO_PIN_DESC(86),
217 MFIO_PIN_DESC(87),
218 MFIO_PIN_DESC(88),
219 MFIO_PIN_DESC(89),
220 PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"),
221 PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"),
222 PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"),
223 PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"),
224 PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"),
225 PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"),
226 PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"),
227 PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"),
228 PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"),
229 };
230
231 static const char * const pistachio_spim0_groups[] = {
232 "mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29",
233 "mfio30", "mfio55", "mfio56", "mfio57",
234 };
235
236 static const char * const pistachio_spim1_groups[] = {
237 "mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6",
238 "mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58",
239 };
240
241 static const char * const pistachio_spis_groups[] = {
242 "mfio11", "mfio12", "mfio13", "mfio14",
243 };
244
245 static const char *const pistachio_sdhost_groups[] = {
246 "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
247 "mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26",
248 "mfio27",
249 };
250
251 static const char * const pistachio_i2c0_groups[] = {
252 "mfio28", "mfio29",
253 };
254
255 static const char * const pistachio_i2c1_groups[] = {
256 "mfio30", "mfio31",
257 };
258
259 static const char * const pistachio_i2c2_groups[] = {
260 "mfio32", "mfio33",
261 };
262
263 static const char * const pistachio_i2c3_groups[] = {
264 "mfio34", "mfio35",
265 };
266
267 static const char * const pistachio_audio_clk_in_groups[] = {
268 "mfio36",
269 };
270
271 static const char * const pistachio_i2s_out_groups[] = {
272 "mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41",
273 "mfio42", "mfio43", "mfio44",
274 };
275
276 static const char * const pistachio_debug_raw_cca_ind_groups[] = {
277 "mfio37",
278 };
279
280 static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = {
281 "mfio38",
282 };
283
284 static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = {
285 "mfio39",
286 };
287
288 static const char * const pistachio_debug_agc_done_0_groups[] = {
289 "mfio40",
290 };
291
292 static const char * const pistachio_debug_agc_done_1_groups[] = {
293 "mfio41",
294 };
295
296 static const char * const pistachio_debug_ed_cca_ind_groups[] = {
297 "mfio42",
298 };
299
300 static const char * const pistachio_debug_s2l_done_groups[] = {
301 "mfio43",
302 };
303
304 static const char * const pistachio_i2s_dac_clk_groups[] = {
305 "mfio45",
306 };
307
308 static const char * const pistachio_audio_sync_groups[] = {
309 "mfio45",
310 };
311
312 static const char * const pistachio_audio_trigger_groups[] = {
313 "mfio46",
314 };
315
316 static const char * const pistachio_i2s_in_groups[] = {
317 "mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52",
318 "mfio53", "mfio54",
319 };
320
321 static const char * const pistachio_uart0_groups[] = {
322 "mfio55", "mfio56", "mfio57", "mfio58",
323 };
324
325 static const char * const pistachio_uart1_groups[] = {
326 "mfio59", "mfio60", "mfio1", "mfio2",
327 };
328
329 static const char * const pistachio_spdif_out_groups[] = {
330 "mfio61",
331 };
332
333 static const char * const pistachio_spdif_in_groups[] = {
334 "mfio62", "mfio54",
335 };
336 static const int pistachio_spdif_in_scenarios[] = {
337 PISTACHIO_PIN_MFIO(62),
338 PISTACHIO_PIN_MFIO(54),
339 };
340
341 static const char * const pistachio_eth_groups[] = {
342 "mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68",
343 "mfio69", "mfio70", "mfio71",
344 };
345
346 static const char * const pistachio_ir_groups[] = {
347 "mfio72",
348 };
349
350 static const char * const pistachio_pwmpdm_groups[] = {
351 "mfio73", "mfio74", "mfio75", "mfio76",
352 };
353
354 static const char * const pistachio_mips_trace_clk_groups[] = {
355 "mfio15", "mfio63", "mfio73",
356 };
357
358 static const char * const pistachio_mips_trace_dint_groups[] = {
359 "mfio16", "mfio64", "mfio74",
360 };
361 static const int pistachio_mips_trace_dint_scenarios[] = {
362 PISTACHIO_PIN_MFIO(16),
363 PISTACHIO_PIN_MFIO(64),
364 PISTACHIO_PIN_MFIO(74),
365 };
366
367 static const char * const pistachio_mips_trace_trigout_groups[] = {
368 "mfio17", "mfio65", "mfio75",
369 };
370
371 static const char * const pistachio_mips_trace_trigin_groups[] = {
372 "mfio18", "mfio66", "mfio76",
373 };
374 static const int pistachio_mips_trace_trigin_scenarios[] = {
375 PISTACHIO_PIN_MFIO(18),
376 PISTACHIO_PIN_MFIO(66),
377 PISTACHIO_PIN_MFIO(76),
378 };
379
380 static const char * const pistachio_mips_trace_dm_groups[] = {
381 "mfio19", "mfio67", "mfio77",
382 };
383
384 static const char * const pistachio_mips_probe_n_groups[] = {
385 "mfio20", "mfio68", "mfio78",
386 };
387 static const int pistachio_mips_probe_n_scenarios[] = {
388 PISTACHIO_PIN_MFIO(20),
389 PISTACHIO_PIN_MFIO(68),
390 PISTACHIO_PIN_MFIO(78),
391 };
392
393 static const char * const pistachio_mips_trace_data_groups[] = {
394 "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
395 "mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66",
396 "mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80",
397 "mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86",
398 };
399
400 static const char * const pistachio_sram_debug_groups[] = {
401 "mfio73", "mfio74",
402 };
403
404 static const char * const pistachio_rom_debug_groups[] = {
405 "mfio75", "mfio76",
406 };
407
408 static const char * const pistachio_rpu_debug_groups[] = {
409 "mfio77", "mfio78",
410 };
411
412 static const char * const pistachio_mips_debug_groups[] = {
413 "mfio79", "mfio80",
414 };
415
416 static const char * const pistachio_eth_debug_groups[] = {
417 "mfio81", "mfio82",
418 };
419
420 static const char * const pistachio_usb_debug_groups[] = {
421 "mfio83", "mfio84",
422 };
423
424 static const char * const pistachio_sdhost_debug_groups[] = {
425 "mfio85", "mfio86",
426 };
427
428 static const char * const pistachio_socif_debug_groups[] = {
429 "mfio87", "mfio88",
430 };
431
432 static const char * const pistachio_mdc_debug_groups[] = {
433 "mfio77", "mfio78",
434 };
435
436 static const char * const pistachio_ddr_debug_groups[] = {
437 "mfio79", "mfio80",
438 };
439
440 static const char * const pistachio_dreq0_groups[] = {
441 "mfio81",
442 };
443
444 static const char * const pistachio_dreq1_groups[] = {
445 "mfio82",
446 };
447
448 static const char * const pistachio_dreq2_groups[] = {
449 "mfio87",
450 };
451
452 static const char * const pistachio_dreq3_groups[] = {
453 "mfio88",
454 };
455
456 static const char * const pistachio_dreq4_groups[] = {
457 "mfio89",
458 };
459
460 static const char * const pistachio_dreq5_groups[] = {
461 "mfio89",
462 };
463
464 static const char * const pistachio_mips_pll_lock_groups[] = {
465 "mfio83",
466 };
467
468 static const char * const pistachio_audio_pll_lock_groups[] = {
469 "mfio84",
470 };
471
472 static const char * const pistachio_rpu_v_pll_lock_groups[] = {
473 "mfio85",
474 };
475
476 static const char * const pistachio_rpu_l_pll_lock_groups[] = {
477 "mfio86",
478 };
479
480 static const char * const pistachio_sys_pll_lock_groups[] = {
481 "mfio87",
482 };
483
484 static const char * const pistachio_wifi_pll_lock_groups[] = {
485 "mfio88",
486 };
487
488 static const char * const pistachio_bt_pll_lock_groups[] = {
489 "mfio89",
490 };
491
492 #define FUNCTION(_name) \
493 { \
494 .name = #_name, \
495 .groups = pistachio_##_name##_groups, \
496 .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
497 }
498
499 #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \
500 { \
501 .name = #_name, \
502 .groups = pistachio_##_name##_groups, \
503 .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
504 .scenarios = pistachio_##_name##_scenarios, \
505 .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\
506 .scenario_reg = _reg, \
507 .scenario_shift = _shift, \
508 .scenario_mask = _mask, \
509 }
510
511 enum pistachio_mux_option {
512 PISTACHIO_FUNCTION_NONE = -1,
513 PISTACHIO_FUNCTION_SPIM0,
514 PISTACHIO_FUNCTION_SPIM1,
515 PISTACHIO_FUNCTION_SPIS,
516 PISTACHIO_FUNCTION_SDHOST,
517 PISTACHIO_FUNCTION_I2C0,
518 PISTACHIO_FUNCTION_I2C1,
519 PISTACHIO_FUNCTION_I2C2,
520 PISTACHIO_FUNCTION_I2C3,
521 PISTACHIO_FUNCTION_AUDIO_CLK_IN,
522 PISTACHIO_FUNCTION_I2S_OUT,
523 PISTACHIO_FUNCTION_I2S_DAC_CLK,
524 PISTACHIO_FUNCTION_AUDIO_SYNC,
525 PISTACHIO_FUNCTION_AUDIO_TRIGGER,
526 PISTACHIO_FUNCTION_I2S_IN,
527 PISTACHIO_FUNCTION_UART0,
528 PISTACHIO_FUNCTION_UART1,
529 PISTACHIO_FUNCTION_SPDIF_OUT,
530 PISTACHIO_FUNCTION_SPDIF_IN,
531 PISTACHIO_FUNCTION_ETH,
532 PISTACHIO_FUNCTION_IR,
533 PISTACHIO_FUNCTION_PWMPDM,
534 PISTACHIO_FUNCTION_MIPS_TRACE_CLK,
535 PISTACHIO_FUNCTION_MIPS_TRACE_DINT,
536 PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT,
537 PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN,
538 PISTACHIO_FUNCTION_MIPS_TRACE_DM,
539 PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N,
540 PISTACHIO_FUNCTION_MIPS_TRACE_DATA,
541 PISTACHIO_FUNCTION_SRAM_DEBUG,
542 PISTACHIO_FUNCTION_ROM_DEBUG,
543 PISTACHIO_FUNCTION_RPU_DEBUG,
544 PISTACHIO_FUNCTION_MIPS_DEBUG,
545 PISTACHIO_FUNCTION_ETH_DEBUG,
546 PISTACHIO_FUNCTION_USB_DEBUG,
547 PISTACHIO_FUNCTION_SDHOST_DEBUG,
548 PISTACHIO_FUNCTION_SOCIF_DEBUG,
549 PISTACHIO_FUNCTION_MDC_DEBUG,
550 PISTACHIO_FUNCTION_DDR_DEBUG,
551 PISTACHIO_FUNCTION_DREQ0,
552 PISTACHIO_FUNCTION_DREQ1,
553 PISTACHIO_FUNCTION_DREQ2,
554 PISTACHIO_FUNCTION_DREQ3,
555 PISTACHIO_FUNCTION_DREQ4,
556 PISTACHIO_FUNCTION_DREQ5,
557 PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
558 PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
559 PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
560 PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
561 PISTACHIO_FUNCTION_SYS_PLL_LOCK,
562 PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
563 PISTACHIO_FUNCTION_BT_PLL_LOCK,
564 PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
565 PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
566 PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
567 PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0,
568 PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1,
569 PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND,
570 PISTACHIO_FUNCTION_DEBUG_S2L_DONE,
571 };
572
573 static const struct pistachio_function pistachio_functions[] = {
574 FUNCTION(spim0),
575 FUNCTION(spim1),
576 FUNCTION(spis),
577 FUNCTION(sdhost),
578 FUNCTION(i2c0),
579 FUNCTION(i2c1),
580 FUNCTION(i2c2),
581 FUNCTION(i2c3),
582 FUNCTION(audio_clk_in),
583 FUNCTION(i2s_out),
584 FUNCTION(i2s_dac_clk),
585 FUNCTION(audio_sync),
586 FUNCTION(audio_trigger),
587 FUNCTION(i2s_in),
588 FUNCTION(uart0),
589 FUNCTION(uart1),
590 FUNCTION(spdif_out),
591 FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1),
592 FUNCTION(eth),
593 FUNCTION(ir),
594 FUNCTION(pwmpdm),
595 FUNCTION(mips_trace_clk),
596 FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3),
597 FUNCTION(mips_trace_trigout),
598 FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3),
599 FUNCTION(mips_trace_dm),
600 FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3),
601 FUNCTION(mips_trace_data),
602 FUNCTION(sram_debug),
603 FUNCTION(rom_debug),
604 FUNCTION(rpu_debug),
605 FUNCTION(mips_debug),
606 FUNCTION(eth_debug),
607 FUNCTION(usb_debug),
608 FUNCTION(sdhost_debug),
609 FUNCTION(socif_debug),
610 FUNCTION(mdc_debug),
611 FUNCTION(ddr_debug),
612 FUNCTION(dreq0),
613 FUNCTION(dreq1),
614 FUNCTION(dreq2),
615 FUNCTION(dreq3),
616 FUNCTION(dreq4),
617 FUNCTION(dreq5),
618 FUNCTION(mips_pll_lock),
619 FUNCTION(audio_pll_lock),
620 FUNCTION(rpu_v_pll_lock),
621 FUNCTION(rpu_l_pll_lock),
622 FUNCTION(sys_pll_lock),
623 FUNCTION(wifi_pll_lock),
624 FUNCTION(bt_pll_lock),
625 FUNCTION(debug_raw_cca_ind),
626 FUNCTION(debug_ed_sec20_cca_ind),
627 FUNCTION(debug_ed_sec40_cca_ind),
628 FUNCTION(debug_agc_done_0),
629 FUNCTION(debug_agc_done_1),
630 FUNCTION(debug_ed_cca_ind),
631 FUNCTION(debug_s2l_done),
632 };
633
634 #define PIN_GROUP(_pin, _name) \
635 { \
636 .name = #_name, \
637 .pin = PISTACHIO_PIN_##_pin, \
638 .mux_option = { \
639 PISTACHIO_FUNCTION_NONE, \
640 PISTACHIO_FUNCTION_NONE, \
641 PISTACHIO_FUNCTION_NONE, \
642 }, \
643 .mux_reg = -1, \
644 .mux_shift = -1, \
645 .mux_mask = -1, \
646 }
647
648 #define MFIO_PIN_GROUP(_pin, _func) \
649 { \
650 .name = "mfio" #_pin, \
651 .pin = PISTACHIO_PIN_MFIO(_pin), \
652 .mux_option = { \
653 PISTACHIO_FUNCTION_##_func, \
654 PISTACHIO_FUNCTION_NONE, \
655 PISTACHIO_FUNCTION_NONE, \
656 }, \
657 .mux_reg = -1, \
658 .mux_shift = -1, \
659 .mux_mask = -1, \
660 }
661
662 #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \
663 { \
664 .name = "mfio" #_pin, \
665 .pin = PISTACHIO_PIN_MFIO(_pin), \
666 .mux_option = { \
667 PISTACHIO_FUNCTION_##_f0, \
668 PISTACHIO_FUNCTION_##_f1, \
669 PISTACHIO_FUNCTION_##_f2, \
670 }, \
671 .mux_reg = _reg, \
672 .mux_shift = _shift, \
673 .mux_mask = _mask, \
674 }
675
676 static const struct pistachio_pin_group pistachio_groups[] = {
677 MFIO_PIN_GROUP(0, SPIM1),
678 MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1,
679 PADS_FUNCTION_SELECT0, 0, 0x3),
680 MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1,
681 PADS_FUNCTION_SELECT0, 2, 0x3),
682 MFIO_PIN_GROUP(3, SPIM1),
683 MFIO_PIN_GROUP(4, SPIM1),
684 MFIO_PIN_GROUP(5, SPIM1),
685 MFIO_PIN_GROUP(6, SPIM1),
686 MFIO_PIN_GROUP(7, SPIM1),
687 MFIO_PIN_GROUP(8, SPIM0),
688 MFIO_PIN_GROUP(9, SPIM0),
689 MFIO_PIN_GROUP(10, SPIM0),
690 MFIO_PIN_GROUP(11, SPIS),
691 MFIO_PIN_GROUP(12, SPIS),
692 MFIO_PIN_GROUP(13, SPIS),
693 MFIO_PIN_GROUP(14, SPIS),
694 MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
695 PADS_FUNCTION_SELECT0, 4, 0x3),
696 MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
697 PADS_FUNCTION_SELECT0, 6, 0x3),
698 MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
699 PADS_FUNCTION_SELECT0, 8, 0x3),
700 MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
701 PADS_FUNCTION_SELECT0, 10, 0x3),
702 MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA,
703 PADS_FUNCTION_SELECT0, 12, 0x3),
704 MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
705 PADS_FUNCTION_SELECT0, 14, 0x3),
706 MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA,
707 PADS_FUNCTION_SELECT0, 16, 0x3),
708 MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA,
709 PADS_FUNCTION_SELECT0, 18, 0x3),
710 MFIO_PIN_GROUP(23, SDHOST),
711 MFIO_PIN_GROUP(24, SDHOST),
712 MFIO_PIN_GROUP(25, SDHOST),
713 MFIO_PIN_GROUP(26, SDHOST),
714 MFIO_PIN_GROUP(27, SDHOST),
715 MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE,
716 PADS_FUNCTION_SELECT0, 20, 0x1),
717 MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE,
718 PADS_FUNCTION_SELECT0, 21, 0x1),
719 MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE,
720 PADS_FUNCTION_SELECT0, 22, 0x1),
721 MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE,
722 PADS_FUNCTION_SELECT0, 23, 0x1),
723 MFIO_PIN_GROUP(32, I2C2),
724 MFIO_PIN_GROUP(33, I2C2),
725 MFIO_PIN_GROUP(34, I2C3),
726 MFIO_PIN_GROUP(35, I2C3),
727 MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE,
728 PADS_FUNCTION_SELECT0, 24, 0x1),
729 MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE,
730 PADS_FUNCTION_SELECT0, 25, 0x1),
731 MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE,
732 PADS_FUNCTION_SELECT0, 26, 0x1),
733 MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE,
734 PADS_FUNCTION_SELECT0, 27, 0x1),
735 MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE,
736 PADS_FUNCTION_SELECT0, 28, 0x1),
737 MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE,
738 PADS_FUNCTION_SELECT0, 29, 0x1),
739 MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE,
740 PADS_FUNCTION_SELECT0, 30, 0x1),
741 MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE,
742 PADS_FUNCTION_SELECT0, 31, 0x1),
743 MFIO_PIN_GROUP(44, I2S_OUT),
744 MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE,
745 PADS_FUNCTION_SELECT1, 0, 0x1),
746 MFIO_PIN_GROUP(46, AUDIO_TRIGGER),
747 MFIO_PIN_GROUP(47, I2S_IN),
748 MFIO_PIN_GROUP(48, I2S_IN),
749 MFIO_PIN_GROUP(49, I2S_IN),
750 MFIO_PIN_GROUP(50, I2S_IN),
751 MFIO_PIN_GROUP(51, I2S_IN),
752 MFIO_PIN_GROUP(52, I2S_IN),
753 MFIO_PIN_GROUP(53, I2S_IN),
754 MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN,
755 PADS_FUNCTION_SELECT1, 1, 0x3),
756 MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1,
757 PADS_FUNCTION_SELECT1, 3, 0x3),
758 MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1,
759 PADS_FUNCTION_SELECT1, 5, 0x3),
760 MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1,
761 PADS_FUNCTION_SELECT1, 7, 0x3),
762 MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE,
763 PADS_FUNCTION_SELECT1, 9, 0x1),
764 MFIO_PIN_GROUP(59, UART1),
765 MFIO_PIN_GROUP(60, UART1),
766 MFIO_PIN_GROUP(61, SPDIF_OUT),
767 MFIO_PIN_GROUP(62, SPDIF_IN),
768 MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
769 PADS_FUNCTION_SELECT1, 10, 0x3),
770 MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
771 PADS_FUNCTION_SELECT1, 12, 0x3),
772 MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
773 PADS_FUNCTION_SELECT1, 14, 0x3),
774 MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
775 PADS_FUNCTION_SELECT1, 16, 0x3),
776 MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA,
777 PADS_FUNCTION_SELECT1, 18, 0x3),
778 MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
779 PADS_FUNCTION_SELECT1, 20, 0x3),
780 MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA,
781 PADS_FUNCTION_SELECT1, 22, 0x3),
782 MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA,
783 PADS_FUNCTION_SELECT1, 24, 0x3),
784 MFIO_PIN_GROUP(71, ETH),
785 MFIO_PIN_GROUP(72, IR),
786 MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG,
787 PADS_FUNCTION_SELECT1, 26, 0x3),
788 MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG,
789 PADS_FUNCTION_SELECT1, 28, 0x3),
790 MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG,
791 PADS_FUNCTION_SELECT1, 30, 0x3),
792 MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG,
793 PADS_FUNCTION_SELECT2, 0, 0x3),
794 MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG,
795 PADS_FUNCTION_SELECT2, 2, 0x3),
796 MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG,
797 PADS_FUNCTION_SELECT2, 4, 0x3),
798 MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
799 PADS_FUNCTION_SELECT2, 6, 0x3),
800 MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
801 PADS_FUNCTION_SELECT2, 8, 0x3),
802 MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG,
803 PADS_FUNCTION_SELECT2, 10, 0x3),
804 MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG,
805 PADS_FUNCTION_SELECT2, 12, 0x3),
806 MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
807 PADS_FUNCTION_SELECT2, 14, 0x3),
808 MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
809 PADS_FUNCTION_SELECT2, 16, 0x3),
810 MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
811 PADS_FUNCTION_SELECT2, 18, 0x3),
812 MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
813 PADS_FUNCTION_SELECT2, 20, 0x3),
814 MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG,
815 PADS_FUNCTION_SELECT2, 22, 0x3),
816 MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG,
817 PADS_FUNCTION_SELECT2, 24, 0x3),
818 MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5,
819 PADS_FUNCTION_SELECT2, 26, 0x3),
820 PIN_GROUP(TCK, "tck"),
821 PIN_GROUP(TRSTN, "trstn"),
822 PIN_GROUP(TDI, "tdi"),
823 PIN_GROUP(TMS, "tms"),
824 PIN_GROUP(TDO, "tdo"),
825 PIN_GROUP(JTAG_COMPLY, "jtag_comply"),
826 PIN_GROUP(SAFE_MODE, "safe_mode"),
827 PIN_GROUP(POR_DISABLE, "por_disable"),
828 PIN_GROUP(RESETN, "resetn"),
829 };
830
831 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
832 {
833 return readl(pctl->base + reg);
834 }
835
836 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
837 {
838 writel(val, pctl->base + reg);
839 }
840
841 static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d)
842 {
843 return gpiochip_get_data(irq_data_get_irq_chip_data(d));
844 }
845
846 static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
847 {
848 return readl(bank->base + reg);
849 }
850
851 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
852 u32 reg)
853 {
854 writel(val, bank->base + reg);
855 }
856
857 static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
858 u32 reg, unsigned int bit, u32 val)
859 {
860
861
862
863
864 gpio_writel(bank, (0x10000 | val) << bit, reg);
865 }
866
867 static inline void gpio_enable(struct pistachio_gpio_bank *bank,
868 unsigned offset)
869 {
870 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
871 }
872
873 static inline void gpio_disable(struct pistachio_gpio_bank *bank,
874 unsigned offset)
875 {
876 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
877 }
878
879 static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
880 {
881 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
882
883 return pctl->ngroups;
884 }
885
886 static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
887 unsigned group)
888 {
889 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
890
891 return pctl->groups[group].name;
892 }
893
894 static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
895 unsigned group,
896 const unsigned **pins,
897 unsigned *num_pins)
898 {
899 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
900
901 *pins = &pctl->groups[group].pin;
902 *num_pins = 1;
903
904 return 0;
905 }
906
907 static const struct pinctrl_ops pistachio_pinctrl_ops = {
908 .get_groups_count = pistachio_pinctrl_get_groups_count,
909 .get_group_name = pistachio_pinctrl_get_group_name,
910 .get_group_pins = pistachio_pinctrl_get_group_pins,
911 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
912 .dt_free_map = pinctrl_utils_free_map,
913 };
914
915 static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
916 {
917 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
918
919 return pctl->nfunctions;
920 }
921
922 static const char *
923 pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
924 {
925 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
926
927 return pctl->functions[func].name;
928 }
929
930 static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
931 unsigned func,
932 const char * const **groups,
933 unsigned * const num_groups)
934 {
935 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
936
937 *groups = pctl->functions[func].groups;
938 *num_groups = pctl->functions[func].ngroups;
939
940 return 0;
941 }
942
943 static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
944 unsigned func, unsigned group)
945 {
946 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
947 const struct pistachio_pin_group *pg = &pctl->groups[group];
948 const struct pistachio_function *pf = &pctl->functions[func];
949 struct pinctrl_gpio_range *range;
950 unsigned int i;
951 u32 val;
952
953 if (pg->mux_reg > 0) {
954 for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {
955 if (pg->mux_option[i] == func)
956 break;
957 }
958 if (i == ARRAY_SIZE(pg->mux_option)) {
959 dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
960 group, func);
961 return -EINVAL;
962 }
963
964 val = pctl_readl(pctl, pg->mux_reg);
965 val &= ~(pg->mux_mask << pg->mux_shift);
966 val |= i << pg->mux_shift;
967 pctl_writel(pctl, val, pg->mux_reg);
968
969 if (pf->scenarios) {
970 for (i = 0; i < pf->nscenarios; i++) {
971 if (pf->scenarios[i] == group)
972 break;
973 }
974 if (WARN_ON(i == pf->nscenarios))
975 return -EINVAL;
976
977 val = pctl_readl(pctl, pf->scenario_reg);
978 val &= ~(pf->scenario_mask << pf->scenario_shift);
979 val |= i << pf->scenario_shift;
980 pctl_writel(pctl, val, pf->scenario_reg);
981 }
982 }
983
984 range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
985 if (range)
986 gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);
987
988 return 0;
989 }
990
991 static const struct pinmux_ops pistachio_pinmux_ops = {
992 .get_functions_count = pistachio_pinmux_get_functions_count,
993 .get_function_name = pistachio_pinmux_get_function_name,
994 .get_function_groups = pistachio_pinmux_get_function_groups,
995 .set_mux = pistachio_pinmux_enable,
996 };
997
998 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
999 unsigned long *config)
1000 {
1001 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1002 enum pin_config_param param = pinconf_to_config_param(*config);
1003 u32 val, arg;
1004
1005 switch (param) {
1006 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1007 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1008 arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
1009 break;
1010 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1011 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1012 PADS_PU_PD_SHIFT(pin);
1013 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
1014 break;
1015 case PIN_CONFIG_BIAS_PULL_UP:
1016 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1017 PADS_PU_PD_SHIFT(pin);
1018 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
1019 break;
1020 case PIN_CONFIG_BIAS_PULL_DOWN:
1021 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1022 PADS_PU_PD_SHIFT(pin);
1023 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
1024 break;
1025 case PIN_CONFIG_BIAS_BUS_HOLD:
1026 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1027 PADS_PU_PD_SHIFT(pin);
1028 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
1029 break;
1030 case PIN_CONFIG_SLEW_RATE:
1031 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1032 arg = !!(val & PADS_SLEW_RATE_BIT(pin));
1033 break;
1034 case PIN_CONFIG_DRIVE_STRENGTH:
1035 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1036 PADS_DRIVE_STRENGTH_SHIFT(pin);
1037 switch (val & PADS_DRIVE_STRENGTH_MASK) {
1038 case PADS_DRIVE_STRENGTH_2MA:
1039 arg = 2;
1040 break;
1041 case PADS_DRIVE_STRENGTH_4MA:
1042 arg = 4;
1043 break;
1044 case PADS_DRIVE_STRENGTH_8MA:
1045 arg = 8;
1046 break;
1047 case PADS_DRIVE_STRENGTH_12MA:
1048 default:
1049 arg = 12;
1050 break;
1051 }
1052 break;
1053 default:
1054 dev_dbg(pctl->dev, "Property %u not supported\n", param);
1055 return -ENOTSUPP;
1056 }
1057
1058 *config = pinconf_to_config_packed(param, arg);
1059
1060 return 0;
1061 }
1062
1063 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1064 unsigned long *configs, unsigned num_configs)
1065 {
1066 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1067 enum pin_config_param param;
1068 u32 drv, val, arg;
1069 unsigned int i;
1070
1071 for (i = 0; i < num_configs; i++) {
1072 param = pinconf_to_config_param(configs[i]);
1073 arg = pinconf_to_config_argument(configs[i]);
1074
1075 switch (param) {
1076 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1077 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1078 if (arg)
1079 val |= PADS_SCHMITT_EN_BIT(pin);
1080 else
1081 val &= ~PADS_SCHMITT_EN_BIT(pin);
1082 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1083 break;
1084 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1085 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1086 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1087 val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
1088 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1089 break;
1090 case PIN_CONFIG_BIAS_PULL_UP:
1091 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1092 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1093 val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
1094 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1095 break;
1096 case PIN_CONFIG_BIAS_PULL_DOWN:
1097 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1098 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1099 val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
1100 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1101 break;
1102 case PIN_CONFIG_BIAS_BUS_HOLD:
1103 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1104 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1105 val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
1106 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1107 break;
1108 case PIN_CONFIG_SLEW_RATE:
1109 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1110 if (arg)
1111 val |= PADS_SLEW_RATE_BIT(pin);
1112 else
1113 val &= ~PADS_SLEW_RATE_BIT(pin);
1114 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1115 break;
1116 case PIN_CONFIG_DRIVE_STRENGTH:
1117 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1118 val &= ~(PADS_DRIVE_STRENGTH_MASK <<
1119 PADS_DRIVE_STRENGTH_SHIFT(pin));
1120 switch (arg) {
1121 case 2:
1122 drv = PADS_DRIVE_STRENGTH_2MA;
1123 break;
1124 case 4:
1125 drv = PADS_DRIVE_STRENGTH_4MA;
1126 break;
1127 case 8:
1128 drv = PADS_DRIVE_STRENGTH_8MA;
1129 break;
1130 case 12:
1131 drv = PADS_DRIVE_STRENGTH_12MA;
1132 break;
1133 default:
1134 dev_err(pctl->dev,
1135 "Drive strength %umA not supported\n",
1136 arg);
1137 return -EINVAL;
1138 }
1139 val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
1140 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
1141 break;
1142 default:
1143 dev_err(pctl->dev, "Property %u not supported\n",
1144 param);
1145 return -ENOTSUPP;
1146 }
1147 }
1148
1149 return 0;
1150 }
1151
1152 static const struct pinconf_ops pistachio_pinconf_ops = {
1153 .pin_config_get = pistachio_pinconf_get,
1154 .pin_config_set = pistachio_pinconf_set,
1155 .is_generic = true,
1156 };
1157
1158 static struct pinctrl_desc pistachio_pinctrl_desc = {
1159 .name = "pistachio-pinctrl",
1160 .pctlops = &pistachio_pinctrl_ops,
1161 .pmxops = &pistachio_pinmux_ops,
1162 .confops = &pistachio_pinconf_ops,
1163 };
1164
1165 static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1166 {
1167 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1168
1169 return !(gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset));
1170 }
1171
1172 static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
1173 {
1174 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1175 u32 reg;
1176
1177 if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1178 reg = GPIO_OUTPUT;
1179 else
1180 reg = GPIO_INPUT;
1181
1182 return !!(gpio_readl(bank, reg) & BIT(offset));
1183 }
1184
1185 static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
1186 int value)
1187 {
1188 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1189
1190 gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
1191 }
1192
1193 static int pistachio_gpio_direction_input(struct gpio_chip *chip,
1194 unsigned offset)
1195 {
1196 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1197
1198 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
1199 gpio_enable(bank, offset);
1200
1201 return 0;
1202 }
1203
1204 static int pistachio_gpio_direction_output(struct gpio_chip *chip,
1205 unsigned offset, int value)
1206 {
1207 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1208
1209 pistachio_gpio_set(chip, offset, value);
1210 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
1211 gpio_enable(bank, offset);
1212
1213 return 0;
1214 }
1215
1216 static void pistachio_gpio_irq_ack(struct irq_data *data)
1217 {
1218 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1219
1220 gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
1221 }
1222
1223 static void pistachio_gpio_irq_mask(struct irq_data *data)
1224 {
1225 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1226
1227 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
1228 }
1229
1230 static void pistachio_gpio_irq_unmask(struct irq_data *data)
1231 {
1232 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1233
1234 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
1235 }
1236
1237 static unsigned int pistachio_gpio_irq_startup(struct irq_data *data)
1238 {
1239 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1240
1241 pistachio_gpio_direction_input(chip, data->hwirq);
1242 pistachio_gpio_irq_unmask(data);
1243
1244 return 0;
1245 }
1246
1247 static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1248 {
1249 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1250
1251 switch (type & IRQ_TYPE_SENSE_MASK) {
1252 case IRQ_TYPE_EDGE_RISING:
1253 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1254 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1255 GPIO_INTERRUPT_TYPE_EDGE);
1256 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1257 GPIO_INTERRUPT_EDGE_SINGLE);
1258 break;
1259 case IRQ_TYPE_EDGE_FALLING:
1260 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1261 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1262 GPIO_INTERRUPT_TYPE_EDGE);
1263 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1264 GPIO_INTERRUPT_EDGE_SINGLE);
1265 break;
1266 case IRQ_TYPE_EDGE_BOTH:
1267 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1268 GPIO_INTERRUPT_TYPE_EDGE);
1269 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1270 GPIO_INTERRUPT_EDGE_DUAL);
1271 break;
1272 case IRQ_TYPE_LEVEL_HIGH:
1273 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1274 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1275 GPIO_INTERRUPT_TYPE_LEVEL);
1276 break;
1277 case IRQ_TYPE_LEVEL_LOW:
1278 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1279 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1280 GPIO_INTERRUPT_TYPE_LEVEL);
1281 break;
1282 default:
1283 return -EINVAL;
1284 }
1285
1286 if (type & IRQ_TYPE_LEVEL_MASK)
1287 irq_set_handler_locked(data, handle_level_irq);
1288 else
1289 irq_set_handler_locked(data, handle_edge_irq);
1290
1291 return 0;
1292 }
1293
1294 static void pistachio_gpio_irq_handler(struct irq_desc *desc)
1295 {
1296 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1297 struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);
1298 struct irq_chip *chip = irq_desc_get_chip(desc);
1299 unsigned long pending;
1300 unsigned int pin;
1301
1302 chained_irq_enter(chip, desc);
1303 pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1304 gpio_readl(bank, GPIO_INTERRUPT_EN);
1305 for_each_set_bit(pin, &pending, 16)
1306 generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
1307 chained_irq_exit(chip, desc);
1308 }
1309
1310 #define GPIO_BANK(_bank, _pin_base, _npins) \
1311 { \
1312 .pin_base = _pin_base, \
1313 .npins = _npins, \
1314 .gpio_chip = { \
1315 .label = "GPIO" #_bank, \
1316 .request = gpiochip_generic_request, \
1317 .free = gpiochip_generic_free, \
1318 .get_direction = pistachio_gpio_get_direction, \
1319 .direction_input = pistachio_gpio_direction_input, \
1320 .direction_output = pistachio_gpio_direction_output, \
1321 .get = pistachio_gpio_get, \
1322 .set = pistachio_gpio_set, \
1323 .base = _pin_base, \
1324 .ngpio = _npins, \
1325 }, \
1326 .irq_chip = { \
1327 .name = "GPIO" #_bank, \
1328 .irq_startup = pistachio_gpio_irq_startup, \
1329 .irq_ack = pistachio_gpio_irq_ack, \
1330 .irq_mask = pistachio_gpio_irq_mask, \
1331 .irq_unmask = pistachio_gpio_irq_unmask, \
1332 .irq_set_type = pistachio_gpio_irq_set_type, \
1333 }, \
1334 }
1335
1336 static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
1337 GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16),
1338 GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16),
1339 GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16),
1340 GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16),
1341 GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16),
1342 GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10),
1343 };
1344
1345 static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1346 {
1347 struct device_node *node = pctl->dev->of_node;
1348 struct pistachio_gpio_bank *bank;
1349 unsigned int i;
1350 int irq, ret = 0;
1351
1352 for (i = 0; i < pctl->nbanks; i++) {
1353 char child_name[sizeof("gpioXX")];
1354 struct device_node *child;
1355
1356 snprintf(child_name, sizeof(child_name), "gpio%d", i);
1357 child = of_get_child_by_name(node, child_name);
1358 if (!child) {
1359 dev_err(pctl->dev, "No node for bank %u\n", i);
1360 ret = -ENODEV;
1361 goto err;
1362 }
1363
1364 if (!of_find_property(child, "gpio-controller", NULL)) {
1365 dev_err(pctl->dev,
1366 "No gpio-controller property for bank %u\n", i);
1367 of_node_put(child);
1368 ret = -ENODEV;
1369 goto err;
1370 }
1371
1372 irq = irq_of_parse_and_map(child, 0);
1373 if (irq < 0) {
1374 dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
1375 of_node_put(child);
1376 ret = irq;
1377 goto err;
1378 }
1379
1380 bank = &pctl->gpio_banks[i];
1381 bank->pctl = pctl;
1382 bank->base = pctl->base + GPIO_BANK_BASE(i);
1383
1384 bank->gpio_chip.parent = pctl->dev;
1385 bank->gpio_chip.of_node = child;
1386 ret = gpiochip_add_data(&bank->gpio_chip, bank);
1387 if (ret < 0) {
1388 dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1389 i, ret);
1390 goto err;
1391 }
1392
1393 ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1394 0, handle_level_irq, IRQ_TYPE_NONE);
1395 if (ret < 0) {
1396 dev_err(pctl->dev, "Failed to add IRQ chip %u: %d\n",
1397 i, ret);
1398 gpiochip_remove(&bank->gpio_chip);
1399 goto err;
1400 }
1401 gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1402 irq, pistachio_gpio_irq_handler);
1403
1404 ret = gpiochip_add_pin_range(&bank->gpio_chip,
1405 dev_name(pctl->dev), 0,
1406 bank->pin_base, bank->npins);
1407 if (ret < 0) {
1408 dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
1409 i, ret);
1410 gpiochip_remove(&bank->gpio_chip);
1411 goto err;
1412 }
1413 }
1414
1415 return 0;
1416 err:
1417 for (; i > 0; i--) {
1418 bank = &pctl->gpio_banks[i - 1];
1419 gpiochip_remove(&bank->gpio_chip);
1420 }
1421 return ret;
1422 }
1423
1424 static const struct of_device_id pistachio_pinctrl_of_match[] = {
1425 { .compatible = "img,pistachio-system-pinctrl", },
1426 { },
1427 };
1428
1429 static int pistachio_pinctrl_probe(struct platform_device *pdev)
1430 {
1431 struct pistachio_pinctrl *pctl;
1432 struct resource *res;
1433
1434 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1435 if (!pctl)
1436 return -ENOMEM;
1437 pctl->dev = &pdev->dev;
1438 dev_set_drvdata(&pdev->dev, pctl);
1439
1440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1441 pctl->base = devm_ioremap_resource(&pdev->dev, res);
1442 if (IS_ERR(pctl->base))
1443 return PTR_ERR(pctl->base);
1444
1445 pctl->pins = pistachio_pins;
1446 pctl->npins = ARRAY_SIZE(pistachio_pins);
1447 pctl->functions = pistachio_functions;
1448 pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
1449 pctl->groups = pistachio_groups;
1450 pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1451 pctl->gpio_banks = pistachio_gpio_banks;
1452 pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1453
1454 pistachio_pinctrl_desc.pins = pctl->pins;
1455 pistachio_pinctrl_desc.npins = pctl->npins;
1456
1457 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
1458 pctl);
1459 if (IS_ERR(pctl->pctldev)) {
1460 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1461 return PTR_ERR(pctl->pctldev);
1462 }
1463
1464 return pistachio_gpio_register(pctl);
1465 }
1466
1467 static struct platform_driver pistachio_pinctrl_driver = {
1468 .driver = {
1469 .name = "pistachio-pinctrl",
1470 .of_match_table = pistachio_pinctrl_of_match,
1471 .suppress_bind_attrs = true,
1472 },
1473 .probe = pistachio_pinctrl_probe,
1474 };
1475
1476 static int __init pistachio_pinctrl_register(void)
1477 {
1478 return platform_driver_register(&pistachio_pinctrl_driver);
1479 }
1480 arch_initcall(pistachio_pinctrl_register);