This source file includes following definitions.
- reg_status
- reg_mask_status
- reg_mask_set
- reg_mask_clr
- l1_readl
- l1_writel
- bcm7038_l1_irq_handle
- __bcm7038_l1_unmask
- __bcm7038_l1_mask
- bcm7038_l1_unmask
- bcm7038_l1_mask
- bcm7038_l1_set_affinity
- bcm7038_l1_cpu_offline
- bcm7038_l1_init_one
- bcm7038_l1_map
- bcm7038_l1_of_init
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9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/bitops.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/smp.h>
27 #include <linux/types.h>
28 #include <linux/irqchip.h>
29 #include <linux/irqchip/chained_irq.h>
30
31 #define IRQS_PER_WORD 32
32 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
33 #define MAX_WORDS 8
34
35 struct bcm7038_l1_cpu;
36
37 struct bcm7038_l1_chip {
38 raw_spinlock_t lock;
39 unsigned int n_words;
40 struct irq_domain *domain;
41 struct bcm7038_l1_cpu *cpus[NR_CPUS];
42 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
43 };
44
45 struct bcm7038_l1_cpu {
46 void __iomem *map_base;
47 u32 mask_cache[0];
48 };
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74 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
75 unsigned int word)
76 {
77 return (0 * intc->n_words + word) * sizeof(u32);
78 }
79
80 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
81 unsigned int word)
82 {
83 return (1 * intc->n_words + word) * sizeof(u32);
84 }
85
86 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
87 unsigned int word)
88 {
89 return (2 * intc->n_words + word) * sizeof(u32);
90 }
91
92 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
93 unsigned int word)
94 {
95 return (3 * intc->n_words + word) * sizeof(u32);
96 }
97
98 static inline u32 l1_readl(void __iomem *reg)
99 {
100 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
101 return ioread32be(reg);
102 else
103 return readl(reg);
104 }
105
106 static inline void l1_writel(u32 val, void __iomem *reg)
107 {
108 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
109 iowrite32be(val, reg);
110 else
111 writel(val, reg);
112 }
113
114 static void bcm7038_l1_irq_handle(struct irq_desc *desc)
115 {
116 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
117 struct bcm7038_l1_cpu *cpu;
118 struct irq_chip *chip = irq_desc_get_chip(desc);
119 unsigned int idx;
120
121 #ifdef CONFIG_SMP
122 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
123 #else
124 cpu = intc->cpus[0];
125 #endif
126
127 chained_irq_enter(chip, desc);
128
129 for (idx = 0; idx < intc->n_words; idx++) {
130 int base = idx * IRQS_PER_WORD;
131 unsigned long pending, flags;
132 int hwirq;
133
134 raw_spin_lock_irqsave(&intc->lock, flags);
135 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
136 ~cpu->mask_cache[idx];
137 raw_spin_unlock_irqrestore(&intc->lock, flags);
138
139 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
140 generic_handle_irq(irq_find_mapping(intc->domain,
141 base + hwirq));
142 }
143 }
144
145 chained_irq_exit(chip, desc);
146 }
147
148 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
149 {
150 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
151 u32 word = d->hwirq / IRQS_PER_WORD;
152 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
153
154 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
155 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
156 reg_mask_clr(intc, word));
157 }
158
159 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
160 {
161 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
162 u32 word = d->hwirq / IRQS_PER_WORD;
163 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
164
165 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
166 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
167 reg_mask_set(intc, word));
168 }
169
170 static void bcm7038_l1_unmask(struct irq_data *d)
171 {
172 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
173 unsigned long flags;
174
175 raw_spin_lock_irqsave(&intc->lock, flags);
176 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
177 raw_spin_unlock_irqrestore(&intc->lock, flags);
178 }
179
180 static void bcm7038_l1_mask(struct irq_data *d)
181 {
182 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
183 unsigned long flags;
184
185 raw_spin_lock_irqsave(&intc->lock, flags);
186 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
187 raw_spin_unlock_irqrestore(&intc->lock, flags);
188 }
189
190 static int bcm7038_l1_set_affinity(struct irq_data *d,
191 const struct cpumask *dest,
192 bool force)
193 {
194 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
195 unsigned long flags;
196 irq_hw_number_t hw = d->hwirq;
197 u32 word = hw / IRQS_PER_WORD;
198 u32 mask = BIT(hw % IRQS_PER_WORD);
199 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
200 bool was_disabled;
201
202 raw_spin_lock_irqsave(&intc->lock, flags);
203
204 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
205 mask);
206 __bcm7038_l1_mask(d, intc->affinity[hw]);
207 intc->affinity[hw] = first_cpu;
208 if (!was_disabled)
209 __bcm7038_l1_unmask(d, first_cpu);
210
211 raw_spin_unlock_irqrestore(&intc->lock, flags);
212 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
213
214 return 0;
215 }
216
217 #ifdef CONFIG_SMP
218 static void bcm7038_l1_cpu_offline(struct irq_data *d)
219 {
220 struct cpumask *mask = irq_data_get_affinity_mask(d);
221 int cpu = smp_processor_id();
222 cpumask_t new_affinity;
223
224
225 if (!cpumask_test_cpu(cpu, mask))
226 return;
227
228 if (cpumask_weight(mask) > 1) {
229
230
231
232
233 cpumask_copy(&new_affinity, mask);
234 cpumask_clear_cpu(cpu, &new_affinity);
235 } else {
236
237 cpumask_clear(&new_affinity);
238 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
239 }
240 irq_set_affinity_locked(d, &new_affinity, false);
241 }
242 #endif
243
244 static int __init bcm7038_l1_init_one(struct device_node *dn,
245 unsigned int idx,
246 struct bcm7038_l1_chip *intc)
247 {
248 struct resource res;
249 resource_size_t sz;
250 struct bcm7038_l1_cpu *cpu;
251 unsigned int i, n_words, parent_irq;
252
253 if (of_address_to_resource(dn, idx, &res))
254 return -EINVAL;
255 sz = resource_size(&res);
256 n_words = sz / REG_BYTES_PER_IRQ_WORD;
257
258 if (n_words > MAX_WORDS)
259 return -EINVAL;
260 else if (!intc->n_words)
261 intc->n_words = n_words;
262 else if (intc->n_words != n_words)
263 return -EINVAL;
264
265 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
266 GFP_KERNEL);
267 if (!cpu)
268 return -ENOMEM;
269
270 cpu->map_base = ioremap(res.start, sz);
271 if (!cpu->map_base)
272 return -ENOMEM;
273
274 for (i = 0; i < n_words; i++) {
275 l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
276 cpu->mask_cache[i] = 0xffffffff;
277 }
278
279 parent_irq = irq_of_parse_and_map(dn, idx);
280 if (!parent_irq) {
281 pr_err("failed to map parent interrupt %d\n", parent_irq);
282 return -EINVAL;
283 }
284
285 if (of_property_read_bool(dn, "brcm,irq-can-wake"))
286 enable_irq_wake(parent_irq);
287
288 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
289 intc);
290
291 return 0;
292 }
293
294 static struct irq_chip bcm7038_l1_irq_chip = {
295 .name = "bcm7038-l1",
296 .irq_mask = bcm7038_l1_mask,
297 .irq_unmask = bcm7038_l1_unmask,
298 .irq_set_affinity = bcm7038_l1_set_affinity,
299 #ifdef CONFIG_SMP
300 .irq_cpu_offline = bcm7038_l1_cpu_offline,
301 #endif
302 };
303
304 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
305 irq_hw_number_t hw_irq)
306 {
307 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
308 irq_set_chip_data(virq, d->host_data);
309 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
310 return 0;
311 }
312
313 static const struct irq_domain_ops bcm7038_l1_domain_ops = {
314 .xlate = irq_domain_xlate_onecell,
315 .map = bcm7038_l1_map,
316 };
317
318 int __init bcm7038_l1_of_init(struct device_node *dn,
319 struct device_node *parent)
320 {
321 struct bcm7038_l1_chip *intc;
322 int idx, ret;
323
324 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
325 if (!intc)
326 return -ENOMEM;
327
328 raw_spin_lock_init(&intc->lock);
329 for_each_possible_cpu(idx) {
330 ret = bcm7038_l1_init_one(dn, idx, intc);
331 if (ret < 0) {
332 if (idx)
333 break;
334 pr_err("failed to remap intc L1 registers\n");
335 goto out_free;
336 }
337 }
338
339 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
340 &bcm7038_l1_domain_ops,
341 intc);
342 if (!intc->domain) {
343 ret = -ENOMEM;
344 goto out_unmap;
345 }
346
347 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
348 dn, IRQS_PER_WORD * intc->n_words);
349
350 return 0;
351
352 out_unmap:
353 for_each_possible_cpu(idx) {
354 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
355
356 if (cpu) {
357 if (cpu->map_base)
358 iounmap(cpu->map_base);
359 kfree(cpu);
360 }
361 }
362 out_free:
363 kfree(intc);
364 return ret;
365 }
366
367 IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);