1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> 4 */ 5 6 #ifndef _ALPHASCALE_ASM9260_ICOLL_H 7 #define _ALPHASCALE_ASM9260_ICOLL_H 8 9 #define ASM9260_NUM_IRQS 64 10 /* 11 * this device provide 4 offsets for each register: 12 * 0x0 - plain read write mode 13 * 0x4 - set mode, OR logic. 14 * 0x8 - clr mode, XOR logic. 15 * 0xc - togle mode. 16 */ 17 18 #define ASM9260_HW_ICOLL_VECTOR 0x0000 19 /* 20 * bits 31:2 21 * This register presents the vector address for the interrupt currently 22 * active on the CPU IRQ input. Writing to this register notifies the 23 * interrupt collector that the interrupt service routine for the current 24 * interrupt has been entered. 25 * The exception trap should have a LDPC instruction from this address: 26 * LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018 27 */ 28 29 /* 30 * The Interrupt Collector Level Acknowledge Register is used by software to 31 * indicate the completion of an interrupt on a specific level. 32 * This register is written at the very end of an interrupt service routine. If 33 * nesting is used then the CPU irq must be turned on before writing to this 34 * register to avoid a race condition in the CPU interrupt hardware. 35 */ 36 #define ASM9260_HW_ICOLL_LEVELACK 0x0010 37 #define ASM9260_BM_LEVELn(nr) BIT(nr) 38 39 #define ASM9260_HW_ICOLL_CTRL 0x0020 40 /* 41 * ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on 42 * asm9260. 43 */ 44 #define ASM9260_BM_CTRL_SFTRST BIT(31) 45 #define ASM9260_BM_CTRL_CLKGATE BIT(30) 46 /* disable interrupt level nesting */ 47 #define ASM9260_BM_CTRL_NO_NESTING BIT(19) 48 /* 49 * Set this bit to one enable the RISC32-style read side effect associated with 50 * the vector address register. In this mode, interrupt in-service is signaled 51 * by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt 52 * vector address. Set this bit to zero for normal operation, in which the ISR 53 * signals in-service explicitly by means of a write to the 54 * ASM9260_HW_ICOLL_VECTOR register. 55 * 0 - Must Write to Vector register to go in-service. 56 * 1 - Go in-service as a read side effect 57 */ 58 #define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18) 59 #define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16) 60 61 #define ASM9260_HW_ICOLL_STAT_OFFSET 0x0030 62 /* 63 * bits 5:0 64 * Vector number of current interrupt. Multiply by 4 and add to vector base 65 * address to obtain the value in ASM9260_HW_ICOLL_VECTOR. 66 */ 67 68 /* 69 * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines 70 * coming from various parts of the chip. Its purpose is to improve diagnostic 71 * observability. 72 */ 73 #define ASM9260_HW_ICOLL_RAW0 0x0040 74 #define ASM9260_HW_ICOLL_RAW1 0x0050 75 76 #define ASM9260_HW_ICOLL_INTERRUPT0 0x0060 77 #define ASM9260_HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10) 78 /* 79 * WARNING: Modifying the priority of an enabled interrupt may result in 80 * undefined behavior. 81 */ 82 #define ASM9260_BM_INT_PRIORITY_MASK 0x3 83 #define ASM9260_BM_INT_ENABLE BIT(2) 84 #define ASM9260_BM_INT_SOFTIRQ BIT(3) 85 86 #define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3) 87 #define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \ 88 ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n))) 89 90 #define ASM9260_HW_ICOLL_VBASE 0x0160 91 /* 92 * bits 31:2 93 * This bitfield holds the upper 30 bits of the base address of the vector 94 * table. 95 */ 96 97 #define ASM9260_HW_ICOLL_CLEAR0 0x01d0 98 #define ASM9260_HW_ICOLL_CLEAR1 0x01e0 99 #define ASM9260_HW_ICOLL_CLEARn(n) (((n >> 5) * 0x10) \ 100 + SET_REG) 101 #define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f) 102 103 /* Scratchpad */ 104 #define ASM9260_HW_ICOLL_UNDEF_VECTOR 0x01f0 105 #endif