drivers/i2c/busses/i2c-axxia.c

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This source file includes following definitions.
i2c_int_disable
i2c_int_enable
ns_to_clk
axxia_i2c_init
i2c_m_rd
i2c_m_ten
i2c_m_recv_len
axxia_i2c_empty_rx_fifo
axxia_i2c_fill_tx_fifo
axxia_i2c_slv_fifo_event
axxia_i2c_slv_isr
axxia_i2c_isr
axxia_i2c_set_addr
axxia_i2c_handle_seq_nak
axxia_i2c_xfer_seq
axxia_i2c_xfer_msg
axxia_i2c_sequence_ok
axxia_i2c_xfer
axxia_i2c_get_scl
axxia_i2c_set_scl
axxia_i2c_get_sda
axxia_i2c_func
axxia_i2c_reg_slave
axxia_i2c_unreg_slave
axxia_i2c_probe
axxia_i2c_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This driver implements I2C master functionality using the LSI API2C
   4  * controller.
   5  *
   6  * NOTE: The controller has a limitation in that it can only do transfers of
   7  * maximum 255 bytes at a time. If a larger transfer is attempted, error code
   8  * (-EINVAL) is returned.
   9  */
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/i2c.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/platform_device.h>
  21 
  22 #define SCL_WAIT_TIMEOUT_NS 25000000
  23 #define I2C_XFER_TIMEOUT    (msecs_to_jiffies(250))
  24 #define I2C_STOP_TIMEOUT    (msecs_to_jiffies(100))
  25 #define FIFO_SIZE           8
  26 #define SEQ_LEN             2
  27 
  28 #define GLOBAL_CONTROL          0x00
  29 #define   GLOBAL_MST_EN         BIT(0)
  30 #define   GLOBAL_SLV_EN         BIT(1)
  31 #define   GLOBAL_IBML_EN        BIT(2)
  32 #define INTERRUPT_STATUS        0x04
  33 #define INTERRUPT_ENABLE        0x08
  34 #define   INT_SLV               BIT(1)
  35 #define   INT_MST               BIT(0)
  36 #define WAIT_TIMER_CONTROL      0x0c
  37 #define   WT_EN                 BIT(15)
  38 #define   WT_VALUE(_x)          ((_x) & 0x7fff)
  39 #define IBML_TIMEOUT            0x10
  40 #define IBML_LOW_MEXT           0x14
  41 #define IBML_LOW_SEXT           0x18
  42 #define TIMER_CLOCK_DIV         0x1c
  43 #define I2C_BUS_MONITOR         0x20
  44 #define   BM_SDAC               BIT(3)
  45 #define   BM_SCLC               BIT(2)
  46 #define   BM_SDAS               BIT(1)
  47 #define   BM_SCLS               BIT(0)
  48 #define SOFT_RESET              0x24
  49 #define MST_COMMAND             0x28
  50 #define   CMD_BUSY              (1<<3)
  51 #define   CMD_MANUAL            (0x00 | CMD_BUSY)
  52 #define   CMD_AUTO              (0x01 | CMD_BUSY)
  53 #define   CMD_SEQUENCE          (0x02 | CMD_BUSY)
  54 #define MST_RX_XFER             0x2c
  55 #define MST_TX_XFER             0x30
  56 #define MST_ADDR_1              0x34
  57 #define MST_ADDR_2              0x38
  58 #define MST_DATA                0x3c
  59 #define MST_TX_FIFO             0x40
  60 #define MST_RX_FIFO             0x44
  61 #define MST_INT_ENABLE          0x48
  62 #define MST_INT_STATUS          0x4c
  63 #define   MST_STATUS_RFL        (1 << 13) /* RX FIFO serivce */
  64 #define   MST_STATUS_TFL        (1 << 12) /* TX FIFO service */
  65 #define   MST_STATUS_SNS        (1 << 11) /* Manual mode done */
  66 #define   MST_STATUS_SS         (1 << 10) /* Automatic mode done */
  67 #define   MST_STATUS_SCC        (1 << 9)  /* Stop complete */
  68 #define   MST_STATUS_IP         (1 << 8)  /* Invalid parameter */
  69 #define   MST_STATUS_TSS        (1 << 7)  /* Timeout */
  70 #define   MST_STATUS_AL         (1 << 6)  /* Arbitration lost */
  71 #define   MST_STATUS_ND         (1 << 5)  /* NAK on data phase */
  72 #define   MST_STATUS_NA         (1 << 4)  /* NAK on address phase */
  73 #define   MST_STATUS_NAK        (MST_STATUS_NA | \
  74                                  MST_STATUS_ND)
  75 #define   MST_STATUS_ERR        (MST_STATUS_NAK | \
  76                                  MST_STATUS_AL  | \
  77                                  MST_STATUS_IP)
  78 #define MST_TX_BYTES_XFRD       0x50
  79 #define MST_RX_BYTES_XFRD       0x54
  80 #define SLV_ADDR_DEC_CTL        0x58
  81 #define   SLV_ADDR_DEC_GCE      BIT(0)  /* ACK to General Call Address from own master (loopback) */
  82 #define   SLV_ADDR_DEC_OGCE     BIT(1)  /* ACK to General Call Address from external masters */
  83 #define   SLV_ADDR_DEC_SA1E     BIT(2)  /* ACK to addr_1 enabled */
  84 #define   SLV_ADDR_DEC_SA1M     BIT(3)  /* 10-bit addressing for addr_1 enabled */
  85 #define   SLV_ADDR_DEC_SA2E     BIT(4)  /* ACK to addr_2 enabled */
  86 #define   SLV_ADDR_DEC_SA2M     BIT(5)  /* 10-bit addressing for addr_2 enabled */
  87 #define SLV_ADDR_1              0x5c
  88 #define SLV_ADDR_2              0x60
  89 #define SLV_RX_CTL              0x64
  90 #define   SLV_RX_ACSA1          BIT(0)  /* Generate ACK for writes to addr_1 */
  91 #define   SLV_RX_ACSA2          BIT(1)  /* Generate ACK for writes to addr_2 */
  92 #define   SLV_RX_ACGCA          BIT(2)  /* ACK data phase transfers to General Call Address */
  93 #define SLV_DATA                0x68
  94 #define SLV_RX_FIFO             0x6c
  95 #define   SLV_FIFO_DV1          BIT(0)  /* Data Valid for addr_1 */
  96 #define   SLV_FIFO_DV2          BIT(1)  /* Data Valid for addr_2 */
  97 #define   SLV_FIFO_AS           BIT(2)  /* (N)ACK Sent */
  98 #define   SLV_FIFO_TNAK         BIT(3)  /* Timeout NACK */
  99 #define   SLV_FIFO_STRC         BIT(4)  /* First byte after start condition received */
 100 #define   SLV_FIFO_RSC          BIT(5)  /* Repeated Start Condition */
 101 #define   SLV_FIFO_STPC         BIT(6)  /* Stop Condition */
 102 #define   SLV_FIFO_DV           (SLV_FIFO_DV1 | SLV_FIFO_DV2)
 103 #define SLV_INT_ENABLE          0x70
 104 #define SLV_INT_STATUS          0x74
 105 #define   SLV_STATUS_RFH        BIT(0)  /* FIFO service */
 106 #define   SLV_STATUS_WTC        BIT(1)  /* Write transfer complete */
 107 #define   SLV_STATUS_SRS1       BIT(2)  /* Slave read from addr 1 */
 108 #define   SLV_STATUS_SRRS1      BIT(3)  /* Repeated start from addr 1 */
 109 #define   SLV_STATUS_SRND1      BIT(4)  /* Read request not following start condition */
 110 #define   SLV_STATUS_SRC1       BIT(5)  /* Read canceled */
 111 #define   SLV_STATUS_SRAT1      BIT(6)  /* Slave Read timed out */
 112 #define   SLV_STATUS_SRDRE1     BIT(7)  /* Data written after timed out */
 113 #define SLV_READ_DUMMY          0x78
 114 #define SCL_HIGH_PERIOD         0x80
 115 #define SCL_LOW_PERIOD          0x84
 116 #define SPIKE_FLTR_LEN          0x88
 117 #define SDA_SETUP_TIME          0x8c
 118 #define SDA_HOLD_TIME           0x90
 119 
 120 /**
 121  * axxia_i2c_dev - I2C device context
 122  * @base: pointer to register struct
 123  * @msg: pointer to current message
 124  * @msg_r: pointer to current read message (sequence transfer)
 125  * @msg_xfrd: number of bytes transferred in tx_fifo
 126  * @msg_xfrd_r: number of bytes transferred in rx_fifo
 127  * @msg_err: error code for completed message
 128  * @msg_complete: xfer completion object
 129  * @dev: device reference
 130  * @adapter: core i2c abstraction
 131  * @i2c_clk: clock reference for i2c input clock
 132  * @bus_clk_rate: current i2c bus clock rate
 133  * @last: a flag indicating is this is last message in transfer
 134  */
 135 struct axxia_i2c_dev {
 136         void __iomem *base;
 137         struct i2c_msg *msg;
 138         struct i2c_msg *msg_r;
 139         size_t msg_xfrd;
 140         size_t msg_xfrd_r;
 141         int msg_err;
 142         struct completion msg_complete;
 143         struct device *dev;
 144         struct i2c_adapter adapter;
 145         struct clk *i2c_clk;
 146         u32 bus_clk_rate;
 147         bool last;
 148         struct i2c_client *slave;
 149         int irq;
 150 };
 151 
 152 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
 153 {
 154         u32 int_en;
 155 
 156         int_en = readl(idev->base + MST_INT_ENABLE);
 157         writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
 158 }
 159 
 160 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
 161 {
 162         u32 int_en;
 163 
 164         int_en = readl(idev->base + MST_INT_ENABLE);
 165         writel(int_en | mask, idev->base + MST_INT_ENABLE);
 166 }
 167 
 168 /**
 169  * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
 170  */
 171 static u32 ns_to_clk(u64 ns, u32 clk_mhz)
 172 {
 173         return div_u64(ns * clk_mhz, 1000);
 174 }
 175 
 176 static int axxia_i2c_init(struct axxia_i2c_dev *idev)
 177 {
 178         u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
 179         u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
 180         u32 t_setup;
 181         u32 t_high, t_low;
 182         u32 tmo_clk;
 183         u32 prescale;
 184         unsigned long timeout;
 185 
 186         dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
 187                 idev->bus_clk_rate, clk_mhz, divisor);
 188 
 189         /* Reset controller */
 190         writel(0x01, idev->base + SOFT_RESET);
 191         timeout = jiffies + msecs_to_jiffies(100);
 192         while (readl(idev->base + SOFT_RESET) & 1) {
 193                 if (time_after(jiffies, timeout)) {
 194                         dev_warn(idev->dev, "Soft reset failed\n");
 195                         break;
 196                 }
 197         }
 198 
 199         /* Enable Master Mode */
 200         writel(0x1, idev->base + GLOBAL_CONTROL);
 201 
 202         if (idev->bus_clk_rate <= 100000) {
 203                 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
 204                 t_high = divisor * 1 / 2;
 205                 t_low = divisor * 1 / 2;
 206                 t_setup = ns_to_clk(250, clk_mhz);
 207         } else {
 208                 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
 209                 t_high = divisor * 1 / 3;
 210                 t_low = divisor * 2 / 3;
 211                 t_setup = ns_to_clk(100, clk_mhz);
 212         }
 213 
 214         /* SCL High Time */
 215         writel(t_high, idev->base + SCL_HIGH_PERIOD);
 216         /* SCL Low Time */
 217         writel(t_low, idev->base + SCL_LOW_PERIOD);
 218         /* SDA Setup Time */
 219         writel(t_setup, idev->base + SDA_SETUP_TIME);
 220         /* SDA Hold Time, 300ns */
 221         writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
 222         /* Filter <50ns spikes */
 223         writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
 224 
 225         /* Configure Time-Out Registers */
 226         tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
 227 
 228         /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
 229         for (prescale = 0; prescale < 15; ++prescale) {
 230                 if (tmo_clk <= 0x7fff)
 231                         break;
 232                 tmo_clk >>= 1;
 233         }
 234         if (tmo_clk > 0x7fff)
 235                 tmo_clk = 0x7fff;
 236 
 237         /* Prescale divider (log2) */
 238         writel(prescale, idev->base + TIMER_CLOCK_DIV);
 239         /* Timeout in divided clocks */
 240         writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
 241 
 242         /* Mask all master interrupt bits */
 243         i2c_int_disable(idev, ~0);
 244 
 245         /* Interrupt enable */
 246         writel(0x01, idev->base + INTERRUPT_ENABLE);
 247 
 248         return 0;
 249 }
 250 
 251 static int i2c_m_rd(const struct i2c_msg *msg)
 252 {
 253         return (msg->flags & I2C_M_RD) != 0;
 254 }
 255 
 256 static int i2c_m_ten(const struct i2c_msg *msg)
 257 {
 258         return (msg->flags & I2C_M_TEN) != 0;
 259 }
 260 
 261 static int i2c_m_recv_len(const struct i2c_msg *msg)
 262 {
 263         return (msg->flags & I2C_M_RECV_LEN) != 0;
 264 }
 265 
 266 /**
 267  * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
 268  * transfer length if this is the first byte of such a transfer.
 269  */
 270 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
 271 {
 272         struct i2c_msg *msg = idev->msg_r;
 273         size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
 274         int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
 275 
 276         while (bytes_to_transfer-- > 0) {
 277                 int c = readl(idev->base + MST_DATA);
 278 
 279                 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
 280                         /*
 281                          * Check length byte for SMBus block read
 282                          */
 283                         if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
 284                                 idev->msg_err = -EPROTO;
 285                                 i2c_int_disable(idev, ~MST_STATUS_TSS);
 286                                 complete(&idev->msg_complete);
 287                                 break;
 288                         }
 289                         msg->len = 1 + c;
 290                         writel(msg->len, idev->base + MST_RX_XFER);
 291                 }
 292                 msg->buf[idev->msg_xfrd_r++] = c;
 293         }
 294 
 295         return 0;
 296 }
 297 
 298 /**
 299  * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
 300  * @return: Number of bytes left to transfer.
 301  */
 302 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
 303 {
 304         struct i2c_msg *msg = idev->msg;
 305         size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
 306         int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
 307         int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
 308 
 309         while (bytes_to_transfer-- > 0)
 310                 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
 311 
 312         return ret;
 313 }
 314 
 315 static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev)
 316 {
 317         u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
 318         u8 val;
 319 
 320         dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status);
 321 
 322         if (fifo_status & SLV_FIFO_DV1) {
 323                 if (fifo_status & SLV_FIFO_STRC)
 324                         i2c_slave_event(idev->slave,
 325                                         I2C_SLAVE_WRITE_REQUESTED, &val);
 326 
 327                 val = readl(idev->base + SLV_DATA);
 328                 i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val);
 329         }
 330         if (fifo_status & SLV_FIFO_STPC) {
 331                 readl(idev->base + SLV_DATA); /* dummy read */
 332                 i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
 333         }
 334         if (fifo_status & SLV_FIFO_RSC)
 335                 readl(idev->base + SLV_DATA); /* dummy read */
 336 }
 337 
 338 static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev)
 339 {
 340         u32 status = readl(idev->base + SLV_INT_STATUS);
 341         u8 val;
 342 
 343         dev_dbg(idev->dev, "slave irq status=0x%x\n", status);
 344 
 345         if (status & SLV_STATUS_RFH)
 346                 axxia_i2c_slv_fifo_event(idev);
 347         if (status & SLV_STATUS_SRS1) {
 348                 i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val);
 349                 writel(val, idev->base + SLV_DATA);
 350         }
 351         if (status & SLV_STATUS_SRND1) {
 352                 i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val);
 353                 writel(val, idev->base + SLV_DATA);
 354         }
 355         if (status & SLV_STATUS_SRC1)
 356                 i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
 357 
 358         writel(INT_SLV, idev->base + INTERRUPT_STATUS);
 359         return IRQ_HANDLED;
 360 }
 361 
 362 static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
 363 {
 364         struct axxia_i2c_dev *idev = _dev;
 365         irqreturn_t ret = IRQ_NONE;
 366         u32 status;
 367 
 368         status = readl(idev->base + INTERRUPT_STATUS);
 369 
 370         if (status & INT_SLV)
 371                 ret = axxia_i2c_slv_isr(idev);
 372         if (!(status & INT_MST))
 373                 return ret;
 374 
 375         /* Read interrupt status bits */
 376         status = readl(idev->base + MST_INT_STATUS);
 377 
 378         if (!idev->msg) {
 379                 dev_warn(idev->dev, "unexpected interrupt\n");
 380                 goto out;
 381         }
 382 
 383         /* RX FIFO needs service? */
 384         if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
 385                 axxia_i2c_empty_rx_fifo(idev);
 386 
 387         /* TX FIFO needs service? */
 388         if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
 389                 if (axxia_i2c_fill_tx_fifo(idev) == 0)
 390                         i2c_int_disable(idev, MST_STATUS_TFL);
 391         }
 392 
 393         if (unlikely(status & MST_STATUS_ERR)) {
 394                 /* Transfer error */
 395                 i2c_int_disable(idev, ~0);
 396                 if (status & MST_STATUS_AL)
 397                         idev->msg_err = -EAGAIN;
 398                 else if (status & MST_STATUS_NAK)
 399                         idev->msg_err = -ENXIO;
 400                 else
 401                         idev->msg_err = -EIO;
 402                 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
 403                         status,
 404                         idev->msg->addr,
 405                         readl(idev->base + MST_RX_BYTES_XFRD),
 406                         readl(idev->base + MST_RX_XFER),
 407                         readl(idev->base + MST_TX_BYTES_XFRD),
 408                         readl(idev->base + MST_TX_XFER));
 409                 complete(&idev->msg_complete);
 410         } else if (status & MST_STATUS_SCC) {
 411                 /* Stop completed */
 412                 i2c_int_disable(idev, ~MST_STATUS_TSS);
 413                 complete(&idev->msg_complete);
 414         } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
 415                 /* Transfer done */
 416                 int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
 417 
 418                 i2c_int_disable(idev, mask);
 419                 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
 420                         axxia_i2c_empty_rx_fifo(idev);
 421                 complete(&idev->msg_complete);
 422         } else if (status & MST_STATUS_TSS) {
 423                 /* Transfer timeout */
 424                 idev->msg_err = -ETIMEDOUT;
 425                 i2c_int_disable(idev, ~MST_STATUS_TSS);
 426                 complete(&idev->msg_complete);
 427         }
 428 
 429 out:
 430         /* Clear interrupt */
 431         writel(INT_MST, idev->base + INTERRUPT_STATUS);
 432 
 433         return IRQ_HANDLED;
 434 }
 435 
 436 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
 437 {
 438         u32 addr_1, addr_2;
 439 
 440         if (i2c_m_ten(msg)) {
 441                 /* 10-bit address
 442                  *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
 443                  *   addr_2: addr[7:0]
 444                  */
 445                 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
 446                 if (i2c_m_rd(msg))
 447                         addr_1 |= 1;    /* Set the R/nW bit of the address */
 448                 addr_2 = msg->addr & 0xFF;
 449         } else {
 450                 /* 7-bit address
 451                  *   addr_1: addr[6:0] | (R/nW)
 452                  *   addr_2: dont care
 453                  */
 454                 addr_1 = i2c_8bit_addr_from_msg(msg);
 455                 addr_2 = 0;
 456         }
 457 
 458         writel(addr_1, idev->base + MST_ADDR_1);
 459         writel(addr_2, idev->base + MST_ADDR_2);
 460 }
 461 
 462 /* The NAK interrupt will be sent _before_ issuing STOP command
 463  * so the controller might still be busy processing it. No
 464  * interrupt will be sent at the end so we have to poll for it
 465  */
 466 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
 467 {
 468         unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
 469 
 470         do {
 471                 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
 472                         return 0;
 473                 usleep_range(1, 100);
 474         } while (time_before(jiffies, timeout));
 475 
 476         return -ETIMEDOUT;
 477 }
 478 
 479 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
 480 {
 481         u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
 482         u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
 483         unsigned long time_left;
 484 
 485         axxia_i2c_set_addr(idev, &msgs[0]);
 486 
 487         writel(msgs[0].len, idev->base + MST_TX_XFER);
 488         writel(rlen, idev->base + MST_RX_XFER);
 489 
 490         idev->msg = &msgs[0];
 491         idev->msg_r = &msgs[1];
 492         idev->msg_xfrd = 0;
 493         idev->msg_xfrd_r = 0;
 494         idev->last = true;
 495         axxia_i2c_fill_tx_fifo(idev);
 496 
 497         writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
 498 
 499         reinit_completion(&idev->msg_complete);
 500         i2c_int_enable(idev, int_mask);
 501 
 502         time_left = wait_for_completion_timeout(&idev->msg_complete,
 503                                                 I2C_XFER_TIMEOUT);
 504 
 505         if (idev->msg_err == -ENXIO) {
 506                 if (axxia_i2c_handle_seq_nak(idev))
 507                         axxia_i2c_init(idev);
 508         } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
 509                 dev_warn(idev->dev, "busy after xfer\n");
 510         }
 511 
 512         if (time_left == 0) {
 513                 idev->msg_err = -ETIMEDOUT;
 514                 i2c_recover_bus(&idev->adapter);
 515                 axxia_i2c_init(idev);
 516         }
 517 
 518         if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
 519                 axxia_i2c_init(idev);
 520 
 521         return idev->msg_err;
 522 }
 523 
 524 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
 525                               bool last)
 526 {
 527         u32 int_mask = MST_STATUS_ERR;
 528         u32 rx_xfer, tx_xfer;
 529         unsigned long time_left;
 530         unsigned int wt_value;
 531 
 532         idev->msg = msg;
 533         idev->msg_r = msg;
 534         idev->msg_xfrd = 0;
 535         idev->msg_xfrd_r = 0;
 536         idev->last = last;
 537         reinit_completion(&idev->msg_complete);
 538 
 539         axxia_i2c_set_addr(idev, msg);
 540 
 541         if (i2c_m_rd(msg)) {
 542                 /* I2C read transfer */
 543                 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
 544                 tx_xfer = 0;
 545         } else {
 546                 /* I2C write transfer */
 547                 rx_xfer = 0;
 548                 tx_xfer = msg->len;
 549         }
 550 
 551         writel(rx_xfer, idev->base + MST_RX_XFER);
 552         writel(tx_xfer, idev->base + MST_TX_XFER);
 553 
 554         if (i2c_m_rd(msg))
 555                 int_mask |= MST_STATUS_RFL;
 556         else if (axxia_i2c_fill_tx_fifo(idev) != 0)
 557                 int_mask |= MST_STATUS_TFL;
 558 
 559         wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
 560         /* Disable wait timer temporarly */
 561         writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
 562         /* Check if timeout error happened */
 563         if (idev->msg_err)
 564                 goto out;
 565 
 566         if (!last) {
 567                 writel(CMD_MANUAL, idev->base + MST_COMMAND);
 568                 int_mask |= MST_STATUS_SNS;
 569         } else {
 570                 writel(CMD_AUTO, idev->base + MST_COMMAND);
 571                 int_mask |= MST_STATUS_SS;
 572         }
 573 
 574         writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
 575 
 576         i2c_int_enable(idev, int_mask);
 577 
 578         time_left = wait_for_completion_timeout(&idev->msg_complete,
 579                                               I2C_XFER_TIMEOUT);
 580 
 581         i2c_int_disable(idev, int_mask);
 582 
 583         if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
 584                 dev_warn(idev->dev, "busy after xfer\n");
 585 
 586         if (time_left == 0) {
 587                 idev->msg_err = -ETIMEDOUT;
 588                 i2c_recover_bus(&idev->adapter);
 589                 axxia_i2c_init(idev);
 590         }
 591 
 592 out:
 593         if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
 594                         idev->msg_err != -ETIMEDOUT)
 595                 axxia_i2c_init(idev);
 596 
 597         return idev->msg_err;
 598 }
 599 
 600 /* This function checks if the msgs[] array contains messages compatible with
 601  * Sequence mode of operation. This mode assumes there will be exactly one
 602  * write of non-zero length followed by exactly one read of non-zero length,
 603  * both targeted at the same client device.
 604  */
 605 static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
 606 {
 607         return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
 608                msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
 609                msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
 610 }
 611 
 612 static int
 613 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 614 {
 615         struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 616         int i;
 617         int ret = 0;
 618 
 619         idev->msg_err = 0;
 620 
 621         if (axxia_i2c_sequence_ok(msgs, num)) {
 622                 ret = axxia_i2c_xfer_seq(idev, msgs);
 623                 return ret ? : SEQ_LEN;
 624         }
 625 
 626         i2c_int_enable(idev, MST_STATUS_TSS);
 627 
 628         for (i = 0; ret == 0 && i < num; ++i)
 629                 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
 630 
 631         return ret ? : i;
 632 }
 633 
 634 static int axxia_i2c_get_scl(struct i2c_adapter *adap)
 635 {
 636         struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 637 
 638         return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
 639 }
 640 
 641 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
 642 {
 643         struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 644         u32 tmp;
 645 
 646         /* Preserve SDA Control */
 647         tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
 648         if (!val)
 649                 tmp |= BM_SCLC;
 650         writel(tmp, idev->base + I2C_BUS_MONITOR);
 651 }
 652 
 653 static int axxia_i2c_get_sda(struct i2c_adapter *adap)
 654 {
 655         struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 656 
 657         return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
 658 }
 659 
 660 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
 661         .recover_bus = i2c_generic_scl_recovery,
 662         .get_scl = axxia_i2c_get_scl,
 663         .set_scl = axxia_i2c_set_scl,
 664         .get_sda = axxia_i2c_get_sda,
 665 };
 666 
 667 static u32 axxia_i2c_func(struct i2c_adapter *adap)
 668 {
 669         u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 670                     I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
 671         return caps;
 672 }
 673 
 674 static int axxia_i2c_reg_slave(struct i2c_client *slave)
 675 {
 676         struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
 677         u32 slv_int_mask = SLV_STATUS_RFH;
 678         u32 dec_ctl;
 679 
 680         if (idev->slave)
 681                 return -EBUSY;
 682 
 683         idev->slave = slave;
 684 
 685         /* Enable slave mode as well */
 686         writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
 687         writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
 688 
 689         /* Set slave address */
 690         dec_ctl = SLV_ADDR_DEC_SA1E;
 691         if (slave->flags & I2C_CLIENT_TEN)
 692                 dec_ctl |= SLV_ADDR_DEC_SA1M;
 693 
 694         writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
 695         writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
 696         writel(slave->addr, idev->base + SLV_ADDR_1);
 697 
 698         /* Enable interrupts */
 699         slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1;
 700         slv_int_mask |= SLV_STATUS_SRC1;
 701         writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
 702 
 703         return 0;
 704 }
 705 
 706 static int axxia_i2c_unreg_slave(struct i2c_client *slave)
 707 {
 708         struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
 709 
 710         /* Disable slave mode */
 711         writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
 712         writel(INT_MST, idev->base + INTERRUPT_ENABLE);
 713 
 714         synchronize_irq(idev->irq);
 715 
 716         idev->slave = NULL;
 717 
 718         return 0;
 719 }
 720 
 721 static const struct i2c_algorithm axxia_i2c_algo = {
 722         .master_xfer = axxia_i2c_xfer,
 723         .functionality = axxia_i2c_func,
 724         .reg_slave = axxia_i2c_reg_slave,
 725         .unreg_slave = axxia_i2c_unreg_slave,
 726 };
 727 
 728 static const struct i2c_adapter_quirks axxia_i2c_quirks = {
 729         .max_read_len = 255,
 730         .max_write_len = 255,
 731 };
 732 
 733 static int axxia_i2c_probe(struct platform_device *pdev)
 734 {
 735         struct device_node *np = pdev->dev.of_node;
 736         struct axxia_i2c_dev *idev = NULL;
 737         struct resource *res;
 738         void __iomem *base;
 739         int ret = 0;
 740 
 741         idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
 742         if (!idev)
 743                 return -ENOMEM;
 744 
 745         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 746         base = devm_ioremap_resource(&pdev->dev, res);
 747         if (IS_ERR(base))
 748                 return PTR_ERR(base);
 749 
 750         idev->irq = platform_get_irq(pdev, 0);
 751         if (idev->irq < 0) {
 752                 dev_err(&pdev->dev, "missing interrupt resource\n");
 753                 return idev->irq;
 754         }
 755 
 756         idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
 757         if (IS_ERR(idev->i2c_clk)) {
 758                 dev_err(&pdev->dev, "missing clock\n");
 759                 return PTR_ERR(idev->i2c_clk);
 760         }
 761 
 762         idev->base = base;
 763         idev->dev = &pdev->dev;
 764         init_completion(&idev->msg_complete);
 765 
 766         of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
 767         if (idev->bus_clk_rate == 0)
 768                 idev->bus_clk_rate = 100000;    /* default clock rate */
 769 
 770         ret = clk_prepare_enable(idev->i2c_clk);
 771         if (ret) {
 772                 dev_err(&pdev->dev, "failed to enable clock\n");
 773                 return ret;
 774         }
 775 
 776         ret = axxia_i2c_init(idev);
 777         if (ret) {
 778                 dev_err(&pdev->dev, "failed to initialize\n");
 779                 goto error_disable_clk;
 780         }
 781 
 782         ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0,
 783                                pdev->name, idev);
 784         if (ret) {
 785                 dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq);
 786                 goto error_disable_clk;
 787         }
 788 
 789         i2c_set_adapdata(&idev->adapter, idev);
 790         strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
 791         idev->adapter.owner = THIS_MODULE;
 792         idev->adapter.algo = &axxia_i2c_algo;
 793         idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
 794         idev->adapter.quirks = &axxia_i2c_quirks;
 795         idev->adapter.dev.parent = &pdev->dev;
 796         idev->adapter.dev.of_node = pdev->dev.of_node;
 797 
 798         platform_set_drvdata(pdev, idev);
 799 
 800         ret = i2c_add_adapter(&idev->adapter);
 801         if (ret)
 802                 goto error_disable_clk;
 803 
 804         return 0;
 805 
 806 error_disable_clk:
 807         clk_disable_unprepare(idev->i2c_clk);
 808         return ret;
 809 }
 810 
 811 static int axxia_i2c_remove(struct platform_device *pdev)
 812 {
 813         struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
 814 
 815         clk_disable_unprepare(idev->i2c_clk);
 816         i2c_del_adapter(&idev->adapter);
 817 
 818         return 0;
 819 }
 820 
 821 /* Match table for of_platform binding */
 822 static const struct of_device_id axxia_i2c_of_match[] = {
 823         { .compatible = "lsi,api2c", },
 824         {},
 825 };
 826 
 827 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
 828 
 829 static struct platform_driver axxia_i2c_driver = {
 830         .probe = axxia_i2c_probe,
 831         .remove = axxia_i2c_remove,
 832         .driver = {
 833                 .name = "axxia-i2c",
 834                 .of_match_table = axxia_i2c_of_match,
 835         },
 836 };
 837 
 838 module_platform_driver(axxia_i2c_driver);
 839 
 840 MODULE_DESCRIPTION("Axxia I2C Bus driver");
 841 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
 842 MODULE_LICENSE("GPL v2");
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root/drivers/i2c/busses/i2c-axxia.c

DEFINITIONS
