drivers/i2c/busses/i2c-rk3x.c

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This source file includes following definitions.
i2c_writel
i2c_readl
rk3x_i2c_clean_ipd
rk3x_i2c_start
rk3x_i2c_stop
rk3x_i2c_prepare_read
rk3x_i2c_fill_transmit_buf
rk3x_i2c_handle_start
rk3x_i2c_handle_write
rk3x_i2c_handle_read
rk3x_i2c_handle_stop
rk3x_i2c_irq
rk3x_i2c_get_spec
rk3x_i2c_v0_calc_timings
rk3x_i2c_v1_calc_timings
rk3x_i2c_adapt_div
rk3x_i2c_clk_notifier_cb
rk3x_i2c_setup
rk3x_i2c_xfer
rk3x_i2c_resume
rk3x_i2c_func
rk3x_i2c_probe
rk3x_i2c_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for I2C adapter in Rockchip RK3xxx SoC
   4  *
   5  * Max Schwarz <max.schwarz@online.de>
   6  * based on the patches by Rockchip Inc.
   7  */
   8 
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/i2c.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/clk.h>
  21 #include <linux/wait.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24 #include <linux/math64.h>
  25 
  26 
  27 /* Register Map */
  28 #define REG_CON        0x00 /* control register */
  29 #define REG_CLKDIV     0x04 /* clock divisor register */
  30 #define REG_MRXADDR    0x08 /* slave address for REGISTER_TX */
  31 #define REG_MRXRADDR   0x0c /* slave register address for REGISTER_TX */
  32 #define REG_MTXCNT     0x10 /* number of bytes to be transmitted */
  33 #define REG_MRXCNT     0x14 /* number of bytes to be received */
  34 #define REG_IEN        0x18 /* interrupt enable */
  35 #define REG_IPD        0x1c /* interrupt pending */
  36 #define REG_FCNT       0x20 /* finished count */
  37 
  38 /* Data buffer offsets */
  39 #define TXBUFFER_BASE 0x100
  40 #define RXBUFFER_BASE 0x200
  41 
  42 /* REG_CON bits */
  43 #define REG_CON_EN        BIT(0)
  44 enum {
  45         REG_CON_MOD_TX = 0,      /* transmit data */
  46         REG_CON_MOD_REGISTER_TX, /* select register and restart */
  47         REG_CON_MOD_RX,          /* receive data */
  48         REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
  49                                   * register addr */
  50 };
  51 #define REG_CON_MOD(mod)  ((mod) << 1)
  52 #define REG_CON_MOD_MASK  (BIT(1) | BIT(2))
  53 #define REG_CON_START     BIT(3)
  54 #define REG_CON_STOP      BIT(4)
  55 #define REG_CON_LASTACK   BIT(5) /* 1: send NACK after last received byte */
  56 #define REG_CON_ACTACK    BIT(6) /* 1: stop if NACK is received */
  57 
  58 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
  59 
  60 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
  61 #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
  62 #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
  63 
  64 /* REG_MRXADDR bits */
  65 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
  66 
  67 /* REG_IEN/REG_IPD bits */
  68 #define REG_INT_BTF       BIT(0) /* a byte was transmitted */
  69 #define REG_INT_BRF       BIT(1) /* a byte was received */
  70 #define REG_INT_MBTF      BIT(2) /* master data transmit finished */
  71 #define REG_INT_MBRF      BIT(3) /* master data receive finished */
  72 #define REG_INT_START     BIT(4) /* START condition generated */
  73 #define REG_INT_STOP      BIT(5) /* STOP condition generated */
  74 #define REG_INT_NAKRCV    BIT(6) /* NACK received */
  75 #define REG_INT_ALL       0x7f
  76 
  77 /* Constants */
  78 #define WAIT_TIMEOUT      1000 /* ms */
  79 #define DEFAULT_SCL_RATE  (100 * 1000) /* Hz */
  80 
  81 /**
  82  * struct i2c_spec_values:
  83  * @min_hold_start_ns: min hold time (repeated) START condition
  84  * @min_low_ns: min LOW period of the SCL clock
  85  * @min_high_ns: min HIGH period of the SCL cloc
  86  * @min_setup_start_ns: min set-up time for a repeated START conditio
  87  * @max_data_hold_ns: max data hold time
  88  * @min_data_setup_ns: min data set-up time
  89  * @min_setup_stop_ns: min set-up time for STOP condition
  90  * @min_hold_buffer_ns: min bus free time between a STOP and
  91  * START condition
  92  */
  93 struct i2c_spec_values {
  94         unsigned long min_hold_start_ns;
  95         unsigned long min_low_ns;
  96         unsigned long min_high_ns;
  97         unsigned long min_setup_start_ns;
  98         unsigned long max_data_hold_ns;
  99         unsigned long min_data_setup_ns;
 100         unsigned long min_setup_stop_ns;
 101         unsigned long min_hold_buffer_ns;
 102 };
 103 
 104 static const struct i2c_spec_values standard_mode_spec = {
 105         .min_hold_start_ns = 4000,
 106         .min_low_ns = 4700,
 107         .min_high_ns = 4000,
 108         .min_setup_start_ns = 4700,
 109         .max_data_hold_ns = 3450,
 110         .min_data_setup_ns = 250,
 111         .min_setup_stop_ns = 4000,
 112         .min_hold_buffer_ns = 4700,
 113 };
 114 
 115 static const struct i2c_spec_values fast_mode_spec = {
 116         .min_hold_start_ns = 600,
 117         .min_low_ns = 1300,
 118         .min_high_ns = 600,
 119         .min_setup_start_ns = 600,
 120         .max_data_hold_ns = 900,
 121         .min_data_setup_ns = 100,
 122         .min_setup_stop_ns = 600,
 123         .min_hold_buffer_ns = 1300,
 124 };
 125 
 126 static const struct i2c_spec_values fast_mode_plus_spec = {
 127         .min_hold_start_ns = 260,
 128         .min_low_ns = 500,
 129         .min_high_ns = 260,
 130         .min_setup_start_ns = 260,
 131         .max_data_hold_ns = 400,
 132         .min_data_setup_ns = 50,
 133         .min_setup_stop_ns = 260,
 134         .min_hold_buffer_ns = 500,
 135 };
 136 
 137 /**
 138  * struct rk3x_i2c_calced_timings:
 139  * @div_low: Divider output for low
 140  * @div_high: Divider output for high
 141  * @tuning: Used to adjust setup/hold data time,
 142  * setup/hold start time and setup stop time for
 143  * v1's calc_timings, the tuning should all be 0
 144  * for old hardware anyone using v0's calc_timings.
 145  */
 146 struct rk3x_i2c_calced_timings {
 147         unsigned long div_low;
 148         unsigned long div_high;
 149         unsigned int tuning;
 150 };
 151 
 152 enum rk3x_i2c_state {
 153         STATE_IDLE,
 154         STATE_START,
 155         STATE_READ,
 156         STATE_WRITE,
 157         STATE_STOP
 158 };
 159 
 160 /**
 161  * struct rk3x_i2c_soc_data:
 162  * @grf_offset: offset inside the grf regmap for setting the i2c type
 163  * @calc_timings: Callback function for i2c timing information calculated
 164  */
 165 struct rk3x_i2c_soc_data {
 166         int grf_offset;
 167         int (*calc_timings)(unsigned long, struct i2c_timings *,
 168                             struct rk3x_i2c_calced_timings *);
 169 };
 170 
 171 /**
 172  * struct rk3x_i2c - private data of the controller
 173  * @adap: corresponding I2C adapter
 174  * @dev: device for this controller
 175  * @soc_data: related soc data struct
 176  * @regs: virtual memory area
 177  * @clk: function clk for rk3399 or function & Bus clks for others
 178  * @pclk: Bus clk for rk3399
 179  * @clk_rate_nb: i2c clk rate change notify
 180  * @t: I2C known timing information
 181  * @lock: spinlock for the i2c bus
 182  * @wait: the waitqueue to wait for i2c transfer
 183  * @busy: the condition for the event to wait for
 184  * @msg: current i2c message
 185  * @addr: addr of i2c slave device
 186  * @mode: mode of i2c transfer
 187  * @is_last_msg: flag determines whether it is the last msg in this transfer
 188  * @state: state of i2c transfer
 189  * @processed: byte length which has been send or received
 190  * @error: error code for i2c transfer
 191  */
 192 struct rk3x_i2c {
 193         struct i2c_adapter adap;
 194         struct device *dev;
 195         const struct rk3x_i2c_soc_data *soc_data;
 196 
 197         /* Hardware resources */
 198         void __iomem *regs;
 199         struct clk *clk;
 200         struct clk *pclk;
 201         struct notifier_block clk_rate_nb;
 202 
 203         /* Settings */
 204         struct i2c_timings t;
 205 
 206         /* Synchronization & notification */
 207         spinlock_t lock;
 208         wait_queue_head_t wait;
 209         bool busy;
 210 
 211         /* Current message */
 212         struct i2c_msg *msg;
 213         u8 addr;
 214         unsigned int mode;
 215         bool is_last_msg;
 216 
 217         /* I2C state machine */
 218         enum rk3x_i2c_state state;
 219         unsigned int processed;
 220         int error;
 221 };
 222 
 223 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
 224                               unsigned int offset)
 225 {
 226         writel(value, i2c->regs + offset);
 227 }
 228 
 229 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
 230 {
 231         return readl(i2c->regs + offset);
 232 }
 233 
 234 /* Reset all interrupt pending bits */
 235 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
 236 {
 237         i2c_writel(i2c, REG_INT_ALL, REG_IPD);
 238 }
 239 
 240 /**
 241  * Generate a START condition, which triggers a REG_INT_START interrupt.
 242  */
 243 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
 244 {
 245         u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
 246 
 247         i2c_writel(i2c, REG_INT_START, REG_IEN);
 248 
 249         /* enable adapter with correct mode, send START condition */
 250         val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
 251 
 252         /* if we want to react to NACK, set ACTACK bit */
 253         if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
 254                 val |= REG_CON_ACTACK;
 255 
 256         i2c_writel(i2c, val, REG_CON);
 257 }
 258 
 259 /**
 260  * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
 261  *
 262  * @error: Error code to return in rk3x_i2c_xfer
 263  */
 264 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
 265 {
 266         unsigned int ctrl;
 267 
 268         i2c->processed = 0;
 269         i2c->msg = NULL;
 270         i2c->error = error;
 271 
 272         if (i2c->is_last_msg) {
 273                 /* Enable stop interrupt */
 274                 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
 275 
 276                 i2c->state = STATE_STOP;
 277 
 278                 ctrl = i2c_readl(i2c, REG_CON);
 279                 ctrl |= REG_CON_STOP;
 280                 i2c_writel(i2c, ctrl, REG_CON);
 281         } else {
 282                 /* Signal rk3x_i2c_xfer to start the next message. */
 283                 i2c->busy = false;
 284                 i2c->state = STATE_IDLE;
 285 
 286                 /*
 287                  * The HW is actually not capable of REPEATED START. But we can
 288                  * get the intended effect by resetting its internal state
 289                  * and issuing an ordinary START.
 290                  */
 291                 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
 292                 i2c_writel(i2c, ctrl, REG_CON);
 293 
 294                 /* signal that we are finished with the current msg */
 295                 wake_up(&i2c->wait);
 296         }
 297 }
 298 
 299 /**
 300  * Setup a read according to i2c->msg
 301  */
 302 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
 303 {
 304         unsigned int len = i2c->msg->len - i2c->processed;
 305         u32 con;
 306 
 307         con = i2c_readl(i2c, REG_CON);
 308 
 309         /*
 310          * The hw can read up to 32 bytes at a time. If we need more than one
 311          * chunk, send an ACK after the last byte of the current chunk.
 312          */
 313         if (len > 32) {
 314                 len = 32;
 315                 con &= ~REG_CON_LASTACK;
 316         } else {
 317                 con |= REG_CON_LASTACK;
 318         }
 319 
 320         /* make sure we are in plain RX mode if we read a second chunk */
 321         if (i2c->processed != 0) {
 322                 con &= ~REG_CON_MOD_MASK;
 323                 con |= REG_CON_MOD(REG_CON_MOD_RX);
 324         }
 325 
 326         i2c_writel(i2c, con, REG_CON);
 327         i2c_writel(i2c, len, REG_MRXCNT);
 328 }
 329 
 330 /**
 331  * Fill the transmit buffer with data from i2c->msg
 332  */
 333 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
 334 {
 335         unsigned int i, j;
 336         u32 cnt = 0;
 337         u32 val;
 338         u8 byte;
 339 
 340         for (i = 0; i < 8; ++i) {
 341                 val = 0;
 342                 for (j = 0; j < 4; ++j) {
 343                         if ((i2c->processed == i2c->msg->len) && (cnt != 0))
 344                                 break;
 345 
 346                         if (i2c->processed == 0 && cnt == 0)
 347                                 byte = (i2c->addr & 0x7f) << 1;
 348                         else
 349                                 byte = i2c->msg->buf[i2c->processed++];
 350 
 351                         val |= byte << (j * 8);
 352                         cnt++;
 353                 }
 354 
 355                 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
 356 
 357                 if (i2c->processed == i2c->msg->len)
 358                         break;
 359         }
 360 
 361         i2c_writel(i2c, cnt, REG_MTXCNT);
 362 }
 363 
 364 
 365 /* IRQ handlers for individual states */
 366 
 367 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
 368 {
 369         if (!(ipd & REG_INT_START)) {
 370                 rk3x_i2c_stop(i2c, -EIO);
 371                 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
 372                 rk3x_i2c_clean_ipd(i2c);
 373                 return;
 374         }
 375 
 376         /* ack interrupt */
 377         i2c_writel(i2c, REG_INT_START, REG_IPD);
 378 
 379         /* disable start bit */
 380         i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
 381 
 382         /* enable appropriate interrupts and transition */
 383         if (i2c->mode == REG_CON_MOD_TX) {
 384                 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
 385                 i2c->state = STATE_WRITE;
 386                 rk3x_i2c_fill_transmit_buf(i2c);
 387         } else {
 388                 /* in any other case, we are going to be reading. */
 389                 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
 390                 i2c->state = STATE_READ;
 391                 rk3x_i2c_prepare_read(i2c);
 392         }
 393 }
 394 
 395 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
 396 {
 397         if (!(ipd & REG_INT_MBTF)) {
 398                 rk3x_i2c_stop(i2c, -EIO);
 399                 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
 400                 rk3x_i2c_clean_ipd(i2c);
 401                 return;
 402         }
 403 
 404         /* ack interrupt */
 405         i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
 406 
 407         /* are we finished? */
 408         if (i2c->processed == i2c->msg->len)
 409                 rk3x_i2c_stop(i2c, i2c->error);
 410         else
 411                 rk3x_i2c_fill_transmit_buf(i2c);
 412 }
 413 
 414 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
 415 {
 416         unsigned int i;
 417         unsigned int len = i2c->msg->len - i2c->processed;
 418         u32 uninitialized_var(val);
 419         u8 byte;
 420 
 421         /* we only care for MBRF here. */
 422         if (!(ipd & REG_INT_MBRF))
 423                 return;
 424 
 425         /* ack interrupt */
 426         i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
 427 
 428         /* Can only handle a maximum of 32 bytes at a time */
 429         if (len > 32)
 430                 len = 32;
 431 
 432         /* read the data from receive buffer */
 433         for (i = 0; i < len; ++i) {
 434                 if (i % 4 == 0)
 435                         val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
 436 
 437                 byte = (val >> ((i % 4) * 8)) & 0xff;
 438                 i2c->msg->buf[i2c->processed++] = byte;
 439         }
 440 
 441         /* are we finished? */
 442         if (i2c->processed == i2c->msg->len)
 443                 rk3x_i2c_stop(i2c, i2c->error);
 444         else
 445                 rk3x_i2c_prepare_read(i2c);
 446 }
 447 
 448 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
 449 {
 450         unsigned int con;
 451 
 452         if (!(ipd & REG_INT_STOP)) {
 453                 rk3x_i2c_stop(i2c, -EIO);
 454                 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
 455                 rk3x_i2c_clean_ipd(i2c);
 456                 return;
 457         }
 458 
 459         /* ack interrupt */
 460         i2c_writel(i2c, REG_INT_STOP, REG_IPD);
 461 
 462         /* disable STOP bit */
 463         con = i2c_readl(i2c, REG_CON);
 464         con &= ~REG_CON_STOP;
 465         i2c_writel(i2c, con, REG_CON);
 466 
 467         i2c->busy = false;
 468         i2c->state = STATE_IDLE;
 469 
 470         /* signal rk3x_i2c_xfer that we are finished */
 471         wake_up(&i2c->wait);
 472 }
 473 
 474 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
 475 {
 476         struct rk3x_i2c *i2c = dev_id;
 477         unsigned int ipd;
 478 
 479         spin_lock(&i2c->lock);
 480 
 481         ipd = i2c_readl(i2c, REG_IPD);
 482         if (i2c->state == STATE_IDLE) {
 483                 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
 484                 rk3x_i2c_clean_ipd(i2c);
 485                 goto out;
 486         }
 487 
 488         dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
 489 
 490         /* Clean interrupt bits we don't care about */
 491         ipd &= ~(REG_INT_BRF | REG_INT_BTF);
 492 
 493         if (ipd & REG_INT_NAKRCV) {
 494                 /*
 495                  * We got a NACK in the last operation. Depending on whether
 496                  * IGNORE_NAK is set, we have to stop the operation and report
 497                  * an error.
 498                  */
 499                 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
 500 
 501                 ipd &= ~REG_INT_NAKRCV;
 502 
 503                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
 504                         rk3x_i2c_stop(i2c, -ENXIO);
 505         }
 506 
 507         /* is there anything left to handle? */
 508         if ((ipd & REG_INT_ALL) == 0)
 509                 goto out;
 510 
 511         switch (i2c->state) {
 512         case STATE_START:
 513                 rk3x_i2c_handle_start(i2c, ipd);
 514                 break;
 515         case STATE_WRITE:
 516                 rk3x_i2c_handle_write(i2c, ipd);
 517                 break;
 518         case STATE_READ:
 519                 rk3x_i2c_handle_read(i2c, ipd);
 520                 break;
 521         case STATE_STOP:
 522                 rk3x_i2c_handle_stop(i2c, ipd);
 523                 break;
 524         case STATE_IDLE:
 525                 break;
 526         }
 527 
 528 out:
 529         spin_unlock(&i2c->lock);
 530         return IRQ_HANDLED;
 531 }
 532 
 533 /**
 534  * Get timing values of I2C specification
 535  *
 536  * @speed: Desired SCL frequency
 537  *
 538  * Returns: Matched i2c spec values.
 539  */
 540 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
 541 {
 542         if (speed <= 100000)
 543                 return &standard_mode_spec;
 544         else if (speed <= 400000)
 545                 return &fast_mode_spec;
 546         else
 547                 return &fast_mode_plus_spec;
 548 }
 549 
 550 /**
 551  * Calculate divider values for desired SCL frequency
 552  *
 553  * @clk_rate: I2C input clock rate
 554  * @t: Known I2C timing information
 555  * @t_calc: Caculated rk3x private timings that would be written into regs
 556  *
 557  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
 558  * a best-effort divider value is returned in divs. If the target rate is
 559  * too high, we silently use the highest possible rate.
 560  */
 561 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
 562                                     struct i2c_timings *t,
 563                                     struct rk3x_i2c_calced_timings *t_calc)
 564 {
 565         unsigned long min_low_ns, min_high_ns;
 566         unsigned long max_low_ns, min_total_ns;
 567 
 568         unsigned long clk_rate_khz, scl_rate_khz;
 569 
 570         unsigned long min_low_div, min_high_div;
 571         unsigned long max_low_div;
 572 
 573         unsigned long min_div_for_hold, min_total_div;
 574         unsigned long extra_div, extra_low_div, ideal_low_div;
 575 
 576         unsigned long data_hold_buffer_ns = 50;
 577         const struct i2c_spec_values *spec;
 578         int ret = 0;
 579 
 580         /* Only support standard-mode and fast-mode */
 581         if (WARN_ON(t->bus_freq_hz > 400000))
 582                 t->bus_freq_hz = 400000;
 583 
 584         /* prevent scl_rate_khz from becoming 0 */
 585         if (WARN_ON(t->bus_freq_hz < 1000))
 586                 t->bus_freq_hz = 1000;
 587 
 588         /*
 589          * min_low_ns:  The minimum number of ns we need to hold low to
 590          *              meet I2C specification, should include fall time.
 591          * min_high_ns: The minimum number of ns we need to hold high to
 592          *              meet I2C specification, should include rise time.
 593          * max_low_ns:  The maximum number of ns we can hold low to meet
 594          *              I2C specification.
 595          *
 596          * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
 597          *       This is because the i2c host on Rockchip holds the data line
 598          *       for half the low time.
 599          */
 600         spec = rk3x_i2c_get_spec(t->bus_freq_hz);
 601         min_high_ns = t->scl_rise_ns + spec->min_high_ns;
 602 
 603         /*
 604          * Timings for repeated start:
 605          * - controller appears to drop SDA at .875x (7/8) programmed clk high.
 606          * - controller appears to keep SCL high for 2x programmed clk high.
 607          *
 608          * We need to account for those rules in picking our "high" time so
 609          * we meet tSU;STA and tHD;STA times.
 610          */
 611         min_high_ns = max(min_high_ns, DIV_ROUND_UP(
 612                 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
 613         min_high_ns = max(min_high_ns, DIV_ROUND_UP(
 614                 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
 615                 spec->min_high_ns), 2));
 616 
 617         min_low_ns = t->scl_fall_ns + spec->min_low_ns;
 618         max_low_ns =  spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
 619         min_total_ns = min_low_ns + min_high_ns;
 620 
 621         /* Adjust to avoid overflow */
 622         clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
 623         scl_rate_khz = t->bus_freq_hz / 1000;
 624 
 625         /*
 626          * We need the total div to be >= this number
 627          * so we don't clock too fast.
 628          */
 629         min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
 630 
 631         /* These are the min dividers needed for min hold times. */
 632         min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
 633         min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
 634         min_div_for_hold = (min_low_div + min_high_div);
 635 
 636         /*
 637          * This is the maximum divider so we don't go over the maximum.
 638          * We don't round up here (we round down) since this is a maximum.
 639          */
 640         max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
 641 
 642         if (min_low_div > max_low_div) {
 643                 WARN_ONCE(true,
 644                           "Conflicting, min_low_div %lu, max_low_div %lu\n",
 645                           min_low_div, max_low_div);
 646                 max_low_div = min_low_div;
 647         }
 648 
 649         if (min_div_for_hold > min_total_div) {
 650                 /*
 651                  * Time needed to meet hold requirements is important.
 652                  * Just use that.
 653                  */
 654                 t_calc->div_low = min_low_div;
 655                 t_calc->div_high = min_high_div;
 656         } else {
 657                 /*
 658                  * We've got to distribute some time among the low and high
 659                  * so we don't run too fast.
 660                  */
 661                 extra_div = min_total_div - min_div_for_hold;
 662 
 663                 /*
 664                  * We'll try to split things up perfectly evenly,
 665                  * biasing slightly towards having a higher div
 666                  * for low (spend more time low).
 667                  */
 668                 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
 669                                              scl_rate_khz * 8 * min_total_ns);
 670 
 671                 /* Don't allow it to go over the maximum */
 672                 if (ideal_low_div > max_low_div)
 673                         ideal_low_div = max_low_div;
 674 
 675                 /*
 676                  * Handle when the ideal low div is going to take up
 677                  * more than we have.
 678                  */
 679                 if (ideal_low_div > min_low_div + extra_div)
 680                         ideal_low_div = min_low_div + extra_div;
 681 
 682                 /* Give low the "ideal" and give high whatever extra is left */
 683                 extra_low_div = ideal_low_div - min_low_div;
 684                 t_calc->div_low = ideal_low_div;
 685                 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
 686         }
 687 
 688         /*
 689          * Adjust to the fact that the hardware has an implicit "+1".
 690          * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
 691          */
 692         t_calc->div_low--;
 693         t_calc->div_high--;
 694 
 695         /* Give the tuning value 0, that would not update con register */
 696         t_calc->tuning = 0;
 697         /* Maximum divider supported by hw is 0xffff */
 698         if (t_calc->div_low > 0xffff) {
 699                 t_calc->div_low = 0xffff;
 700                 ret = -EINVAL;
 701         }
 702 
 703         if (t_calc->div_high > 0xffff) {
 704                 t_calc->div_high = 0xffff;
 705                 ret = -EINVAL;
 706         }
 707 
 708         return ret;
 709 }
 710 
 711 /**
 712  * Calculate timing values for desired SCL frequency
 713  *
 714  * @clk_rate: I2C input clock rate
 715  * @t: Known I2C timing information
 716  * @t_calc: Caculated rk3x private timings that would be written into regs
 717  *
 718  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
 719  * a best-effort divider value is returned in divs. If the target rate is
 720  * too high, we silently use the highest possible rate.
 721  * The following formulas are v1's method to calculate timings.
 722  *
 723  * l = divl + 1;
 724  * h = divh + 1;
 725  * s = sda_update_config + 1;
 726  * u = start_setup_config + 1;
 727  * p = stop_setup_config + 1;
 728  * T = Tclk_i2c;
 729  *
 730  * tHigh = 8 * h * T;
 731  * tLow = 8 * l * T;
 732  *
 733  * tHD;sda = (l * s + 1) * T;
 734  * tSU;sda = [(8 - s) * l + 1] * T;
 735  * tI2C = 8 * (l + h) * T;
 736  *
 737  * tSU;sta = (8h * u + 1) * T;
 738  * tHD;sta = [8h * (u + 1) - 1] * T;
 739  * tSU;sto = (8h * p + 1) * T;
 740  */
 741 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
 742                                     struct i2c_timings *t,
 743                                     struct rk3x_i2c_calced_timings *t_calc)
 744 {
 745         unsigned long min_low_ns, min_high_ns;
 746         unsigned long min_setup_start_ns, min_setup_data_ns;
 747         unsigned long min_setup_stop_ns, max_hold_data_ns;
 748 
 749         unsigned long clk_rate_khz, scl_rate_khz;
 750 
 751         unsigned long min_low_div, min_high_div;
 752 
 753         unsigned long min_div_for_hold, min_total_div;
 754         unsigned long extra_div, extra_low_div;
 755         unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
 756 
 757         const struct i2c_spec_values *spec;
 758         int ret = 0;
 759 
 760         /* Support standard-mode, fast-mode and fast-mode plus */
 761         if (WARN_ON(t->bus_freq_hz > 1000000))
 762                 t->bus_freq_hz = 1000000;
 763 
 764         /* prevent scl_rate_khz from becoming 0 */
 765         if (WARN_ON(t->bus_freq_hz < 1000))
 766                 t->bus_freq_hz = 1000;
 767 
 768         /*
 769          * min_low_ns: The minimum number of ns we need to hold low to
 770          *             meet I2C specification, should include fall time.
 771          * min_high_ns: The minimum number of ns we need to hold high to
 772          *              meet I2C specification, should include rise time.
 773          */
 774         spec = rk3x_i2c_get_spec(t->bus_freq_hz);
 775 
 776         /* calculate min-divh and min-divl */
 777         clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
 778         scl_rate_khz = t->bus_freq_hz / 1000;
 779         min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
 780 
 781         min_high_ns = t->scl_rise_ns + spec->min_high_ns;
 782         min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
 783 
 784         min_low_ns = t->scl_fall_ns + spec->min_low_ns;
 785         min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
 786 
 787         /*
 788          * Final divh and divl must be greater than 0, otherwise the
 789          * hardware would not output the i2c clk.
 790          */
 791         min_high_div = (min_high_div < 1) ? 2 : min_high_div;
 792         min_low_div = (min_low_div < 1) ? 2 : min_low_div;
 793 
 794         /* These are the min dividers needed for min hold times. */
 795         min_div_for_hold = (min_low_div + min_high_div);
 796 
 797         /*
 798          * This is the maximum divider so we don't go over the maximum.
 799          * We don't round up here (we round down) since this is a maximum.
 800          */
 801         if (min_div_for_hold >= min_total_div) {
 802                 /*
 803                  * Time needed to meet hold requirements is important.
 804                  * Just use that.
 805                  */
 806                 t_calc->div_low = min_low_div;
 807                 t_calc->div_high = min_high_div;
 808         } else {
 809                 /*
 810                  * We've got to distribute some time among the low and high
 811                  * so we don't run too fast.
 812                  * We'll try to split things up by the scale of min_low_div and
 813                  * min_high_div, biasing slightly towards having a higher div
 814                  * for low (spend more time low).
 815                  */
 816                 extra_div = min_total_div - min_div_for_hold;
 817                 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
 818                                              min_div_for_hold);
 819 
 820                 t_calc->div_low = min_low_div + extra_low_div;
 821                 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
 822         }
 823 
 824         /*
 825          * calculate sda data hold count by the rules, data_upd_st:3
 826          * is a appropriate value to reduce calculated times.
 827          */
 828         for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
 829                 max_hold_data_ns =  DIV_ROUND_UP((sda_update_cfg
 830                                                  * (t_calc->div_low) + 1)
 831                                                  * 1000000, clk_rate_khz);
 832                 min_setup_data_ns =  DIV_ROUND_UP(((8 - sda_update_cfg)
 833                                                  * (t_calc->div_low) + 1)
 834                                                  * 1000000, clk_rate_khz);
 835                 if ((max_hold_data_ns < spec->max_data_hold_ns) &&
 836                     (min_setup_data_ns > spec->min_data_setup_ns))
 837                         break;
 838         }
 839 
 840         /* calculate setup start config */
 841         min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
 842         stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
 843                            - 1000000, 8 * 1000000 * (t_calc->div_high));
 844 
 845         /* calculate setup stop config */
 846         min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
 847         stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
 848                            - 1000000, 8 * 1000000 * (t_calc->div_high));
 849 
 850         t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
 851                          REG_CON_STA_CFG(--stp_sta_cfg) |
 852                          REG_CON_STO_CFG(--stp_sto_cfg);
 853 
 854         t_calc->div_low--;
 855         t_calc->div_high--;
 856 
 857         /* Maximum divider supported by hw is 0xffff */
 858         if (t_calc->div_low > 0xffff) {
 859                 t_calc->div_low = 0xffff;
 860                 ret = -EINVAL;
 861         }
 862 
 863         if (t_calc->div_high > 0xffff) {
 864                 t_calc->div_high = 0xffff;
 865                 ret = -EINVAL;
 866         }
 867 
 868         return ret;
 869 }
 870 
 871 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
 872 {
 873         struct i2c_timings *t = &i2c->t;
 874         struct rk3x_i2c_calced_timings calc;
 875         u64 t_low_ns, t_high_ns;
 876         unsigned long flags;
 877         u32 val;
 878         int ret;
 879 
 880         ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
 881         WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
 882 
 883         clk_enable(i2c->pclk);
 884 
 885         spin_lock_irqsave(&i2c->lock, flags);
 886         val = i2c_readl(i2c, REG_CON);
 887         val &= ~REG_CON_TUNING_MASK;
 888         val |= calc.tuning;
 889         i2c_writel(i2c, val, REG_CON);
 890         i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
 891                    REG_CLKDIV);
 892         spin_unlock_irqrestore(&i2c->lock, flags);
 893 
 894         clk_disable(i2c->pclk);
 895 
 896         t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate);
 897         t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000,
 898                             clk_rate);
 899         dev_dbg(i2c->dev,
 900                 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
 901                 clk_rate / 1000,
 902                 1000000000 / t->bus_freq_hz,
 903                 t_low_ns, t_high_ns);
 904 }
 905 
 906 /**
 907  * rk3x_i2c_clk_notifier_cb - Clock rate change callback
 908  * @nb:         Pointer to notifier block
 909  * @event:      Notification reason
 910  * @data:       Pointer to notification data object
 911  *
 912  * The callback checks whether a valid bus frequency can be generated after the
 913  * change. If so, the change is acknowledged, otherwise the change is aborted.
 914  * New dividers are written to the HW in the pre- or post change notification
 915  * depending on the scaling direction.
 916  *
 917  * Code adapted from i2c-cadence.c.
 918  *
 919  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
 920  *              to acknowledge the change, NOTIFY_DONE if the notification is
 921  *              considered irrelevant.
 922  */
 923 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
 924                                     event, void *data)
 925 {
 926         struct clk_notifier_data *ndata = data;
 927         struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
 928         struct rk3x_i2c_calced_timings calc;
 929 
 930         switch (event) {
 931         case PRE_RATE_CHANGE:
 932                 /*
 933                  * Try the calculation (but don't store the result) ahead of
 934                  * time to see if we need to block the clock change.  Timings
 935                  * shouldn't actually take effect until rk3x_i2c_adapt_div().
 936                  */
 937                 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
 938                                                 &calc) != 0)
 939                         return NOTIFY_STOP;
 940 
 941                 /* scale up */
 942                 if (ndata->new_rate > ndata->old_rate)
 943                         rk3x_i2c_adapt_div(i2c, ndata->new_rate);
 944 
 945                 return NOTIFY_OK;
 946         case POST_RATE_CHANGE:
 947                 /* scale down */
 948                 if (ndata->new_rate < ndata->old_rate)
 949                         rk3x_i2c_adapt_div(i2c, ndata->new_rate);
 950                 return NOTIFY_OK;
 951         case ABORT_RATE_CHANGE:
 952                 /* scale up */
 953                 if (ndata->new_rate > ndata->old_rate)
 954                         rk3x_i2c_adapt_div(i2c, ndata->old_rate);
 955                 return NOTIFY_OK;
 956         default:
 957                 return NOTIFY_DONE;
 958         }
 959 }
 960 
 961 /**
 962  * Setup I2C registers for an I2C operation specified by msgs, num.
 963  *
 964  * Must be called with i2c->lock held.
 965  *
 966  * @msgs: I2C msgs to process
 967  * @num: Number of msgs
 968  *
 969  * returns: Number of I2C msgs processed or negative in case of error
 970  */
 971 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
 972 {
 973         u32 addr = (msgs[0].addr & 0x7f) << 1;
 974         int ret = 0;
 975 
 976         /*
 977          * The I2C adapter can issue a small (len < 4) write packet before
 978          * reading. This speeds up SMBus-style register reads.
 979          * The MRXADDR/MRXRADDR hold the slave address and the slave register
 980          * address in this case.
 981          */
 982 
 983         if (num >= 2 && msgs[0].len < 4 &&
 984             !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 985                 u32 reg_addr = 0;
 986                 int i;
 987 
 988                 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
 989                         addr >> 1);
 990 
 991                 /* Fill MRXRADDR with the register address(es) */
 992                 for (i = 0; i < msgs[0].len; ++i) {
 993                         reg_addr |= msgs[0].buf[i] << (i * 8);
 994                         reg_addr |= REG_MRXADDR_VALID(i);
 995                 }
 996 
 997                 /* msgs[0] is handled by hw. */
 998                 i2c->msg = &msgs[1];
 999 
1000                 i2c->mode = REG_CON_MOD_REGISTER_TX;
1001 
1002                 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1003                 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
1004 
1005                 ret = 2;
1006         } else {
1007                 /*
1008                  * We'll have to do it the boring way and process the msgs
1009                  * one-by-one.
1010                  */
1011 
1012                 if (msgs[0].flags & I2C_M_RD) {
1013                         addr |= 1; /* set read bit */
1014 
1015                         /*
1016                          * We have to transmit the slave addr first. Use
1017                          * MOD_REGISTER_TX for that purpose.
1018                          */
1019                         i2c->mode = REG_CON_MOD_REGISTER_TX;
1020                         i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
1021                                    REG_MRXADDR);
1022                         i2c_writel(i2c, 0, REG_MRXRADDR);
1023                 } else {
1024                         i2c->mode = REG_CON_MOD_TX;
1025                 }
1026 
1027                 i2c->msg = &msgs[0];
1028 
1029                 ret = 1;
1030         }
1031 
1032         i2c->addr = msgs[0].addr;
1033         i2c->busy = true;
1034         i2c->state = STATE_START;
1035         i2c->processed = 0;
1036         i2c->error = 0;
1037 
1038         rk3x_i2c_clean_ipd(i2c);
1039 
1040         return ret;
1041 }
1042 
1043 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1044                          struct i2c_msg *msgs, int num)
1045 {
1046         struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1047         unsigned long timeout, flags;
1048         u32 val;
1049         int ret = 0;
1050         int i;
1051 
1052         spin_lock_irqsave(&i2c->lock, flags);
1053 
1054         clk_enable(i2c->clk);
1055         clk_enable(i2c->pclk);
1056 
1057         i2c->is_last_msg = false;
1058 
1059         /*
1060          * Process msgs. We can handle more than one message at once (see
1061          * rk3x_i2c_setup()).
1062          */
1063         for (i = 0; i < num; i += ret) {
1064                 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1065 
1066                 if (ret < 0) {
1067                         dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1068                         break;
1069                 }
1070 
1071                 if (i + ret >= num)
1072                         i2c->is_last_msg = true;
1073 
1074                 spin_unlock_irqrestore(&i2c->lock, flags);
1075 
1076                 rk3x_i2c_start(i2c);
1077 
1078                 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
1079                                              msecs_to_jiffies(WAIT_TIMEOUT));
1080 
1081                 spin_lock_irqsave(&i2c->lock, flags);
1082 
1083                 if (timeout == 0) {
1084                         dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
1085                                 i2c_readl(i2c, REG_IPD), i2c->state);
1086 
1087                         /* Force a STOP condition without interrupt */
1088                         i2c_writel(i2c, 0, REG_IEN);
1089                         val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1090                         val |= REG_CON_EN | REG_CON_STOP;
1091                         i2c_writel(i2c, val, REG_CON);
1092 
1093                         i2c->state = STATE_IDLE;
1094 
1095                         ret = -ETIMEDOUT;
1096                         break;
1097                 }
1098 
1099                 if (i2c->error) {
1100                         ret = i2c->error;
1101                         break;
1102                 }
1103         }
1104 
1105         clk_disable(i2c->pclk);
1106         clk_disable(i2c->clk);
1107 
1108         spin_unlock_irqrestore(&i2c->lock, flags);
1109 
1110         return ret < 0 ? ret : num;
1111 }
1112 
1113 static __maybe_unused int rk3x_i2c_resume(struct device *dev)
1114 {
1115         struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1116 
1117         rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1118 
1119         return 0;
1120 }
1121 
1122 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1123 {
1124         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1125 }
1126 
1127 static const struct i2c_algorithm rk3x_i2c_algorithm = {
1128         .master_xfer            = rk3x_i2c_xfer,
1129         .functionality          = rk3x_i2c_func,
1130 };
1131 
1132 static const struct rk3x_i2c_soc_data rv1108_soc_data = {
1133         .grf_offset = -1,
1134         .calc_timings = rk3x_i2c_v1_calc_timings,
1135 };
1136 
1137 static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1138         .grf_offset = 0x154,
1139         .calc_timings = rk3x_i2c_v0_calc_timings,
1140 };
1141 
1142 static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1143         .grf_offset = 0x0a4,
1144         .calc_timings = rk3x_i2c_v0_calc_timings,
1145 };
1146 
1147 static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1148         .grf_offset = -1,
1149         .calc_timings = rk3x_i2c_v0_calc_timings,
1150 };
1151 
1152 static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1153         .grf_offset = -1,
1154         .calc_timings = rk3x_i2c_v0_calc_timings,
1155 };
1156 
1157 static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1158         .grf_offset = -1,
1159         .calc_timings = rk3x_i2c_v1_calc_timings,
1160 };
1161 
1162 static const struct of_device_id rk3x_i2c_match[] = {
1163         {
1164                 .compatible = "rockchip,rv1108-i2c",
1165                 .data = &rv1108_soc_data
1166         },
1167         {
1168                 .compatible = "rockchip,rk3066-i2c",
1169                 .data = &rk3066_soc_data
1170         },
1171         {
1172                 .compatible = "rockchip,rk3188-i2c",
1173                 .data = &rk3188_soc_data
1174         },
1175         {
1176                 .compatible = "rockchip,rk3228-i2c",
1177                 .data = &rk3228_soc_data
1178         },
1179         {
1180                 .compatible = "rockchip,rk3288-i2c",
1181                 .data = &rk3288_soc_data
1182         },
1183         {
1184                 .compatible = "rockchip,rk3399-i2c",
1185                 .data = &rk3399_soc_data
1186         },
1187         {},
1188 };
1189 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1190 
1191 static int rk3x_i2c_probe(struct platform_device *pdev)
1192 {
1193         struct device_node *np = pdev->dev.of_node;
1194         const struct of_device_id *match;
1195         struct rk3x_i2c *i2c;
1196         struct resource *mem;
1197         int ret = 0;
1198         int bus_nr;
1199         u32 value;
1200         int irq;
1201         unsigned long clk_rate;
1202 
1203         i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1204         if (!i2c)
1205                 return -ENOMEM;
1206 
1207         match = of_match_node(rk3x_i2c_match, np);
1208         i2c->soc_data = match->data;
1209 
1210         /* use common interface to get I2C timing properties */
1211         i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1212 
1213         strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1214         i2c->adap.owner = THIS_MODULE;
1215         i2c->adap.algo = &rk3x_i2c_algorithm;
1216         i2c->adap.retries = 3;
1217         i2c->adap.dev.of_node = np;
1218         i2c->adap.algo_data = i2c;
1219         i2c->adap.dev.parent = &pdev->dev;
1220 
1221         i2c->dev = &pdev->dev;
1222 
1223         spin_lock_init(&i2c->lock);
1224         init_waitqueue_head(&i2c->wait);
1225 
1226         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1227         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
1228         if (IS_ERR(i2c->regs))
1229                 return PTR_ERR(i2c->regs);
1230 
1231         /* Try to set the I2C adapter number from dt */
1232         bus_nr = of_alias_get_id(np, "i2c");
1233 
1234         /*
1235          * Switch to new interface if the SoC also offers the old one.
1236          * The control bit is located in the GRF register space.
1237          */
1238         if (i2c->soc_data->grf_offset >= 0) {
1239                 struct regmap *grf;
1240 
1241                 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1242                 if (IS_ERR(grf)) {
1243                         dev_err(&pdev->dev,
1244                                 "rk3x-i2c needs 'rockchip,grf' property\n");
1245                         return PTR_ERR(grf);
1246                 }
1247 
1248                 if (bus_nr < 0) {
1249                         dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1250                         return -EINVAL;
1251                 }
1252 
1253                 /* 27+i: write mask, 11+i: value */
1254                 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1255 
1256                 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
1257                 if (ret != 0) {
1258                         dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1259                         return ret;
1260                 }
1261         }
1262 
1263         /* IRQ setup */
1264         irq = platform_get_irq(pdev, 0);
1265         if (irq < 0) {
1266                 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
1267                 return irq;
1268         }
1269 
1270         ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1271                                0, dev_name(&pdev->dev), i2c);
1272         if (ret < 0) {
1273                 dev_err(&pdev->dev, "cannot request IRQ\n");
1274                 return ret;
1275         }
1276 
1277         platform_set_drvdata(pdev, i2c);
1278 
1279         if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1280                 /* Only one clock to use for bus clock and peripheral clock */
1281                 i2c->clk = devm_clk_get(&pdev->dev, NULL);
1282                 i2c->pclk = i2c->clk;
1283         } else {
1284                 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1285                 i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1286         }
1287 
1288         if (IS_ERR(i2c->clk)) {
1289                 ret = PTR_ERR(i2c->clk);
1290                 if (ret != -EPROBE_DEFER)
1291                         dev_err(&pdev->dev, "Can't get bus clk: %d\n", ret);
1292                 return ret;
1293         }
1294         if (IS_ERR(i2c->pclk)) {
1295                 ret = PTR_ERR(i2c->pclk);
1296                 if (ret != -EPROBE_DEFER)
1297                         dev_err(&pdev->dev, "Can't get periph clk: %d\n", ret);
1298                 return ret;
1299         }
1300 
1301         ret = clk_prepare(i2c->clk);
1302         if (ret < 0) {
1303                 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1304                 return ret;
1305         }
1306         ret = clk_prepare(i2c->pclk);
1307         if (ret < 0) {
1308                 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1309                 goto err_clk;
1310         }
1311 
1312         i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1313         ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1314         if (ret != 0) {
1315                 dev_err(&pdev->dev, "Unable to register clock notifier\n");
1316                 goto err_pclk;
1317         }
1318 
1319         clk_rate = clk_get_rate(i2c->clk);
1320         rk3x_i2c_adapt_div(i2c, clk_rate);
1321 
1322         ret = i2c_add_adapter(&i2c->adap);
1323         if (ret < 0)
1324                 goto err_clk_notifier;
1325 
1326         return 0;
1327 
1328 err_clk_notifier:
1329         clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1330 err_pclk:
1331         clk_unprepare(i2c->pclk);
1332 err_clk:
1333         clk_unprepare(i2c->clk);
1334         return ret;
1335 }
1336 
1337 static int rk3x_i2c_remove(struct platform_device *pdev)
1338 {
1339         struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1340 
1341         i2c_del_adapter(&i2c->adap);
1342 
1343         clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1344         clk_unprepare(i2c->pclk);
1345         clk_unprepare(i2c->clk);
1346 
1347         return 0;
1348 }
1349 
1350 static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume);
1351 
1352 static struct platform_driver rk3x_i2c_driver = {
1353         .probe   = rk3x_i2c_probe,
1354         .remove  = rk3x_i2c_remove,
1355         .driver  = {
1356                 .name  = "rk3x-i2c",
1357                 .of_match_table = rk3x_i2c_match,
1358                 .pm = &rk3x_i2c_pm_ops,
1359         },
1360 };
1361 
1362 module_platform_driver(rk3x_i2c_driver);
1363 
1364 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1365 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1366 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/i2c/busses/i2c-rk3x.c

DEFINITIONS
