drivers/i2c/busses/i2c-st.c

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This source file includes following definitions.
st_i2c_set_bits
st_i2c_clr_bits
st_i2c_flush_rx_fifo
st_i2c_soft_reset
st_i2c_hw_config
st_i2c_recover_bus
st_i2c_wait_free_bus
st_i2c_write_tx_fifo
st_i2c_wr_fill_tx_fifo
st_i2c_rd_fill_tx_fifo
st_i2c_read_rx_fifo
st_i2c_terminate_xfer
st_i2c_handle_write
st_i2c_handle_read
st_i2c_isr_thread
st_i2c_xfer_msg
st_i2c_xfer
st_i2c_suspend
st_i2c_resume
st_i2c_func
st_i2c_of_get_deglitch
st_i2c_probe
st_i2c_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 STMicroelectronics
   4  *
   5  * I2C master mode controller driver, used in STMicroelectronics devices.
   6  *
   7  * Author: Maxime Coquelin <maxime.coquelin@st.com>
   8  */
   9 
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/i2c.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 
  23 /* SSC registers */
  24 #define SSC_BRG                         0x000
  25 #define SSC_TBUF                        0x004
  26 #define SSC_RBUF                        0x008
  27 #define SSC_CTL                         0x00C
  28 #define SSC_IEN                         0x010
  29 #define SSC_STA                         0x014
  30 #define SSC_I2C                         0x018
  31 #define SSC_SLAD                        0x01C
  32 #define SSC_REP_START_HOLD              0x020
  33 #define SSC_START_HOLD                  0x024
  34 #define SSC_REP_START_SETUP             0x028
  35 #define SSC_DATA_SETUP                  0x02C
  36 #define SSC_STOP_SETUP                  0x030
  37 #define SSC_BUS_FREE                    0x034
  38 #define SSC_TX_FSTAT                    0x038
  39 #define SSC_RX_FSTAT                    0x03C
  40 #define SSC_PRE_SCALER_BRG              0x040
  41 #define SSC_CLR                         0x080
  42 #define SSC_NOISE_SUPP_WIDTH            0x100
  43 #define SSC_PRSCALER                    0x104
  44 #define SSC_NOISE_SUPP_WIDTH_DATAOUT    0x108
  45 #define SSC_PRSCALER_DATAOUT            0x10c
  46 
  47 /* SSC Control */
  48 #define SSC_CTL_DATA_WIDTH_9            0x8
  49 #define SSC_CTL_DATA_WIDTH_MSK          0xf
  50 #define SSC_CTL_BM                      0xf
  51 #define SSC_CTL_HB                      BIT(4)
  52 #define SSC_CTL_PH                      BIT(5)
  53 #define SSC_CTL_PO                      BIT(6)
  54 #define SSC_CTL_SR                      BIT(7)
  55 #define SSC_CTL_MS                      BIT(8)
  56 #define SSC_CTL_EN                      BIT(9)
  57 #define SSC_CTL_LPB                     BIT(10)
  58 #define SSC_CTL_EN_TX_FIFO              BIT(11)
  59 #define SSC_CTL_EN_RX_FIFO              BIT(12)
  60 #define SSC_CTL_EN_CLST_RX              BIT(13)
  61 
  62 /* SSC Interrupt Enable */
  63 #define SSC_IEN_RIEN                    BIT(0)
  64 #define SSC_IEN_TIEN                    BIT(1)
  65 #define SSC_IEN_TEEN                    BIT(2)
  66 #define SSC_IEN_REEN                    BIT(3)
  67 #define SSC_IEN_PEEN                    BIT(4)
  68 #define SSC_IEN_AASEN                   BIT(6)
  69 #define SSC_IEN_STOPEN                  BIT(7)
  70 #define SSC_IEN_ARBLEN                  BIT(8)
  71 #define SSC_IEN_NACKEN                  BIT(10)
  72 #define SSC_IEN_REPSTRTEN               BIT(11)
  73 #define SSC_IEN_TX_FIFO_HALF            BIT(12)
  74 #define SSC_IEN_RX_FIFO_HALF_FULL       BIT(14)
  75 
  76 /* SSC Status */
  77 #define SSC_STA_RIR                     BIT(0)
  78 #define SSC_STA_TIR                     BIT(1)
  79 #define SSC_STA_TE                      BIT(2)
  80 #define SSC_STA_RE                      BIT(3)
  81 #define SSC_STA_PE                      BIT(4)
  82 #define SSC_STA_CLST                    BIT(5)
  83 #define SSC_STA_AAS                     BIT(6)
  84 #define SSC_STA_STOP                    BIT(7)
  85 #define SSC_STA_ARBL                    BIT(8)
  86 #define SSC_STA_BUSY                    BIT(9)
  87 #define SSC_STA_NACK                    BIT(10)
  88 #define SSC_STA_REPSTRT                 BIT(11)
  89 #define SSC_STA_TX_FIFO_HALF            BIT(12)
  90 #define SSC_STA_TX_FIFO_FULL            BIT(13)
  91 #define SSC_STA_RX_FIFO_HALF            BIT(14)
  92 
  93 /* SSC I2C Control */
  94 #define SSC_I2C_I2CM                    BIT(0)
  95 #define SSC_I2C_STRTG                   BIT(1)
  96 #define SSC_I2C_STOPG                   BIT(2)
  97 #define SSC_I2C_ACKG                    BIT(3)
  98 #define SSC_I2C_AD10                    BIT(4)
  99 #define SSC_I2C_TXENB                   BIT(5)
 100 #define SSC_I2C_REPSTRTG                BIT(11)
 101 #define SSC_I2C_SLAVE_DISABLE           BIT(12)
 102 
 103 /* SSC Tx FIFO Status */
 104 #define SSC_TX_FSTAT_STATUS             0x07
 105 
 106 /* SSC Rx FIFO Status */
 107 #define SSC_RX_FSTAT_STATUS             0x07
 108 
 109 /* SSC Clear bit operation */
 110 #define SSC_CLR_SSCAAS                  BIT(6)
 111 #define SSC_CLR_SSCSTOP                 BIT(7)
 112 #define SSC_CLR_SSCARBL                 BIT(8)
 113 #define SSC_CLR_NACK                    BIT(10)
 114 #define SSC_CLR_REPSTRT                 BIT(11)
 115 
 116 /* SSC Clock Prescaler */
 117 #define SSC_PRSC_VALUE                  0x0f
 118 
 119 
 120 #define SSC_TXFIFO_SIZE                 0x8
 121 #define SSC_RXFIFO_SIZE                 0x8
 122 
 123 enum st_i2c_mode {
 124         I2C_MODE_STANDARD,
 125         I2C_MODE_FAST,
 126         I2C_MODE_END,
 127 };
 128 
 129 /**
 130  * struct st_i2c_timings - per-Mode tuning parameters
 131  * @rate: I2C bus rate
 132  * @rep_start_hold: I2C repeated start hold time requirement
 133  * @rep_start_setup: I2C repeated start set up time requirement
 134  * @start_hold: I2C start hold time requirement
 135  * @data_setup_time: I2C data set up time requirement
 136  * @stop_setup_time: I2C stop set up time requirement
 137  * @bus_free_time: I2C bus free time requirement
 138  * @sda_pulse_min_limit: I2C SDA pulse mini width limit
 139  */
 140 struct st_i2c_timings {
 141         u32 rate;
 142         u32 rep_start_hold;
 143         u32 rep_start_setup;
 144         u32 start_hold;
 145         u32 data_setup_time;
 146         u32 stop_setup_time;
 147         u32 bus_free_time;
 148         u32 sda_pulse_min_limit;
 149 };
 150 
 151 /**
 152  * struct st_i2c_client - client specific data
 153  * @addr: 8-bit slave addr, including r/w bit
 154  * @count: number of bytes to be transfered
 155  * @xfered: number of bytes already transferred
 156  * @buf: data buffer
 157  * @result: result of the transfer
 158  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 159  */
 160 struct st_i2c_client {
 161         u8      addr;
 162         u32     count;
 163         u32     xfered;
 164         u8      *buf;
 165         int     result;
 166         bool    stop;
 167 };
 168 
 169 /**
 170  * struct st_i2c_dev - private data of the controller
 171  * @adap: I2C adapter for this controller
 172  * @dev: device for this controller
 173  * @base: virtual memory area
 174  * @complete: completion of I2C message
 175  * @irq: interrupt line for th controller
 176  * @clk: hw ssc block clock
 177  * @mode: I2C mode of the controller. Standard or Fast only supported
 178  * @scl_min_width_us: SCL line minimum pulse width in us
 179  * @sda_min_width_us: SDA line minimum pulse width in us
 180  * @client: I2C transfert information
 181  * @busy: I2C transfer on-going
 182  */
 183 struct st_i2c_dev {
 184         struct i2c_adapter      adap;
 185         struct device           *dev;
 186         void __iomem            *base;
 187         struct completion       complete;
 188         int                     irq;
 189         struct clk              *clk;
 190         int                     mode;
 191         u32                     scl_min_width_us;
 192         u32                     sda_min_width_us;
 193         struct st_i2c_client    client;
 194         bool                    busy;
 195 };
 196 
 197 static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
 198 {
 199         writel_relaxed(readl_relaxed(reg) | mask, reg);
 200 }
 201 
 202 static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
 203 {
 204         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 205 }
 206 
 207 /*
 208  * From I2C Specifications v0.5.
 209  *
 210  * All the values below have +10% margin added to be
 211  * compatible with some out-of-spec devices,
 212  * like HDMI link of the Toshiba 19AV600 TV.
 213  */
 214 static struct st_i2c_timings i2c_timings[] = {
 215         [I2C_MODE_STANDARD] = {
 216                 .rate                   = 100000,
 217                 .rep_start_hold         = 4400,
 218                 .rep_start_setup        = 5170,
 219                 .start_hold             = 4400,
 220                 .data_setup_time        = 275,
 221                 .stop_setup_time        = 4400,
 222                 .bus_free_time          = 5170,
 223         },
 224         [I2C_MODE_FAST] = {
 225                 .rate                   = 400000,
 226                 .rep_start_hold         = 660,
 227                 .rep_start_setup        = 660,
 228                 .start_hold             = 660,
 229                 .data_setup_time        = 110,
 230                 .stop_setup_time        = 660,
 231                 .bus_free_time          = 1430,
 232         },
 233 };
 234 
 235 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
 236 {
 237         int count, i;
 238 
 239         /*
 240          * Counter only counts up to 7 but fifo size is 8...
 241          * When fifo is full, counter is 0 and RIR bit of status register is
 242          * set
 243          */
 244         if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
 245                 count = SSC_RXFIFO_SIZE;
 246         else
 247                 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
 248                         SSC_RX_FSTAT_STATUS;
 249 
 250         for (i = 0; i < count; i++)
 251                 readl_relaxed(i2c_dev->base + SSC_RBUF);
 252 }
 253 
 254 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
 255 {
 256         /*
 257          * FIFO needs to be emptied before reseting the IP,
 258          * else the controller raises a BUSY error.
 259          */
 260         st_i2c_flush_rx_fifo(i2c_dev);
 261 
 262         st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
 263         st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
 264 }
 265 
 266 /**
 267  * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
 268  * @i2c_dev: Controller's private data
 269  */
 270 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
 271 {
 272         unsigned long rate;
 273         u32 val, ns_per_clk;
 274         struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
 275 
 276         st_i2c_soft_reset(i2c_dev);
 277 
 278         val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
 279                 SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
 280         writel_relaxed(val, i2c_dev->base + SSC_CLR);
 281 
 282         /* SSC Control register setup */
 283         val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
 284         writel_relaxed(val, i2c_dev->base + SSC_CTL);
 285 
 286         rate = clk_get_rate(i2c_dev->clk);
 287         ns_per_clk = 1000000000 / rate;
 288 
 289         /* Baudrate */
 290         val = rate / (2 * t->rate);
 291         writel_relaxed(val, i2c_dev->base + SSC_BRG);
 292 
 293         /* Pre-scaler baudrate */
 294         writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
 295 
 296         /* Enable I2C mode */
 297         writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
 298 
 299         /* Repeated start hold time */
 300         val = t->rep_start_hold / ns_per_clk;
 301         writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
 302 
 303         /* Repeated start set up time */
 304         val = t->rep_start_setup / ns_per_clk;
 305         writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
 306 
 307         /* Start hold time */
 308         val = t->start_hold / ns_per_clk;
 309         writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
 310 
 311         /* Data set up time */
 312         val = t->data_setup_time / ns_per_clk;
 313         writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
 314 
 315         /* Stop set up time */
 316         val = t->stop_setup_time / ns_per_clk;
 317         writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
 318 
 319         /* Bus free time */
 320         val = t->bus_free_time / ns_per_clk;
 321         writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
 322 
 323         /* Prescalers set up */
 324         val = rate / 10000000;
 325         writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
 326         writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
 327 
 328         /* Noise suppression witdh */
 329         val = i2c_dev->scl_min_width_us * rate / 100000000;
 330         writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
 331 
 332         /* Noise suppression max output data delay width */
 333         val = i2c_dev->sda_min_width_us * rate / 100000000;
 334         writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
 335 }
 336 
 337 static int st_i2c_recover_bus(struct i2c_adapter *i2c_adap)
 338 {
 339         struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 340         u32 ctl;
 341 
 342         dev_dbg(i2c_dev->dev, "Trying to recover bus\n");
 343 
 344         /*
 345          * SSP IP is dual role SPI/I2C to generate 9 clock pulses
 346          * we switch to SPI node, 9 bit words and write a 0. This
 347          * has been validate with a oscilloscope and is easier
 348          * than switching to GPIO mode.
 349          */
 350 
 351         /* Disable interrupts */
 352         writel_relaxed(0, i2c_dev->base + SSC_IEN);
 353 
 354         st_i2c_hw_config(i2c_dev);
 355 
 356         ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
 357         st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
 358 
 359         st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
 360         usleep_range(8000, 10000);
 361 
 362         writel_relaxed(0, i2c_dev->base + SSC_TBUF);
 363         usleep_range(2000, 4000);
 364         st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
 365 
 366         return 0;
 367 }
 368 
 369 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
 370 {
 371         u32 sta;
 372         int i, ret;
 373 
 374         for (i = 0; i < 10; i++) {
 375                 sta = readl_relaxed(i2c_dev->base + SSC_STA);
 376                 if (!(sta & SSC_STA_BUSY))
 377                         return 0;
 378 
 379                 usleep_range(2000, 4000);
 380         }
 381 
 382         dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
 383 
 384         ret = i2c_recover_bus(&i2c_dev->adap);
 385         if (ret) {
 386                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 387                 return ret;
 388         }
 389 
 390         return -EBUSY;
 391 }
 392 
 393 /**
 394  * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
 395  * @i2c_dev: Controller's private data
 396  * @byte: Data to write in the Tx FIFO
 397  */
 398 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
 399 {
 400         u16 tbuf = byte << 1;
 401 
 402         writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
 403 }
 404 
 405 /**
 406  * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
 407  * @i2c_dev: Controller's private data
 408  *
 409  * This functions fills the Tx FIFO with I2C transfert buffer when
 410  * in write mode.
 411  */
 412 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
 413 {
 414         struct st_i2c_client *c = &i2c_dev->client;
 415         u32 tx_fstat, sta;
 416         int i;
 417 
 418         sta = readl_relaxed(i2c_dev->base + SSC_STA);
 419         if (sta & SSC_STA_TX_FIFO_FULL)
 420                 return;
 421 
 422         tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
 423         tx_fstat &= SSC_TX_FSTAT_STATUS;
 424 
 425         if (c->count < (SSC_TXFIFO_SIZE - tx_fstat))
 426                 i = c->count;
 427         else
 428                 i = SSC_TXFIFO_SIZE - tx_fstat;
 429 
 430         for (; i > 0; i--, c->count--, c->buf++)
 431                 st_i2c_write_tx_fifo(i2c_dev, *c->buf);
 432 }
 433 
 434 /**
 435  * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
 436  * @i2c_dev: Controller's private data
 437  * @max: Maximum amount of data to fill into the Tx FIFO
 438  *
 439  * This functions fills the Tx FIFO with fixed pattern when
 440  * in read mode to trigger clock.
 441  */
 442 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max)
 443 {
 444         struct st_i2c_client *c = &i2c_dev->client;
 445         u32 tx_fstat, sta;
 446         int i;
 447 
 448         sta = readl_relaxed(i2c_dev->base + SSC_STA);
 449         if (sta & SSC_STA_TX_FIFO_FULL)
 450                 return;
 451 
 452         tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
 453         tx_fstat &= SSC_TX_FSTAT_STATUS;
 454 
 455         if (max < (SSC_TXFIFO_SIZE - tx_fstat))
 456                 i = max;
 457         else
 458                 i = SSC_TXFIFO_SIZE - tx_fstat;
 459 
 460         for (; i > 0; i--, c->xfered++)
 461                 st_i2c_write_tx_fifo(i2c_dev, 0xff);
 462 }
 463 
 464 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
 465 {
 466         struct st_i2c_client *c = &i2c_dev->client;
 467         u32 i, sta;
 468         u16 rbuf;
 469 
 470         sta = readl_relaxed(i2c_dev->base + SSC_STA);
 471         if (sta & SSC_STA_RIR) {
 472                 i = SSC_RXFIFO_SIZE;
 473         } else {
 474                 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
 475                 i &= SSC_RX_FSTAT_STATUS;
 476         }
 477 
 478         for (; (i > 0) && (c->count > 0); i--, c->count--) {
 479                 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
 480                 *c->buf++ = (u8)rbuf & 0xff;
 481         }
 482 
 483         if (i) {
 484                 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
 485                 st_i2c_flush_rx_fifo(i2c_dev);
 486         }
 487 }
 488 
 489 /**
 490  * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
 491  * @i2c_dev: Controller's private data
 492  */
 493 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
 494 {
 495         struct st_i2c_client *c = &i2c_dev->client;
 496 
 497         st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
 498         st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
 499 
 500         if (c->stop) {
 501                 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
 502                 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
 503         } else {
 504                 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
 505                 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
 506         }
 507 }
 508 
 509 /**
 510  * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
 511  * @i2c_dev: Controller's private data
 512  */
 513 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
 514 {
 515         struct st_i2c_client *c = &i2c_dev->client;
 516 
 517         st_i2c_flush_rx_fifo(i2c_dev);
 518 
 519         if (!c->count)
 520                 /* End of xfer, send stop or repstart */
 521                 st_i2c_terminate_xfer(i2c_dev);
 522         else
 523                 st_i2c_wr_fill_tx_fifo(i2c_dev);
 524 }
 525 
 526 /**
 527  * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
 528  * @i2c_dev: Controller's private data
 529  */
 530 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
 531 {
 532         struct st_i2c_client *c = &i2c_dev->client;
 533         u32 ien;
 534 
 535         /* Trash the address read back */
 536         if (!c->xfered) {
 537                 readl_relaxed(i2c_dev->base + SSC_RBUF);
 538                 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
 539         } else {
 540                 st_i2c_read_rx_fifo(i2c_dev);
 541         }
 542 
 543         if (!c->count) {
 544                 /* End of xfer, send stop or repstart */
 545                 st_i2c_terminate_xfer(i2c_dev);
 546         } else if (c->count == 1) {
 547                 /* Penultimate byte to xfer, disable ACK gen. */
 548                 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
 549 
 550                 /* Last received byte is to be handled by NACK interrupt */
 551                 ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN;
 552                 writel_relaxed(ien, i2c_dev->base + SSC_IEN);
 553 
 554                 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
 555         } else {
 556                 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
 557         }
 558 }
 559 
 560 /**
 561  * st_i2c_isr() - Interrupt routine
 562  * @irq: interrupt number
 563  * @data: Controller's private data
 564  */
 565 static irqreturn_t st_i2c_isr_thread(int irq, void *data)
 566 {
 567         struct st_i2c_dev *i2c_dev = data;
 568         struct st_i2c_client *c = &i2c_dev->client;
 569         u32 sta, ien;
 570         int it;
 571 
 572         ien = readl_relaxed(i2c_dev->base + SSC_IEN);
 573         sta = readl_relaxed(i2c_dev->base + SSC_STA);
 574 
 575         /* Use __fls() to check error bits first */
 576         it = __fls(sta & ien);
 577         if (it < 0) {
 578                 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
 579                                 sta, ien);
 580                 return IRQ_NONE;
 581         }
 582 
 583         switch (1 << it) {
 584         case SSC_STA_TE:
 585                 if (c->addr & I2C_M_RD)
 586                         st_i2c_handle_read(i2c_dev);
 587                 else
 588                         st_i2c_handle_write(i2c_dev);
 589                 break;
 590 
 591         case SSC_STA_STOP:
 592         case SSC_STA_REPSTRT:
 593                 writel_relaxed(0, i2c_dev->base + SSC_IEN);
 594                 complete(&i2c_dev->complete);
 595                 break;
 596 
 597         case SSC_STA_NACK:
 598                 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
 599 
 600                 /* Last received byte handled by NACK interrupt */
 601                 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) {
 602                         st_i2c_handle_read(i2c_dev);
 603                         break;
 604                 }
 605 
 606                 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
 607                 writel_relaxed(it, i2c_dev->base + SSC_IEN);
 608 
 609                 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
 610                 c->result = -EIO;
 611                 break;
 612 
 613         case SSC_STA_ARBL:
 614                 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
 615 
 616                 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
 617                 writel_relaxed(it, i2c_dev->base + SSC_IEN);
 618 
 619                 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
 620                 c->result = -EAGAIN;
 621                 break;
 622 
 623         default:
 624                 dev_err(i2c_dev->dev,
 625                                 "it %d unhandled (sta=0x%04x)\n", it, sta);
 626         }
 627 
 628         /*
 629          * Read IEN register to ensure interrupt mask write is effective
 630          * before re-enabling interrupt at GIC level, and thus avoid spurious
 631          * interrupts.
 632          */
 633         readl(i2c_dev->base + SSC_IEN);
 634 
 635         return IRQ_HANDLED;
 636 }
 637 
 638 /**
 639  * st_i2c_xfer_msg() - Transfer a single I2C message
 640  * @i2c_dev: Controller's private data
 641  * @msg: I2C message to transfer
 642  * @is_first: first message of the sequence
 643  * @is_last: last message of the sequence
 644  */
 645 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
 646                             bool is_first, bool is_last)
 647 {
 648         struct st_i2c_client *c = &i2c_dev->client;
 649         u32 ctl, i2c, it;
 650         unsigned long timeout;
 651         int ret;
 652 
 653         c->addr         = i2c_8bit_addr_from_msg(msg);
 654         c->buf          = msg->buf;
 655         c->count        = msg->len;
 656         c->xfered       = 0;
 657         c->result       = 0;
 658         c->stop         = is_last;
 659 
 660         reinit_completion(&i2c_dev->complete);
 661 
 662         ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
 663         st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
 664 
 665         i2c = SSC_I2C_TXENB;
 666         if (c->addr & I2C_M_RD)
 667                 i2c |= SSC_I2C_ACKG;
 668         st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
 669 
 670         /* Write slave address */
 671         st_i2c_write_tx_fifo(i2c_dev, c->addr);
 672 
 673         /* Pre-fill Tx fifo with data in case of write */
 674         if (!(c->addr & I2C_M_RD))
 675                 st_i2c_wr_fill_tx_fifo(i2c_dev);
 676 
 677         it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN;
 678         writel_relaxed(it, i2c_dev->base + SSC_IEN);
 679 
 680         if (is_first) {
 681                 ret = st_i2c_wait_free_bus(i2c_dev);
 682                 if (ret)
 683                         return ret;
 684 
 685                 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
 686         }
 687 
 688         timeout = wait_for_completion_timeout(&i2c_dev->complete,
 689                         i2c_dev->adap.timeout);
 690         ret = c->result;
 691 
 692         if (!timeout) {
 693                 dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n",
 694                                 c->addr);
 695                 ret = -ETIMEDOUT;
 696         }
 697 
 698         i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG;
 699         st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
 700 
 701         writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
 702                         i2c_dev->base + SSC_CLR);
 703 
 704         return ret;
 705 }
 706 
 707 /**
 708  * st_i2c_xfer() - Transfer a single I2C message
 709  * @i2c_adap: Adapter pointer to the controller
 710  * @msgs: Pointer to data to be written.
 711  * @num: Number of messages to be executed
 712  */
 713 static int st_i2c_xfer(struct i2c_adapter *i2c_adap,
 714                         struct i2c_msg msgs[], int num)
 715 {
 716         struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 717         int ret, i;
 718 
 719         i2c_dev->busy = true;
 720 
 721         ret = clk_prepare_enable(i2c_dev->clk);
 722         if (ret) {
 723                 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
 724                 return ret;
 725         }
 726 
 727         pinctrl_pm_select_default_state(i2c_dev->dev);
 728 
 729         st_i2c_hw_config(i2c_dev);
 730 
 731         for (i = 0; (i < num) && !ret; i++)
 732                 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
 733 
 734         pinctrl_pm_select_idle_state(i2c_dev->dev);
 735 
 736         clk_disable_unprepare(i2c_dev->clk);
 737 
 738         i2c_dev->busy = false;
 739 
 740         return (ret < 0) ? ret : i;
 741 }
 742 
 743 #ifdef CONFIG_PM_SLEEP
 744 static int st_i2c_suspend(struct device *dev)
 745 {
 746         struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 747 
 748         if (i2c_dev->busy)
 749                 return -EBUSY;
 750 
 751         pinctrl_pm_select_sleep_state(dev);
 752 
 753         return 0;
 754 }
 755 
 756 static int st_i2c_resume(struct device *dev)
 757 {
 758         pinctrl_pm_select_default_state(dev);
 759         /* Go in idle state if available */
 760         pinctrl_pm_select_idle_state(dev);
 761 
 762         return 0;
 763 }
 764 
 765 static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume);
 766 #define ST_I2C_PM       (&st_i2c_pm)
 767 #else
 768 #define ST_I2C_PM       NULL
 769 #endif
 770 
 771 static u32 st_i2c_func(struct i2c_adapter *adap)
 772 {
 773         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 774 }
 775 
 776 static const struct i2c_algorithm st_i2c_algo = {
 777         .master_xfer = st_i2c_xfer,
 778         .functionality = st_i2c_func,
 779 };
 780 
 781 static struct i2c_bus_recovery_info st_i2c_recovery_info = {
 782         .recover_bus = st_i2c_recover_bus,
 783 };
 784 
 785 static int st_i2c_of_get_deglitch(struct device_node *np,
 786                 struct st_i2c_dev *i2c_dev)
 787 {
 788         int ret;
 789 
 790         ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us",
 791                         &i2c_dev->scl_min_width_us);
 792         if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
 793                 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
 794                 return ret;
 795         }
 796 
 797         ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us",
 798                         &i2c_dev->sda_min_width_us);
 799         if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
 800                 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
 801                 return ret;
 802         }
 803 
 804         return 0;
 805 }
 806 
 807 static int st_i2c_probe(struct platform_device *pdev)
 808 {
 809         struct device_node *np = pdev->dev.of_node;
 810         struct st_i2c_dev *i2c_dev;
 811         struct resource *res;
 812         u32 clk_rate;
 813         struct i2c_adapter *adap;
 814         int ret;
 815 
 816         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 817         if (!i2c_dev)
 818                 return -ENOMEM;
 819 
 820         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 821         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
 822         if (IS_ERR(i2c_dev->base))
 823                 return PTR_ERR(i2c_dev->base);
 824 
 825         i2c_dev->irq = irq_of_parse_and_map(np, 0);
 826         if (!i2c_dev->irq) {
 827                 dev_err(&pdev->dev, "IRQ missing or invalid\n");
 828                 return -EINVAL;
 829         }
 830 
 831         i2c_dev->clk = of_clk_get_by_name(np, "ssc");
 832         if (IS_ERR(i2c_dev->clk)) {
 833                 dev_err(&pdev->dev, "Unable to request clock\n");
 834                 return PTR_ERR(i2c_dev->clk);
 835         }
 836 
 837         i2c_dev->mode = I2C_MODE_STANDARD;
 838         ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
 839         if ((!ret) && (clk_rate == 400000))
 840                 i2c_dev->mode = I2C_MODE_FAST;
 841 
 842         i2c_dev->dev = &pdev->dev;
 843 
 844         ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
 845                         NULL, st_i2c_isr_thread,
 846                         IRQF_ONESHOT, pdev->name, i2c_dev);
 847         if (ret) {
 848                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 849                 return ret;
 850         }
 851 
 852         pinctrl_pm_select_default_state(i2c_dev->dev);
 853         /* In case idle state available, select it */
 854         pinctrl_pm_select_idle_state(i2c_dev->dev);
 855 
 856         ret = st_i2c_of_get_deglitch(np, i2c_dev);
 857         if (ret)
 858                 return ret;
 859 
 860         adap = &i2c_dev->adap;
 861         i2c_set_adapdata(adap, i2c_dev);
 862         snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start);
 863         adap->owner = THIS_MODULE;
 864         adap->timeout = 2 * HZ;
 865         adap->retries = 0;
 866         adap->algo = &st_i2c_algo;
 867         adap->bus_recovery_info = &st_i2c_recovery_info;
 868         adap->dev.parent = &pdev->dev;
 869         adap->dev.of_node = pdev->dev.of_node;
 870 
 871         init_completion(&i2c_dev->complete);
 872 
 873         ret = i2c_add_adapter(adap);
 874         if (ret)
 875                 return ret;
 876 
 877         platform_set_drvdata(pdev, i2c_dev);
 878 
 879         dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
 880 
 881         return 0;
 882 }
 883 
 884 static int st_i2c_remove(struct platform_device *pdev)
 885 {
 886         struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 887 
 888         i2c_del_adapter(&i2c_dev->adap);
 889 
 890         return 0;
 891 }
 892 
 893 static const struct of_device_id st_i2c_match[] = {
 894         { .compatible = "st,comms-ssc-i2c", },
 895         { .compatible = "st,comms-ssc4-i2c", },
 896         {},
 897 };
 898 MODULE_DEVICE_TABLE(of, st_i2c_match);
 899 
 900 static struct platform_driver st_i2c_driver = {
 901         .driver = {
 902                 .name = "st-i2c",
 903                 .of_match_table = st_i2c_match,
 904                 .pm = ST_I2C_PM,
 905         },
 906         .probe = st_i2c_probe,
 907         .remove = st_i2c_remove,
 908 };
 909 
 910 module_platform_driver(st_i2c_driver);
 911 
 912 MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>");
 913 MODULE_DESCRIPTION("STMicroelectronics I2C driver");
 914 MODULE_LICENSE("GPL v2");
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root/drivers/i2c/busses/i2c-st.c

DEFINITIONS
