root/drivers/rtc/rtc-sirfsoc.c

DEFINITIONS

1. sirfsoc_rtc_readl
2. sirfsoc_rtc_writel
3. sirfsoc_rtc_read_alarm
4. sirfsoc_rtc_set_alarm
5. sirfsoc_rtc_read_time
6. sirfsoc_rtc_set_time
7. sirfsoc_rtc_alarm_irq_enable
8. sirfsoc_rtc_irq_handler
9. sirfsoc_rtc_probe
10. sirfsoc_rtc_remove
11. sirfsoc_rtc_suspend
12. sirfsoc_rtc_resume

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * SiRFSoC Real Time Clock interface for Linux
   4  *
   5  * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7 
   8 #include <linux/module.h>
   9 #include <linux/err.h>
  10 #include <linux/rtc.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/slab.h>
  13 #include <linux/io.h>
  14 #include <linux/of.h>
  15 #include <linux/regmap.h>
  16 #include <linux/rtc/sirfsoc_rtciobrg.h>
  17 
  18 
  19 #define RTC_CN                  0x00
  20 #define RTC_ALARM0              0x04
  21 #define RTC_ALARM1              0x18
  22 #define RTC_STATUS              0x08
  23 #define RTC_SW_VALUE            0x40
  24 #define SIRFSOC_RTC_AL1E        (1<<6)
  25 #define SIRFSOC_RTC_AL1         (1<<4)
  26 #define SIRFSOC_RTC_HZE         (1<<3)
  27 #define SIRFSOC_RTC_AL0E        (1<<2)
  28 #define SIRFSOC_RTC_HZ          (1<<1)
  29 #define SIRFSOC_RTC_AL0         (1<<0)
  30 #define RTC_DIV                 0x0c
  31 #define RTC_DEEP_CTRL           0x14
  32 #define RTC_CLOCK_SWITCH        0x1c
  33 #define SIRFSOC_RTC_CLK         0x03    /* others are reserved */
  34 
  35 /* Refer to RTC DIV switch */
  36 #define RTC_HZ                  16
  37 
  38 /* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
  39 #define RTC_SHIFT               4
  40 
  41 #define INTR_SYSRTC_CN          0x48
  42 
  43 struct sirfsoc_rtc_drv {
  44         struct rtc_device       *rtc;
  45         u32                     rtc_base;
  46         u32                     irq;
  47         unsigned                irq_wake;
  48         /* Overflow for every 8 years extra time */
  49         u32                     overflow_rtc;
  50         spinlock_t              lock;
  51         struct regmap *regmap;
  52 #ifdef CONFIG_PM
  53         u32             saved_counter;
  54         u32             saved_overflow_rtc;
  55 #endif
  56 };
  57 
  58 static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
  59 {
  60         u32 val;
  61 
  62         regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
  63         return val;
  64 }
  65 
  66 static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
  67                                u32 offset, u32 val)
  68 {
  69         regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
  70 }
  71 
  72 static int sirfsoc_rtc_read_alarm(struct device *dev,
  73                 struct rtc_wkalrm *alrm)
  74 {
  75         unsigned long rtc_alarm, rtc_count;
  76         struct sirfsoc_rtc_drv *rtcdrv;
  77 
  78         rtcdrv = dev_get_drvdata(dev);
  79 
  80         spin_lock_irq(&rtcdrv->lock);
  81 
  82         rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
  83 
  84         rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
  85         memset(alrm, 0, sizeof(struct rtc_wkalrm));
  86 
  87         /*
  88          * assume alarm interval not beyond one round counter overflow_rtc:
  89          * 0->0xffffffff
  90          */
  91         /* if alarm is in next overflow cycle */
  92         if (rtc_count > rtc_alarm)
  93                 rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
  94                                 << (BITS_PER_LONG - RTC_SHIFT)
  95                                 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
  96         else
  97                 rtc_time_to_tm(rtcdrv->overflow_rtc
  98                                 << (BITS_PER_LONG - RTC_SHIFT)
  99                                 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
 100         if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
 101                 alrm->enabled = 1;
 102 
 103         spin_unlock_irq(&rtcdrv->lock);
 104 
 105         return 0;
 106 }
 107 
 108 static int sirfsoc_rtc_set_alarm(struct device *dev,
 109                 struct rtc_wkalrm *alrm)
 110 {
 111         unsigned long rtc_status_reg, rtc_alarm;
 112         struct sirfsoc_rtc_drv *rtcdrv;
 113         rtcdrv = dev_get_drvdata(dev);
 114 
 115         if (alrm->enabled) {
 116                 rtc_tm_to_time(&(alrm->time), &rtc_alarm);
 117 
 118                 spin_lock_irq(&rtcdrv->lock);
 119 
 120                 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
 121                 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
 122                         /*
 123                          * An ongoing alarm in progress - ingore it and not
 124                          * to return EBUSY
 125                          */
 126                         dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
 127                 }
 128 
 129                 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
 130                 rtc_status_reg &= ~0x07; /* mask out the lower status bits */
 131                 /*
 132                  * This bit RTC_AL sets it as a wake-up source for Sleep Mode
 133                  * Writing 1 into this bit will clear it
 134                  */
 135                 rtc_status_reg |= SIRFSOC_RTC_AL0;
 136                 /* enable the RTC alarm interrupt */
 137                 rtc_status_reg |= SIRFSOC_RTC_AL0E;
 138                 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
 139 
 140                 spin_unlock_irq(&rtcdrv->lock);
 141         } else {
 142                 /*
 143                  * if this function was called with enabled=0
 144                  * then it could mean that the application is
 145                  * trying to cancel an ongoing alarm
 146                  */
 147                 spin_lock_irq(&rtcdrv->lock);
 148 
 149                 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
 150                 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
 151                         /* clear the RTC status register's alarm bit */
 152                         rtc_status_reg &= ~0x07;
 153                         /* write 1 into SIRFSOC_RTC_AL0 to force a clear */
 154                         rtc_status_reg |= (SIRFSOC_RTC_AL0);
 155                         /* Clear the Alarm enable bit */
 156                         rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
 157 
 158                         sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
 159                                            rtc_status_reg);
 160                 }
 161 
 162                 spin_unlock_irq(&rtcdrv->lock);
 163         }
 164 
 165         return 0;
 166 }
 167 
 168 static int sirfsoc_rtc_read_time(struct device *dev,
 169                 struct rtc_time *tm)
 170 {
 171         unsigned long tmp_rtc = 0;
 172         struct sirfsoc_rtc_drv *rtcdrv;
 173         rtcdrv = dev_get_drvdata(dev);
 174         /*
 175          * This patch is taken from WinCE - Need to validate this for
 176          * correctness. To work around sirfsoc RTC counter double sync logic
 177          * fail, read several times to make sure get stable value.
 178          */
 179         do {
 180                 tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
 181                 cpu_relax();
 182         } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
 183 
 184         rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
 185                                         tmp_rtc >> RTC_SHIFT, tm);
 186         return 0;
 187 }
 188 
 189 static int sirfsoc_rtc_set_time(struct device *dev,
 190                 struct rtc_time *tm)
 191 {
 192         unsigned long rtc_time;
 193         struct sirfsoc_rtc_drv *rtcdrv;
 194         rtcdrv = dev_get_drvdata(dev);
 195 
 196         rtc_tm_to_time(tm, &rtc_time);
 197 
 198         rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
 199 
 200         sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
 201         sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
 202 
 203         return 0;
 204 }
 205 
 206 static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
 207                 unsigned int enabled)
 208 {
 209         unsigned long rtc_status_reg = 0x0;
 210         struct sirfsoc_rtc_drv *rtcdrv;
 211 
 212         rtcdrv = dev_get_drvdata(dev);
 213 
 214         spin_lock_irq(&rtcdrv->lock);
 215 
 216         rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
 217         if (enabled)
 218                 rtc_status_reg |= SIRFSOC_RTC_AL0E;
 219         else
 220                 rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
 221 
 222         sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
 223 
 224         spin_unlock_irq(&rtcdrv->lock);
 225 
 226         return 0;
 227 
 228 }
 229 
 230 static const struct rtc_class_ops sirfsoc_rtc_ops = {
 231         .read_time = sirfsoc_rtc_read_time,
 232         .set_time = sirfsoc_rtc_set_time,
 233         .read_alarm = sirfsoc_rtc_read_alarm,
 234         .set_alarm = sirfsoc_rtc_set_alarm,
 235         .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
 236 };
 237 
 238 static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
 239 {
 240         struct sirfsoc_rtc_drv *rtcdrv = pdata;
 241         unsigned long rtc_status_reg = 0x0;
 242         unsigned long events = 0x0;
 243 
 244         spin_lock(&rtcdrv->lock);
 245 
 246         rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
 247         /* this bit will be set ONLY if an alarm was active
 248          * and it expired NOW
 249          * So this is being used as an ASSERT
 250          */
 251         if (rtc_status_reg & SIRFSOC_RTC_AL0) {
 252                 /*
 253                  * clear the RTC status register's alarm bit
 254                  * mask out the lower status bits
 255                  */
 256                 rtc_status_reg &= ~0x07;
 257                 /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
 258                 rtc_status_reg |= (SIRFSOC_RTC_AL0);
 259                 /* Clear the Alarm enable bit */
 260                 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
 261         }
 262 
 263         sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
 264 
 265         spin_unlock(&rtcdrv->lock);
 266 
 267         /* this should wake up any apps polling/waiting on the read
 268          * after setting the alarm
 269          */
 270         events |= RTC_IRQF | RTC_AF;
 271         rtc_update_irq(rtcdrv->rtc, 1, events);
 272 
 273         return IRQ_HANDLED;
 274 }
 275 
 276 static const struct of_device_id sirfsoc_rtc_of_match[] = {
 277         { .compatible = "sirf,prima2-sysrtc"},
 278         {},
 279 };
 280 
 281 static const struct regmap_config sysrtc_regmap_config = {
 282         .reg_bits = 32,
 283         .val_bits = 32,
 284         .fast_io = true,
 285 };
 286 
 287 MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
 288 
 289 static int sirfsoc_rtc_probe(struct platform_device *pdev)
 290 {
 291         int err;
 292         unsigned long rtc_div;
 293         struct sirfsoc_rtc_drv *rtcdrv;
 294         struct device_node *np = pdev->dev.of_node;
 295 
 296         rtcdrv = devm_kzalloc(&pdev->dev,
 297                 sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
 298         if (rtcdrv == NULL)
 299                 return -ENOMEM;
 300 
 301         spin_lock_init(&rtcdrv->lock);
 302 
 303         err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
 304         if (err) {
 305                 dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
 306                 return err;
 307         }
 308 
 309         platform_set_drvdata(pdev, rtcdrv);
 310 
 311         /* Register rtc alarm as a wakeup source */
 312         device_init_wakeup(&pdev->dev, 1);
 313 
 314         rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
 315                         &sysrtc_regmap_config);
 316         if (IS_ERR(rtcdrv->regmap)) {
 317                 err = PTR_ERR(rtcdrv->regmap);
 318                 dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
 319                         err);
 320                 return err;
 321         }
 322 
 323         /*
 324          * Set SYS_RTC counter in RTC_HZ HZ Units
 325          * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
 326          * If 16HZ, therefore RTC_DIV = 1023;
 327          */
 328         rtc_div = ((32768 / RTC_HZ) / 2) - 1;
 329         sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
 330 
 331         /* 0x3 -> RTC_CLK */
 332         sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
 333 
 334         /* reset SYS RTC ALARM0 */
 335         sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
 336 
 337         /* reset SYS RTC ALARM1 */
 338         sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
 339 
 340         /* Restore RTC Overflow From Register After Command Reboot */
 341         rtcdrv->overflow_rtc =
 342                 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
 343 
 344         rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 345                         &sirfsoc_rtc_ops, THIS_MODULE);
 346         if (IS_ERR(rtcdrv->rtc)) {
 347                 err = PTR_ERR(rtcdrv->rtc);
 348                 dev_err(&pdev->dev, "can't register RTC device\n");
 349                 return err;
 350         }
 351 
 352         rtcdrv->irq = platform_get_irq(pdev, 0);
 353         err = devm_request_irq(
 354                         &pdev->dev,
 355                         rtcdrv->irq,
 356                         sirfsoc_rtc_irq_handler,
 357                         IRQF_SHARED,
 358                         pdev->name,
 359                         rtcdrv);
 360         if (err) {
 361                 dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
 362                 return err;
 363         }
 364 
 365         return 0;
 366 }
 367 
 368 static int sirfsoc_rtc_remove(struct platform_device *pdev)
 369 {
 370         device_init_wakeup(&pdev->dev, 0);
 371 
 372         return 0;
 373 }
 374 
 375 #ifdef CONFIG_PM_SLEEP
 376 static int sirfsoc_rtc_suspend(struct device *dev)
 377 {
 378         struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
 379         rtcdrv->overflow_rtc =
 380                 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
 381 
 382         rtcdrv->saved_counter =
 383                 sirfsoc_rtc_readl(rtcdrv, RTC_CN);
 384         rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
 385         if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
 386                 rtcdrv->irq_wake = 1;
 387 
 388         return 0;
 389 }
 390 
 391 static int sirfsoc_rtc_resume(struct device *dev)
 392 {
 393         u32 tmp;
 394         struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
 395 
 396         /*
 397          * if resume from snapshot and the rtc power is lost,
 398          * restroe the rtc settings
 399          */
 400         if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
 401                 u32 rtc_div;
 402                 /* 0x3 -> RTC_CLK */
 403                 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
 404                 /*
 405                  * Set SYS_RTC counter in RTC_HZ HZ Units
 406                  * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
 407                  * If 16HZ, therefore RTC_DIV = 1023;
 408                  */
 409                 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
 410 
 411                 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
 412 
 413                 /* reset SYS RTC ALARM0 */
 414                 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
 415 
 416                 /* reset SYS RTC ALARM1 */
 417                 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
 418         }
 419         rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
 420 
 421         /*
 422          * if current counter is small than previous,
 423          * it means overflow in sleep
 424          */
 425         tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
 426         if (tmp <= rtcdrv->saved_counter)
 427                 rtcdrv->overflow_rtc++;
 428         /*
 429          *PWRC Value Be Changed When Suspend, Restore Overflow
 430          * In Memory To Register
 431          */
 432         sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
 433 
 434         if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
 435                 disable_irq_wake(rtcdrv->irq);
 436                 rtcdrv->irq_wake = 0;
 437         }
 438 
 439         return 0;
 440 }
 441 #endif
 442 
 443 static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
 444                 sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
 445 
 446 static struct platform_driver sirfsoc_rtc_driver = {
 447         .driver = {
 448                 .name = "sirfsoc-rtc",
 449                 .pm = &sirfsoc_rtc_pm_ops,
 450                 .of_match_table = sirfsoc_rtc_of_match,
 451         },
 452         .probe = sirfsoc_rtc_probe,
 453         .remove = sirfsoc_rtc_remove,
 454 };
 455 module_platform_driver(sirfsoc_rtc_driver);
 456 
 457 MODULE_DESCRIPTION("SiRF SoC rtc driver");
 458 MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
 459 MODULE_LICENSE("GPL v2");
 460 MODULE_ALIAS("platform:sirfsoc-rtc");