This source file includes following definitions.
- emc_ccfifo_writel
- emc_seq_update_timing
- emc_seq_disable_auto_cal
- emc_seq_wait_clkchange
- tegra_emc_find_timing
- tegra_emc_prepare_timing_change
- tegra_emc_complete_timing_change
- emc_read_current_timing
- emc_init
- load_one_timing_from_dt
- cmp_timings
- tegra_emc_load_timings_from_dt
- tegra_emc_find_node_by_ram_code
- emc_debug_rate_get
- emc_debug_rate_set
- emc_debug_supported_rates_show
- emc_debug_supported_rates_open
- emc_debugfs_init
- tegra_emc_probe
- tegra_emc_init
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9 #include <linux/clk-provider.h>
10 #include <linux/clk.h>
11 #include <linux/clkdev.h>
12 #include <linux/debugfs.h>
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_device.h>
18 #include <linux/sort.h>
19 #include <linux/string.h>
20
21 #include <soc/tegra/emc.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/mc.h>
24
25 #define EMC_FBIO_CFG5 0x104
26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
28
29 #define EMC_INTSTATUS 0x0
30 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
31
32 #define EMC_CFG 0xc
33 #define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
34 #define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
35 #define EMC_CFG_DRAM_ACPD BIT(29)
36 #define EMC_CFG_DYN_SREF BIT(28)
37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
38 #define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18)
39
40 #define EMC_REFCTRL 0x20
41 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
42 #define EMC_REFCTRL_ENABLE BIT(31)
43
44 #define EMC_TIMING_CONTROL 0x28
45 #define EMC_RC 0x2c
46 #define EMC_RFC 0x30
47 #define EMC_RAS 0x34
48 #define EMC_RP 0x38
49 #define EMC_R2W 0x3c
50 #define EMC_W2R 0x40
51 #define EMC_R2P 0x44
52 #define EMC_W2P 0x48
53 #define EMC_RD_RCD 0x4c
54 #define EMC_WR_RCD 0x50
55 #define EMC_RRD 0x54
56 #define EMC_REXT 0x58
57 #define EMC_WDV 0x5c
58 #define EMC_QUSE 0x60
59 #define EMC_QRST 0x64
60 #define EMC_QSAFE 0x68
61 #define EMC_RDV 0x6c
62 #define EMC_REFRESH 0x70
63 #define EMC_BURST_REFRESH_NUM 0x74
64 #define EMC_PDEX2WR 0x78
65 #define EMC_PDEX2RD 0x7c
66 #define EMC_PCHG2PDEN 0x80
67 #define EMC_ACT2PDEN 0x84
68 #define EMC_AR2PDEN 0x88
69 #define EMC_RW2PDEN 0x8c
70 #define EMC_TXSR 0x90
71 #define EMC_TCKE 0x94
72 #define EMC_TFAW 0x98
73 #define EMC_TRPAB 0x9c
74 #define EMC_TCLKSTABLE 0xa0
75 #define EMC_TCLKSTOP 0xa4
76 #define EMC_TREFBW 0xa8
77 #define EMC_ODT_WRITE 0xb0
78 #define EMC_ODT_READ 0xb4
79 #define EMC_WEXT 0xb8
80 #define EMC_CTT 0xbc
81 #define EMC_RFC_SLR 0xc0
82 #define EMC_MRS_WAIT_CNT2 0xc4
83
84 #define EMC_MRS_WAIT_CNT 0xc8
85 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
86 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
87 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
88 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
89 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
90 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
91
92 #define EMC_MRS 0xcc
93 #define EMC_MODE_SET_DLL_RESET BIT(8)
94 #define EMC_MODE_SET_LONG_CNT BIT(26)
95 #define EMC_EMRS 0xd0
96 #define EMC_REF 0xd4
97 #define EMC_PRE 0xd8
98
99 #define EMC_SELF_REF 0xe0
100 #define EMC_SELF_REF_CMD_ENABLED BIT(0)
101 #define EMC_SELF_REF_DEV_SEL_SHIFT 30
102
103 #define EMC_MRW 0xe8
104
105 #define EMC_MRR 0xec
106 #define EMC_MRR_MA_SHIFT 16
107 #define LPDDR2_MR4_TEMP_SHIFT 0
108
109 #define EMC_XM2DQSPADCTRL3 0xf8
110 #define EMC_FBIO_SPARE 0x100
111
112 #define EMC_FBIO_CFG6 0x114
113 #define EMC_EMRS2 0x12c
114 #define EMC_MRW2 0x134
115 #define EMC_MRW4 0x13c
116 #define EMC_EINPUT 0x14c
117 #define EMC_EINPUT_DURATION 0x150
118 #define EMC_PUTERM_EXTRA 0x154
119 #define EMC_TCKESR 0x158
120 #define EMC_TPD 0x15c
121
122 #define EMC_AUTO_CAL_CONFIG 0x2a4
123 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
124 #define EMC_AUTO_CAL_INTERVAL 0x2a8
125 #define EMC_AUTO_CAL_STATUS 0x2ac
126 #define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
127 #define EMC_STATUS 0x2b4
128 #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
129
130 #define EMC_CFG_2 0x2b8
131 #define EMC_CFG_2_MODE_SHIFT 0
132 #define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6)
133
134 #define EMC_CFG_DIG_DLL 0x2bc
135 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
136 #define EMC_RDV_MASK 0x2cc
137 #define EMC_WDV_MASK 0x2d0
138 #define EMC_CTT_DURATION 0x2d8
139 #define EMC_CTT_TERM_CTRL 0x2dc
140 #define EMC_ZCAL_INTERVAL 0x2e0
141 #define EMC_ZCAL_WAIT_CNT 0x2e4
142
143 #define EMC_ZQ_CAL 0x2ec
144 #define EMC_ZQ_CAL_CMD BIT(0)
145 #define EMC_ZQ_CAL_LONG BIT(4)
146 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \
147 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
148 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \
149 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
150
151 #define EMC_XM2CMDPADCTRL 0x2f0
152 #define EMC_XM2DQSPADCTRL 0x2f8
153 #define EMC_XM2DQSPADCTRL2 0x2fc
154 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
155 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
156 #define EMC_XM2DQPADCTRL 0x300
157 #define EMC_XM2DQPADCTRL2 0x304
158 #define EMC_XM2CLKPADCTRL 0x308
159 #define EMC_XM2COMPPADCTRL 0x30c
160 #define EMC_XM2VTTGENPADCTRL 0x310
161 #define EMC_XM2VTTGENPADCTRL2 0x314
162 #define EMC_XM2VTTGENPADCTRL3 0x318
163 #define EMC_XM2DQSPADCTRL4 0x320
164 #define EMC_DLL_XFORM_DQS0 0x328
165 #define EMC_DLL_XFORM_DQS1 0x32c
166 #define EMC_DLL_XFORM_DQS2 0x330
167 #define EMC_DLL_XFORM_DQS3 0x334
168 #define EMC_DLL_XFORM_DQS4 0x338
169 #define EMC_DLL_XFORM_DQS5 0x33c
170 #define EMC_DLL_XFORM_DQS6 0x340
171 #define EMC_DLL_XFORM_DQS7 0x344
172 #define EMC_DLL_XFORM_QUSE0 0x348
173 #define EMC_DLL_XFORM_QUSE1 0x34c
174 #define EMC_DLL_XFORM_QUSE2 0x350
175 #define EMC_DLL_XFORM_QUSE3 0x354
176 #define EMC_DLL_XFORM_QUSE4 0x358
177 #define EMC_DLL_XFORM_QUSE5 0x35c
178 #define EMC_DLL_XFORM_QUSE6 0x360
179 #define EMC_DLL_XFORM_QUSE7 0x364
180 #define EMC_DLL_XFORM_DQ0 0x368
181 #define EMC_DLL_XFORM_DQ1 0x36c
182 #define EMC_DLL_XFORM_DQ2 0x370
183 #define EMC_DLL_XFORM_DQ3 0x374
184 #define EMC_DLI_TRIM_TXDQS0 0x3a8
185 #define EMC_DLI_TRIM_TXDQS1 0x3ac
186 #define EMC_DLI_TRIM_TXDQS2 0x3b0
187 #define EMC_DLI_TRIM_TXDQS3 0x3b4
188 #define EMC_DLI_TRIM_TXDQS4 0x3b8
189 #define EMC_DLI_TRIM_TXDQS5 0x3bc
190 #define EMC_DLI_TRIM_TXDQS6 0x3c0
191 #define EMC_DLI_TRIM_TXDQS7 0x3c4
192 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
193 #define EMC_SEL_DPD_CTRL 0x3d8
194 #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8)
195 #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5)
196 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
197 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
198 #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2)
199 #define EMC_SEL_DPD_CTRL_DDR3_MASK \
200 ((0xf << 2) | BIT(8))
201 #define EMC_SEL_DPD_CTRL_MASK \
202 ((0x3 << 2) | BIT(5) | BIT(8))
203 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
204 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
205 #define EMC_TXSRDLL 0x3e4
206 #define EMC_CCFIFO_ADDR 0x3e8
207 #define EMC_CCFIFO_DATA 0x3ec
208 #define EMC_CCFIFO_STATUS 0x3f0
209 #define EMC_CDB_CNTL_1 0x3f4
210 #define EMC_CDB_CNTL_2 0x3f8
211 #define EMC_XM2CLKPADCTRL2 0x3fc
212 #define EMC_AUTO_CAL_CONFIG2 0x458
213 #define EMC_AUTO_CAL_CONFIG3 0x45c
214 #define EMC_IBDLY 0x468
215 #define EMC_DLL_XFORM_ADDR0 0x46c
216 #define EMC_DLL_XFORM_ADDR1 0x470
217 #define EMC_DLL_XFORM_ADDR2 0x474
218 #define EMC_DSR_VTTGEN_DRV 0x47c
219 #define EMC_TXDSRVTTGEN 0x480
220 #define EMC_XM2CMDPADCTRL4 0x484
221 #define EMC_XM2CMDPADCTRL5 0x488
222 #define EMC_DLL_XFORM_DQS8 0x4a0
223 #define EMC_DLL_XFORM_DQS9 0x4a4
224 #define EMC_DLL_XFORM_DQS10 0x4a8
225 #define EMC_DLL_XFORM_DQS11 0x4ac
226 #define EMC_DLL_XFORM_DQS12 0x4b0
227 #define EMC_DLL_XFORM_DQS13 0x4b4
228 #define EMC_DLL_XFORM_DQS14 0x4b8
229 #define EMC_DLL_XFORM_DQS15 0x4bc
230 #define EMC_DLL_XFORM_QUSE8 0x4c0
231 #define EMC_DLL_XFORM_QUSE9 0x4c4
232 #define EMC_DLL_XFORM_QUSE10 0x4c8
233 #define EMC_DLL_XFORM_QUSE11 0x4cc
234 #define EMC_DLL_XFORM_QUSE12 0x4d0
235 #define EMC_DLL_XFORM_QUSE13 0x4d4
236 #define EMC_DLL_XFORM_QUSE14 0x4d8
237 #define EMC_DLL_XFORM_QUSE15 0x4dc
238 #define EMC_DLL_XFORM_DQ4 0x4e0
239 #define EMC_DLL_XFORM_DQ5 0x4e4
240 #define EMC_DLL_XFORM_DQ6 0x4e8
241 #define EMC_DLL_XFORM_DQ7 0x4ec
242 #define EMC_DLI_TRIM_TXDQS8 0x520
243 #define EMC_DLI_TRIM_TXDQS9 0x524
244 #define EMC_DLI_TRIM_TXDQS10 0x528
245 #define EMC_DLI_TRIM_TXDQS11 0x52c
246 #define EMC_DLI_TRIM_TXDQS12 0x530
247 #define EMC_DLI_TRIM_TXDQS13 0x534
248 #define EMC_DLI_TRIM_TXDQS14 0x538
249 #define EMC_DLI_TRIM_TXDQS15 0x53c
250 #define EMC_CDB_CNTL_3 0x540
251 #define EMC_XM2DQSPADCTRL5 0x544
252 #define EMC_XM2DQSPADCTRL6 0x548
253 #define EMC_XM2DQPADCTRL3 0x54c
254 #define EMC_DLL_XFORM_ADDR3 0x550
255 #define EMC_DLL_XFORM_ADDR4 0x554
256 #define EMC_DLL_XFORM_ADDR5 0x558
257 #define EMC_CFG_PIPE 0x560
258 #define EMC_QPOP 0x564
259 #define EMC_QUSE_WIDTH 0x568
260 #define EMC_PUTERM_WIDTH 0x56c
261 #define EMC_BGBIAS_CTL0 0x570
262 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
263 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
264 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
265 #define EMC_PUTERM_ADJ 0x574
266
267 #define DRAM_DEV_SEL_ALL 0
268 #define DRAM_DEV_SEL_0 (2 << 30)
269 #define DRAM_DEV_SEL_1 (1 << 30)
270
271 #define EMC_CFG_POWER_FEATURES_MASK \
272 (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
273 EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
274 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
275 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
276
277
278 #define EMC_STATUS_UPDATE_TIMEOUT 1000
279
280 enum emc_dram_type {
281 DRAM_TYPE_DDR3 = 0,
282 DRAM_TYPE_DDR1 = 1,
283 DRAM_TYPE_LPDDR3 = 2,
284 DRAM_TYPE_DDR2 = 3
285 };
286
287 enum emc_dll_change {
288 DLL_CHANGE_NONE,
289 DLL_CHANGE_ON,
290 DLL_CHANGE_OFF
291 };
292
293 static const unsigned long emc_burst_regs[] = {
294 EMC_RC,
295 EMC_RFC,
296 EMC_RFC_SLR,
297 EMC_RAS,
298 EMC_RP,
299 EMC_R2W,
300 EMC_W2R,
301 EMC_R2P,
302 EMC_W2P,
303 EMC_RD_RCD,
304 EMC_WR_RCD,
305 EMC_RRD,
306 EMC_REXT,
307 EMC_WEXT,
308 EMC_WDV,
309 EMC_WDV_MASK,
310 EMC_QUSE,
311 EMC_QUSE_WIDTH,
312 EMC_IBDLY,
313 EMC_EINPUT,
314 EMC_EINPUT_DURATION,
315 EMC_PUTERM_EXTRA,
316 EMC_PUTERM_WIDTH,
317 EMC_PUTERM_ADJ,
318 EMC_CDB_CNTL_1,
319 EMC_CDB_CNTL_2,
320 EMC_CDB_CNTL_3,
321 EMC_QRST,
322 EMC_QSAFE,
323 EMC_RDV,
324 EMC_RDV_MASK,
325 EMC_REFRESH,
326 EMC_BURST_REFRESH_NUM,
327 EMC_PRE_REFRESH_REQ_CNT,
328 EMC_PDEX2WR,
329 EMC_PDEX2RD,
330 EMC_PCHG2PDEN,
331 EMC_ACT2PDEN,
332 EMC_AR2PDEN,
333 EMC_RW2PDEN,
334 EMC_TXSR,
335 EMC_TXSRDLL,
336 EMC_TCKE,
337 EMC_TCKESR,
338 EMC_TPD,
339 EMC_TFAW,
340 EMC_TRPAB,
341 EMC_TCLKSTABLE,
342 EMC_TCLKSTOP,
343 EMC_TREFBW,
344 EMC_FBIO_CFG6,
345 EMC_ODT_WRITE,
346 EMC_ODT_READ,
347 EMC_FBIO_CFG5,
348 EMC_CFG_DIG_DLL,
349 EMC_CFG_DIG_DLL_PERIOD,
350 EMC_DLL_XFORM_DQS0,
351 EMC_DLL_XFORM_DQS1,
352 EMC_DLL_XFORM_DQS2,
353 EMC_DLL_XFORM_DQS3,
354 EMC_DLL_XFORM_DQS4,
355 EMC_DLL_XFORM_DQS5,
356 EMC_DLL_XFORM_DQS6,
357 EMC_DLL_XFORM_DQS7,
358 EMC_DLL_XFORM_DQS8,
359 EMC_DLL_XFORM_DQS9,
360 EMC_DLL_XFORM_DQS10,
361 EMC_DLL_XFORM_DQS11,
362 EMC_DLL_XFORM_DQS12,
363 EMC_DLL_XFORM_DQS13,
364 EMC_DLL_XFORM_DQS14,
365 EMC_DLL_XFORM_DQS15,
366 EMC_DLL_XFORM_QUSE0,
367 EMC_DLL_XFORM_QUSE1,
368 EMC_DLL_XFORM_QUSE2,
369 EMC_DLL_XFORM_QUSE3,
370 EMC_DLL_XFORM_QUSE4,
371 EMC_DLL_XFORM_QUSE5,
372 EMC_DLL_XFORM_QUSE6,
373 EMC_DLL_XFORM_QUSE7,
374 EMC_DLL_XFORM_ADDR0,
375 EMC_DLL_XFORM_ADDR1,
376 EMC_DLL_XFORM_ADDR2,
377 EMC_DLL_XFORM_ADDR3,
378 EMC_DLL_XFORM_ADDR4,
379 EMC_DLL_XFORM_ADDR5,
380 EMC_DLL_XFORM_QUSE8,
381 EMC_DLL_XFORM_QUSE9,
382 EMC_DLL_XFORM_QUSE10,
383 EMC_DLL_XFORM_QUSE11,
384 EMC_DLL_XFORM_QUSE12,
385 EMC_DLL_XFORM_QUSE13,
386 EMC_DLL_XFORM_QUSE14,
387 EMC_DLL_XFORM_QUSE15,
388 EMC_DLI_TRIM_TXDQS0,
389 EMC_DLI_TRIM_TXDQS1,
390 EMC_DLI_TRIM_TXDQS2,
391 EMC_DLI_TRIM_TXDQS3,
392 EMC_DLI_TRIM_TXDQS4,
393 EMC_DLI_TRIM_TXDQS5,
394 EMC_DLI_TRIM_TXDQS6,
395 EMC_DLI_TRIM_TXDQS7,
396 EMC_DLI_TRIM_TXDQS8,
397 EMC_DLI_TRIM_TXDQS9,
398 EMC_DLI_TRIM_TXDQS10,
399 EMC_DLI_TRIM_TXDQS11,
400 EMC_DLI_TRIM_TXDQS12,
401 EMC_DLI_TRIM_TXDQS13,
402 EMC_DLI_TRIM_TXDQS14,
403 EMC_DLI_TRIM_TXDQS15,
404 EMC_DLL_XFORM_DQ0,
405 EMC_DLL_XFORM_DQ1,
406 EMC_DLL_XFORM_DQ2,
407 EMC_DLL_XFORM_DQ3,
408 EMC_DLL_XFORM_DQ4,
409 EMC_DLL_XFORM_DQ5,
410 EMC_DLL_XFORM_DQ6,
411 EMC_DLL_XFORM_DQ7,
412 EMC_XM2CMDPADCTRL,
413 EMC_XM2CMDPADCTRL4,
414 EMC_XM2CMDPADCTRL5,
415 EMC_XM2DQPADCTRL2,
416 EMC_XM2DQPADCTRL3,
417 EMC_XM2CLKPADCTRL,
418 EMC_XM2CLKPADCTRL2,
419 EMC_XM2COMPPADCTRL,
420 EMC_XM2VTTGENPADCTRL,
421 EMC_XM2VTTGENPADCTRL2,
422 EMC_XM2VTTGENPADCTRL3,
423 EMC_XM2DQSPADCTRL3,
424 EMC_XM2DQSPADCTRL4,
425 EMC_XM2DQSPADCTRL5,
426 EMC_XM2DQSPADCTRL6,
427 EMC_DSR_VTTGEN_DRV,
428 EMC_TXDSRVTTGEN,
429 EMC_FBIO_SPARE,
430 EMC_ZCAL_WAIT_CNT,
431 EMC_MRS_WAIT_CNT2,
432 EMC_CTT,
433 EMC_CTT_DURATION,
434 EMC_CFG_PIPE,
435 EMC_DYN_SELF_REF_CONTROL,
436 EMC_QPOP
437 };
438
439 struct emc_timing {
440 unsigned long rate;
441
442 u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
443
444 u32 emc_auto_cal_config;
445 u32 emc_auto_cal_config2;
446 u32 emc_auto_cal_config3;
447 u32 emc_auto_cal_interval;
448 u32 emc_bgbias_ctl0;
449 u32 emc_cfg;
450 u32 emc_cfg_2;
451 u32 emc_ctt_term_ctrl;
452 u32 emc_mode_1;
453 u32 emc_mode_2;
454 u32 emc_mode_4;
455 u32 emc_mode_reset;
456 u32 emc_mrs_wait_cnt;
457 u32 emc_sel_dpd_ctrl;
458 u32 emc_xm2dqspadctrl2;
459 u32 emc_zcal_cnt_long;
460 u32 emc_zcal_interval;
461 };
462
463 struct tegra_emc {
464 struct device *dev;
465
466 struct tegra_mc *mc;
467
468 void __iomem *regs;
469
470 enum emc_dram_type dram_type;
471 unsigned int dram_num;
472
473 struct emc_timing last_timing;
474 struct emc_timing *timings;
475 unsigned int num_timings;
476 };
477
478
479
480 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
481 unsigned long offset)
482 {
483 writel(value, emc->regs + EMC_CCFIFO_DATA);
484 writel(offset, emc->regs + EMC_CCFIFO_ADDR);
485 }
486
487 static void emc_seq_update_timing(struct tegra_emc *emc)
488 {
489 unsigned int i;
490 u32 value;
491
492 writel(1, emc->regs + EMC_TIMING_CONTROL);
493
494 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
495 value = readl(emc->regs + EMC_STATUS);
496 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
497 return;
498 udelay(1);
499 }
500
501 dev_err(emc->dev, "timing update timed out\n");
502 }
503
504 static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
505 {
506 unsigned int i;
507 u32 value;
508
509 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
510
511 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
512 value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
513 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
514 return;
515 udelay(1);
516 }
517
518 dev_err(emc->dev, "auto cal disable timed out\n");
519 }
520
521 static void emc_seq_wait_clkchange(struct tegra_emc *emc)
522 {
523 unsigned int i;
524 u32 value;
525
526 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
527 value = readl(emc->regs + EMC_INTSTATUS);
528 if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
529 return;
530 udelay(1);
531 }
532
533 dev_err(emc->dev, "clock change timed out\n");
534 }
535
536 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
537 unsigned long rate)
538 {
539 struct emc_timing *timing = NULL;
540 unsigned int i;
541
542 for (i = 0; i < emc->num_timings; i++) {
543 if (emc->timings[i].rate == rate) {
544 timing = &emc->timings[i];
545 break;
546 }
547 }
548
549 if (!timing) {
550 dev_err(emc->dev, "no timing for rate %lu\n", rate);
551 return NULL;
552 }
553
554 return timing;
555 }
556
557 int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
558 unsigned long rate)
559 {
560 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
561 struct emc_timing *last = &emc->last_timing;
562 enum emc_dll_change dll_change;
563 unsigned int pre_wait = 0;
564 u32 val, val2, mask;
565 bool update = false;
566 unsigned int i;
567
568 if (!timing)
569 return -ENOENT;
570
571 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
572 dll_change = DLL_CHANGE_NONE;
573 else if (timing->emc_mode_1 & 0x1)
574 dll_change = DLL_CHANGE_ON;
575 else
576 dll_change = DLL_CHANGE_OFF;
577
578
579 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
580
581
582 val = readl(emc->regs + EMC_CFG);
583 if (val & EMC_CFG_PWR_MASK) {
584 val &= ~EMC_CFG_POWER_FEATURES_MASK;
585 writel(val, emc->regs + EMC_CFG);
586
587 pre_wait = 5;
588 }
589
590
591 if (emc->dram_type == DRAM_TYPE_DDR3)
592 mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
593 else
594 mask = EMC_SEL_DPD_CTRL_MASK;
595
596 val = readl(emc->regs + EMC_SEL_DPD_CTRL);
597 if (val & mask) {
598 val &= ~mask;
599 writel(val, emc->regs + EMC_SEL_DPD_CTRL);
600 }
601
602
603 val = readl(emc->regs + EMC_BGBIAS_CTL0);
604 val2 = last->emc_bgbias_ctl0;
605 if (!(timing->emc_bgbias_ctl0 &
606 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
607 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
608 val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
609 update = true;
610 }
611
612 if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
613 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
614 update = true;
615 }
616
617 if (update) {
618 writel(val2, emc->regs + EMC_BGBIAS_CTL0);
619 if (pre_wait < 5)
620 pre_wait = 5;
621 }
622
623 update = false;
624 val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
625 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
626 !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
627 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
628 update = true;
629 }
630
631 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
632 !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
633 val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
634 update = true;
635 }
636
637 if (update) {
638 writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
639 if (pre_wait < 30)
640 pre_wait = 30;
641 }
642
643
644 if (pre_wait) {
645 emc_seq_update_timing(emc);
646 udelay(pre_wait);
647 }
648
649
650 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
651 emc_seq_disable_auto_cal(emc);
652 writel(timing->emc_ctt_term_ctrl,
653 emc->regs + EMC_CTT_TERM_CTRL);
654 emc_seq_update_timing(emc);
655 }
656
657
658 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
659 writel(timing->emc_burst_data[i],
660 emc->regs + emc_burst_regs[i]);
661
662 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
663 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
664
665 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
666
667 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
668 emc_ccfifo_writel(emc, val, EMC_CFG);
669
670
671 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
672 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
673 EMC_AUTO_CAL_CONFIG2);
674
675 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
676 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
677 EMC_AUTO_CAL_CONFIG3);
678
679 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
680 val = timing->emc_auto_cal_config;
681 val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
682 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
683 }
684
685
686 if (emc->dram_type == DRAM_TYPE_DDR3 &&
687 dll_change == DLL_CHANGE_ON) {
688 u32 cnt = 512;
689
690 if (timing->emc_zcal_interval != 0 &&
691 last->emc_zcal_interval == 0)
692 cnt -= emc->dram_num * 256;
693
694 val = (timing->emc_mrs_wait_cnt
695 & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
696 >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
697 if (cnt < val)
698 cnt = val;
699
700 val = timing->emc_mrs_wait_cnt
701 & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
702 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
703 & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
704
705 writel(val, emc->regs + EMC_MRS_WAIT_CNT);
706 }
707
708 val = timing->emc_cfg_2;
709 val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
710 emc_ccfifo_writel(emc, val, EMC_CFG_2);
711
712
713 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
714 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
715
716
717 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
718 EMC_REFCTRL);
719 if (emc->dram_type == DRAM_TYPE_DDR3)
720 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
721 EMC_SELF_REF_CMD_ENABLED,
722 EMC_SELF_REF);
723
724
725 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
726
727
728 if (emc->dram_type == DRAM_TYPE_DDR3)
729 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
730 EMC_SELF_REF);
731 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
732 EMC_REFCTRL_ENABLE,
733 EMC_REFCTRL);
734
735
736 if (emc->dram_type == DRAM_TYPE_DDR3) {
737 if (timing->emc_mode_1 != last->emc_mode_1)
738 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
739 if (timing->emc_mode_2 != last->emc_mode_2)
740 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
741
742 if ((timing->emc_mode_reset != last->emc_mode_reset) ||
743 dll_change == DLL_CHANGE_ON) {
744 val = timing->emc_mode_reset;
745 if (dll_change == DLL_CHANGE_ON) {
746 val |= EMC_MODE_SET_DLL_RESET;
747 val |= EMC_MODE_SET_LONG_CNT;
748 } else {
749 val &= ~EMC_MODE_SET_DLL_RESET;
750 }
751 emc_ccfifo_writel(emc, val, EMC_MRS);
752 }
753 } else {
754 if (timing->emc_mode_2 != last->emc_mode_2)
755 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
756 if (timing->emc_mode_1 != last->emc_mode_1)
757 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
758 if (timing->emc_mode_4 != last->emc_mode_4)
759 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
760 }
761
762
763 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
764 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
765 if (emc->dram_num > 1)
766 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
767 EMC_ZQ_CAL);
768 }
769
770
771 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
772
773 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
774 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
775
776
777 emc_seq_disable_auto_cal(emc);
778
779
780 readl(emc->regs + EMC_INTSTATUS);
781
782 return 0;
783 }
784
785 void tegra_emc_complete_timing_change(struct tegra_emc *emc,
786 unsigned long rate)
787 {
788 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
789 struct emc_timing *last = &emc->last_timing;
790 u32 val;
791
792 if (!timing)
793 return;
794
795
796 emc_seq_wait_clkchange(emc);
797
798
799 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
800 writel(timing->emc_auto_cal_interval,
801 emc->regs + EMC_AUTO_CAL_INTERVAL);
802
803
804 if (timing->emc_cfg & EMC_CFG_PWR_MASK)
805 writel(timing->emc_cfg, emc->regs + EMC_CFG);
806
807
808 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
809
810
811 if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
812 timing->emc_bgbias_ctl0 &
813 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
814 val = timing->emc_bgbias_ctl0;
815 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
816 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
817 writel(val, emc->regs + EMC_BGBIAS_CTL0);
818 } else {
819 if (emc->dram_type == DRAM_TYPE_DDR3 &&
820 readl(emc->regs + EMC_BGBIAS_CTL0) !=
821 timing->emc_bgbias_ctl0) {
822 writel(timing->emc_bgbias_ctl0,
823 emc->regs + EMC_BGBIAS_CTL0);
824 }
825
826 writel(timing->emc_auto_cal_interval,
827 emc->regs + EMC_AUTO_CAL_INTERVAL);
828 }
829
830
831 udelay(2);
832
833
834 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
835 emc_seq_update_timing(emc);
836
837 emc->last_timing = *timing;
838 }
839
840
841
842 static void emc_read_current_timing(struct tegra_emc *emc,
843 struct emc_timing *timing)
844 {
845 unsigned int i;
846
847 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
848 timing->emc_burst_data[i] =
849 readl(emc->regs + emc_burst_regs[i]);
850
851 timing->emc_cfg = readl(emc->regs + EMC_CFG);
852
853 timing->emc_auto_cal_interval = 0;
854 timing->emc_zcal_cnt_long = 0;
855 timing->emc_mode_1 = 0;
856 timing->emc_mode_2 = 0;
857 timing->emc_mode_4 = 0;
858 timing->emc_mode_reset = 0;
859 }
860
861 static int emc_init(struct tegra_emc *emc)
862 {
863 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
864 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
865 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
866
867 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
868
869 emc_read_current_timing(emc, &emc->last_timing);
870
871 return 0;
872 }
873
874 static int load_one_timing_from_dt(struct tegra_emc *emc,
875 struct emc_timing *timing,
876 struct device_node *node)
877 {
878 u32 value;
879 int err;
880
881 err = of_property_read_u32(node, "clock-frequency", &value);
882 if (err) {
883 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
884 node, err);
885 return err;
886 }
887
888 timing->rate = value;
889
890 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
891 timing->emc_burst_data,
892 ARRAY_SIZE(timing->emc_burst_data));
893 if (err) {
894 dev_err(emc->dev,
895 "timing %pOFn: failed to read emc burst data: %d\n",
896 node, err);
897 return err;
898 }
899
900 #define EMC_READ_PROP(prop, dtprop) { \
901 err = of_property_read_u32(node, dtprop, &timing->prop); \
902 if (err) { \
903 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
904 node, err); \
905 return err; \
906 } \
907 }
908
909 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
910 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
911 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
912 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
913 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
914 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
915 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
916 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
917 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
918 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
919 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
920 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
921 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
922 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
923 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
924 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
925 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
926
927 #undef EMC_READ_PROP
928
929 return 0;
930 }
931
932 static int cmp_timings(const void *_a, const void *_b)
933 {
934 const struct emc_timing *a = _a;
935 const struct emc_timing *b = _b;
936
937 if (a->rate < b->rate)
938 return -1;
939 else if (a->rate == b->rate)
940 return 0;
941 else
942 return 1;
943 }
944
945 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
946 struct device_node *node)
947 {
948 int child_count = of_get_child_count(node);
949 struct device_node *child;
950 struct emc_timing *timing;
951 unsigned int i = 0;
952 int err;
953
954 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
955 GFP_KERNEL);
956 if (!emc->timings)
957 return -ENOMEM;
958
959 emc->num_timings = child_count;
960
961 for_each_child_of_node(node, child) {
962 timing = &emc->timings[i++];
963
964 err = load_one_timing_from_dt(emc, timing, child);
965 if (err) {
966 of_node_put(child);
967 return err;
968 }
969 }
970
971 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
972 NULL);
973
974 return 0;
975 }
976
977 static const struct of_device_id tegra_emc_of_match[] = {
978 { .compatible = "nvidia,tegra124-emc" },
979 {}
980 };
981
982 static struct device_node *
983 tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
984 {
985 struct device_node *np;
986 int err;
987
988 for_each_child_of_node(node, np) {
989 u32 value;
990
991 err = of_property_read_u32(np, "nvidia,ram-code", &value);
992 if (err || (value != ram_code))
993 continue;
994
995 return np;
996 }
997
998 return NULL;
999 }
1000
1001
1002
1003 static int emc_debug_rate_get(void *data, u64 *rate)
1004 {
1005 struct clk *c = data;
1006
1007 *rate = clk_get_rate(c);
1008
1009 return 0;
1010 }
1011
1012 static int emc_debug_rate_set(void *data, u64 rate)
1013 {
1014 struct clk *c = data;
1015
1016 return clk_set_rate(c, rate);
1017 }
1018
1019 DEFINE_SIMPLE_ATTRIBUTE(emc_debug_rate_fops, emc_debug_rate_get,
1020 emc_debug_rate_set, "%lld\n");
1021
1022 static int emc_debug_supported_rates_show(struct seq_file *s, void *data)
1023 {
1024 struct tegra_emc *emc = s->private;
1025 const char *prefix = "";
1026 unsigned int i;
1027
1028 for (i = 0; i < emc->num_timings; i++) {
1029 struct emc_timing *timing = &emc->timings[i];
1030
1031 seq_printf(s, "%s%lu", prefix, timing->rate);
1032
1033 prefix = " ";
1034 }
1035
1036 seq_puts(s, "\n");
1037
1038 return 0;
1039 }
1040
1041 static int emc_debug_supported_rates_open(struct inode *inode,
1042 struct file *file)
1043 {
1044 return single_open(file, emc_debug_supported_rates_show,
1045 inode->i_private);
1046 }
1047
1048 static const struct file_operations emc_debug_supported_rates_fops = {
1049 .open = emc_debug_supported_rates_open,
1050 .read = seq_read,
1051 .llseek = seq_lseek,
1052 .release = single_release,
1053 };
1054
1055 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
1056 {
1057 struct dentry *root, *file;
1058 struct clk *clk;
1059
1060 root = debugfs_create_dir("emc", NULL);
1061 if (!root) {
1062 dev_err(dev, "failed to create debugfs directory\n");
1063 return;
1064 }
1065
1066 clk = clk_get_sys("tegra-clk-debug", "emc");
1067 if (IS_ERR(clk)) {
1068 dev_err(dev, "failed to get debug clock: %ld\n", PTR_ERR(clk));
1069 return;
1070 }
1071
1072 file = debugfs_create_file("rate", S_IRUGO | S_IWUSR, root, clk,
1073 &emc_debug_rate_fops);
1074 if (!file)
1075 dev_err(dev, "failed to create debugfs entry\n");
1076
1077 file = debugfs_create_file("supported_rates", S_IRUGO, root, emc,
1078 &emc_debug_supported_rates_fops);
1079 if (!file)
1080 dev_err(dev, "failed to create debugfs entry\n");
1081 }
1082
1083 static int tegra_emc_probe(struct platform_device *pdev)
1084 {
1085 struct platform_device *mc;
1086 struct device_node *np;
1087 struct tegra_emc *emc;
1088 struct resource *res;
1089 u32 ram_code;
1090 int err;
1091
1092 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1093 if (!emc)
1094 return -ENOMEM;
1095
1096 emc->dev = &pdev->dev;
1097
1098 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099 emc->regs = devm_ioremap_resource(&pdev->dev, res);
1100 if (IS_ERR(emc->regs))
1101 return PTR_ERR(emc->regs);
1102
1103 np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
1104 if (!np) {
1105 dev_err(&pdev->dev, "could not get memory controller\n");
1106 return -ENOENT;
1107 }
1108
1109 mc = of_find_device_by_node(np);
1110 of_node_put(np);
1111 if (!mc)
1112 return -ENOENT;
1113
1114 emc->mc = platform_get_drvdata(mc);
1115 if (!emc->mc)
1116 return -EPROBE_DEFER;
1117
1118 ram_code = tegra_read_ram_code();
1119
1120 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
1121 if (!np) {
1122 dev_err(&pdev->dev,
1123 "no memory timings for RAM code %u found in DT\n",
1124 ram_code);
1125 return -ENOENT;
1126 }
1127
1128 err = tegra_emc_load_timings_from_dt(emc, np);
1129 of_node_put(np);
1130 if (err)
1131 return err;
1132
1133 if (emc->num_timings == 0) {
1134 dev_err(&pdev->dev,
1135 "no memory timings for RAM code %u registered\n",
1136 ram_code);
1137 return -ENOENT;
1138 }
1139
1140 err = emc_init(emc);
1141 if (err) {
1142 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
1143 return err;
1144 }
1145
1146 platform_set_drvdata(pdev, emc);
1147
1148 if (IS_ENABLED(CONFIG_DEBUG_FS))
1149 emc_debugfs_init(&pdev->dev, emc);
1150
1151 return 0;
1152 };
1153
1154 static struct platform_driver tegra_emc_driver = {
1155 .probe = tegra_emc_probe,
1156 .driver = {
1157 .name = "tegra-emc",
1158 .of_match_table = tegra_emc_of_match,
1159 .suppress_bind_attrs = true,
1160 },
1161 };
1162
1163 static int tegra_emc_init(void)
1164 {
1165 return platform_driver_register(&tegra_emc_driver);
1166 }
1167 subsys_initcall(tegra_emc_init);