drivers/memory/brcmstb

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This source file includes following definitions.
is_dcpu_enabled
__disable_dcpu
__enable_dcpu
get_msg_chksum
get_msg_ptr
__finalize_command
__send_command
__verify_firmware
__verify_fw_checksum
__write_firmware
brcmstb_dpfe_download_firmware
generic_show
show_info
show_refresh
store_refresh
show_vendor
show_dram
brcmstb_dpfe_resume
brcmstb_dpfe_probe
brcmstb_dpfe_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
   4  *
   5  * Copyright (c) 2017 Broadcom
   6  */
   7 
   8 /*
   9  * This driver provides access to the DPFE interface of Broadcom STB SoCs.
  10  * The firmware running on the DCPU inside the DDR PHY can provide current
  11  * information about the system's RAM, for instance the DRAM refresh rate.
  12  * This can be used as an indirect indicator for the DRAM's temperature.
  13  * Slower refresh rate means cooler RAM, higher refresh rate means hotter
  14  * RAM.
  15  *
  16  * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
  17  * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
  18  *
  19  * Note regarding the loading of the firmware image: we use be32_to_cpu()
  20  * and le_32_to_cpu(), so we can support the following four cases:
  21  *     - LE kernel + LE firmware image (the most common case)
  22  *     - LE kernel + BE firmware image
  23  *     - BE kernel + LE firmware image
  24  *     - BE kernel + BE firmware image
  25  *
  26  * The DPCU always runs in big endian mode. The firwmare image, however, can
  27  * be in either format. Also, communication between host CPU and DCPU is
  28  * always in little endian.
  29  */
  30 
  31 #include <linux/delay.h>
  32 #include <linux/firmware.h>
  33 #include <linux/io.h>
  34 #include <linux/module.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_device.h>
  37 #include <linux/platform_device.h>
  38 
  39 #define DRVNAME                 "brcmstb-dpfe"
  40 
  41 /* DCPU register offsets */
  42 #define REG_DCPU_RESET          0x0
  43 #define REG_TO_DCPU_MBOX        0x10
  44 #define REG_TO_HOST_MBOX        0x14
  45 
  46 /* Macros to process offsets returned by the DCPU */
  47 #define DRAM_MSG_ADDR_OFFSET    0x0
  48 #define DRAM_MSG_TYPE_OFFSET    0x1c
  49 #define DRAM_MSG_ADDR_MASK      ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
  50 #define DRAM_MSG_TYPE_MASK      ((1UL << \
  51                                  (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
  52 
  53 /* Message RAM */
  54 #define DCPU_MSG_RAM_START      0x100
  55 #define DCPU_MSG_RAM(x)         (DCPU_MSG_RAM_START + (x) * sizeof(u32))
  56 
  57 /* DRAM Info Offsets & Masks */
  58 #define DRAM_INFO_INTERVAL      0x0
  59 #define DRAM_INFO_MR4           0x4
  60 #define DRAM_INFO_ERROR         0x8
  61 #define DRAM_INFO_MR4_MASK      0xff
  62 #define DRAM_INFO_MR4_SHIFT     24      /* We need to look at byte 3 */
  63 
  64 /* DRAM MR4 Offsets & Masks */
  65 #define DRAM_MR4_REFRESH        0x0     /* Refresh rate */
  66 #define DRAM_MR4_SR_ABORT       0x3     /* Self Refresh Abort */
  67 #define DRAM_MR4_PPRE           0x4     /* Post-package repair entry/exit */
  68 #define DRAM_MR4_TH_OFFS        0x5     /* Thermal Offset; vendor specific */
  69 #define DRAM_MR4_TUF            0x7     /* Temperature Update Flag */
  70 
  71 #define DRAM_MR4_REFRESH_MASK   0x7
  72 #define DRAM_MR4_SR_ABORT_MASK  0x1
  73 #define DRAM_MR4_PPRE_MASK      0x1
  74 #define DRAM_MR4_TH_OFFS_MASK   0x3
  75 #define DRAM_MR4_TUF_MASK       0x1
  76 
  77 /* DRAM Vendor Offsets & Masks (API v2) */
  78 #define DRAM_VENDOR_MR5         0x0
  79 #define DRAM_VENDOR_MR6         0x4
  80 #define DRAM_VENDOR_MR7         0x8
  81 #define DRAM_VENDOR_MR8         0xc
  82 #define DRAM_VENDOR_ERROR       0x10
  83 #define DRAM_VENDOR_MASK        0xff
  84 #define DRAM_VENDOR_SHIFT       24      /* We need to look at byte 3 */
  85 
  86 /* DRAM Information Offsets & Masks (API v3) */
  87 #define DRAM_DDR_INFO_MR4       0x0
  88 #define DRAM_DDR_INFO_MR5       0x4
  89 #define DRAM_DDR_INFO_MR6       0x8
  90 #define DRAM_DDR_INFO_MR7       0xc
  91 #define DRAM_DDR_INFO_MR8       0x10
  92 #define DRAM_DDR_INFO_ERROR     0x14
  93 #define DRAM_DDR_INFO_MASK      0xff
  94 
  95 /* Reset register bits & masks */
  96 #define DCPU_RESET_SHIFT        0x0
  97 #define DCPU_RESET_MASK         0x1
  98 #define DCPU_CLK_DISABLE_SHIFT  0x2
  99 
 100 /* DCPU return codes */
 101 #define DCPU_RET_ERROR_BIT      BIT(31)
 102 #define DCPU_RET_SUCCESS        0x1
 103 #define DCPU_RET_ERR_HEADER     (DCPU_RET_ERROR_BIT | BIT(0))
 104 #define DCPU_RET_ERR_INVAL      (DCPU_RET_ERROR_BIT | BIT(1))
 105 #define DCPU_RET_ERR_CHKSUM     (DCPU_RET_ERROR_BIT | BIT(2))
 106 #define DCPU_RET_ERR_COMMAND    (DCPU_RET_ERROR_BIT | BIT(3))
 107 /* This error code is not firmware defined and only used in the driver. */
 108 #define DCPU_RET_ERR_TIMEDOUT   (DCPU_RET_ERROR_BIT | BIT(4))
 109 
 110 /* Firmware magic */
 111 #define DPFE_BE_MAGIC           0xfe1010fe
 112 #define DPFE_LE_MAGIC           0xfe0101fe
 113 
 114 /* Error codes */
 115 #define ERR_INVALID_MAGIC       -1
 116 #define ERR_INVALID_SIZE        -2
 117 #define ERR_INVALID_CHKSUM      -3
 118 
 119 /* Message types */
 120 #define DPFE_MSG_TYPE_COMMAND   1
 121 #define DPFE_MSG_TYPE_RESPONSE  2
 122 
 123 #define DELAY_LOOP_MAX          1000
 124 
 125 enum dpfe_msg_fields {
 126         MSG_HEADER,
 127         MSG_COMMAND,
 128         MSG_ARG_COUNT,
 129         MSG_ARG0,
 130         MSG_CHKSUM,
 131         MSG_FIELD_MAX   = 16 /* Max number of arguments */
 132 };
 133 
 134 enum dpfe_commands {
 135         DPFE_CMD_GET_INFO,
 136         DPFE_CMD_GET_REFRESH,
 137         DPFE_CMD_GET_VENDOR,
 138         DPFE_CMD_MAX /* Last entry */
 139 };
 140 
 141 /*
 142  * Format of the binary firmware file:
 143  *
 144  *   entry
 145  *      0    header
 146  *              value:  0xfe0101fe  <== little endian
 147  *                      0xfe1010fe  <== big endian
 148  *      1    sequence:
 149  *              [31:16] total segments on this build
 150  *              [15:0]  this segment sequence.
 151  *      2    FW version
 152  *      3    IMEM byte size
 153  *      4    DMEM byte size
 154  *           IMEM
 155  *           DMEM
 156  *      last checksum ==> sum of everything
 157  */
 158 struct dpfe_firmware_header {
 159         u32 magic;
 160         u32 sequence;
 161         u32 version;
 162         u32 imem_size;
 163         u32 dmem_size;
 164 };
 165 
 166 /* Things we only need during initialization. */
 167 struct init_data {
 168         unsigned int dmem_len;
 169         unsigned int imem_len;
 170         unsigned int chksum;
 171         bool is_big_endian;
 172 };
 173 
 174 /* API version and corresponding commands */
 175 struct dpfe_api {
 176         int version;
 177         const char *fw_name;
 178         const struct attribute_group **sysfs_attrs;
 179         u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
 180 };
 181 
 182 /* Things we need for as long as we are active. */
 183 struct private_data {
 184         void __iomem *regs;
 185         void __iomem *dmem;
 186         void __iomem *imem;
 187         struct device *dev;
 188         const struct dpfe_api *dpfe_api;
 189         struct mutex lock;
 190 };
 191 
 192 static const char *error_text[] = {
 193         "Success", "Header code incorrect", "Unknown command or argument",
 194         "Incorrect checksum", "Malformed command", "Timed out",
 195 };
 196 
 197 /*
 198  * Forward declaration of our sysfs attribute functions, so we can declare the
 199  * attribute data structures early.
 200  */
 201 static ssize_t show_info(struct device *, struct device_attribute *, char *);
 202 static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
 203 static ssize_t store_refresh(struct device *, struct device_attribute *,
 204                           const char *, size_t);
 205 static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
 206 static ssize_t show_dram(struct device *, struct device_attribute *, char *);
 207 
 208 /*
 209  * Declare our attributes early, so they can be referenced in the API data
 210  * structure. We need to do this, because the attributes depend on the API
 211  * version.
 212  */
 213 static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
 214 static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
 215 static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
 216 static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
 217 
 218 /* API v2 sysfs attributes */
 219 static struct attribute *dpfe_v2_attrs[] = {
 220         &dev_attr_dpfe_info.attr,
 221         &dev_attr_dpfe_refresh.attr,
 222         &dev_attr_dpfe_vendor.attr,
 223         NULL
 224 };
 225 ATTRIBUTE_GROUPS(dpfe_v2);
 226 
 227 /* API v3 sysfs attributes */
 228 static struct attribute *dpfe_v3_attrs[] = {
 229         &dev_attr_dpfe_info.attr,
 230         &dev_attr_dpfe_dram.attr,
 231         NULL
 232 };
 233 ATTRIBUTE_GROUPS(dpfe_v3);
 234 
 235 /* API v2 firmware commands */
 236 static const struct dpfe_api dpfe_api_v2 = {
 237         .version = 2,
 238         .fw_name = "dpfe.bin",
 239         .sysfs_attrs = dpfe_v2_groups,
 240         .command = {
 241                 [DPFE_CMD_GET_INFO] = {
 242                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 243                         [MSG_COMMAND] = 1,
 244                         [MSG_ARG_COUNT] = 1,
 245                         [MSG_ARG0] = 1,
 246                         [MSG_CHKSUM] = 4,
 247                 },
 248                 [DPFE_CMD_GET_REFRESH] = {
 249                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 250                         [MSG_COMMAND] = 2,
 251                         [MSG_ARG_COUNT] = 1,
 252                         [MSG_ARG0] = 1,
 253                         [MSG_CHKSUM] = 5,
 254                 },
 255                 [DPFE_CMD_GET_VENDOR] = {
 256                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 257                         [MSG_COMMAND] = 2,
 258                         [MSG_ARG_COUNT] = 1,
 259                         [MSG_ARG0] = 2,
 260                         [MSG_CHKSUM] = 6,
 261                 },
 262         }
 263 };
 264 
 265 /* API v3 firmware commands */
 266 static const struct dpfe_api dpfe_api_v3 = {
 267         .version = 3,
 268         .fw_name = NULL, /* We expect the firmware to have been downloaded! */
 269         .sysfs_attrs = dpfe_v3_groups,
 270         .command = {
 271                 [DPFE_CMD_GET_INFO] = {
 272                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 273                         [MSG_COMMAND] = 0x0101,
 274                         [MSG_ARG_COUNT] = 1,
 275                         [MSG_ARG0] = 1,
 276                         [MSG_CHKSUM] = 0x104,
 277                 },
 278                 [DPFE_CMD_GET_REFRESH] = {
 279                         [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
 280                         [MSG_COMMAND] = 0x0202,
 281                         [MSG_ARG_COUNT] = 0,
 282                         /*
 283                          * This is a bit ugly. Without arguments, the checksum
 284                          * follows right after the argument count and not at
 285                          * offset MSG_CHKSUM.
 286                          */
 287                         [MSG_ARG0] = 0x203,
 288                 },
 289                 /* There's no GET_VENDOR command in API v3. */
 290         },
 291 };
 292 
 293 static bool is_dcpu_enabled(void __iomem *regs)
 294 {
 295         u32 val;
 296 
 297         val = readl_relaxed(regs + REG_DCPU_RESET);
 298 
 299         return !(val & DCPU_RESET_MASK);
 300 }
 301 
 302 static void __disable_dcpu(void __iomem *regs)
 303 {
 304         u32 val;
 305 
 306         if (!is_dcpu_enabled(regs))
 307                 return;
 308 
 309         /* Put DCPU in reset if it's running. */
 310         val = readl_relaxed(regs + REG_DCPU_RESET);
 311         val |= (1 << DCPU_RESET_SHIFT);
 312         writel_relaxed(val, regs + REG_DCPU_RESET);
 313 }
 314 
 315 static void __enable_dcpu(void __iomem *regs)
 316 {
 317         u32 val;
 318 
 319         /* Clear mailbox registers. */
 320         writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
 321         writel_relaxed(0, regs + REG_TO_HOST_MBOX);
 322 
 323         /* Disable DCPU clock gating */
 324         val = readl_relaxed(regs + REG_DCPU_RESET);
 325         val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
 326         writel_relaxed(val, regs + REG_DCPU_RESET);
 327 
 328         /* Take DCPU out of reset */
 329         val = readl_relaxed(regs + REG_DCPU_RESET);
 330         val &= ~(1 << DCPU_RESET_SHIFT);
 331         writel_relaxed(val, regs + REG_DCPU_RESET);
 332 }
 333 
 334 static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
 335 {
 336         unsigned int sum = 0;
 337         unsigned int i;
 338 
 339         /* Don't include the last field in the checksum. */
 340         for (i = 0; i < max; i++)
 341                 sum += msg[i];
 342 
 343         return sum;
 344 }
 345 
 346 static void __iomem *get_msg_ptr(struct private_data *priv, u32 response,
 347                                  char *buf, ssize_t *size)
 348 {
 349         unsigned int msg_type;
 350         unsigned int offset;
 351         void __iomem *ptr = NULL;
 352 
 353         /* There is no need to use this function for API v3 or later. */
 354         if (unlikely(priv->dpfe_api->version >= 3)) {
 355                 return NULL;
 356         }
 357 
 358         msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
 359         offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
 360 
 361         /*
 362          * msg_type == 1: the offset is relative to the message RAM
 363          * msg_type == 0: the offset is relative to the data RAM (this is the
 364          *                previous way of passing data)
 365          * msg_type is anything else: there's critical hardware problem
 366          */
 367         switch (msg_type) {
 368         case 1:
 369                 ptr = priv->regs + DCPU_MSG_RAM_START + offset;
 370                 break;
 371         case 0:
 372                 ptr = priv->dmem + offset;
 373                 break;
 374         default:
 375                 dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
 376                         response);
 377                 if (buf && size)
 378                         *size = sprintf(buf,
 379                                 "FATAL: communication error with DCPU\n");
 380         }
 381 
 382         return ptr;
 383 }
 384 
 385 static void __finalize_command(struct private_data *priv)
 386 {
 387         unsigned int release_mbox;
 388 
 389         /*
 390          * It depends on the API version which MBOX register we have to write to
 391          * to signal we are done.
 392          */
 393         release_mbox = (priv->dpfe_api->version < 3)
 394                         ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
 395         writel_relaxed(0, priv->regs + release_mbox);
 396 }
 397 
 398 static int __send_command(struct private_data *priv, unsigned int cmd,
 399                           u32 result[])
 400 {
 401         const u32 *msg = priv->dpfe_api->command[cmd];
 402         void __iomem *regs = priv->regs;
 403         unsigned int i, chksum, chksum_idx;
 404         int ret = 0;
 405         u32 resp;
 406 
 407         if (cmd >= DPFE_CMD_MAX)
 408                 return -1;
 409 
 410         mutex_lock(&priv->lock);
 411 
 412         /* Wait for DCPU to become ready */
 413         for (i = 0; i < DELAY_LOOP_MAX; i++) {
 414                 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
 415                 if (resp == 0)
 416                         break;
 417                 msleep(1);
 418         }
 419         if (resp != 0) {
 420                 mutex_unlock(&priv->lock);
 421                 return -ETIMEDOUT;
 422         }
 423 
 424         /* Write command and arguments to message area */
 425         for (i = 0; i < MSG_FIELD_MAX; i++)
 426                 writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
 427 
 428         /* Tell DCPU there is a command waiting */
 429         writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
 430 
 431         /* Wait for DCPU to process the command */
 432         for (i = 0; i < DELAY_LOOP_MAX; i++) {
 433                 /* Read response code */
 434                 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
 435                 if (resp > 0)
 436                         break;
 437                 msleep(1);
 438         }
 439 
 440         if (i == DELAY_LOOP_MAX) {
 441                 resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
 442                 ret = -ffs(resp);
 443         } else {
 444                 /* Read response data */
 445                 for (i = 0; i < MSG_FIELD_MAX; i++)
 446                         result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
 447                 chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
 448         }
 449 
 450         /* Tell DCPU we are done */
 451         __finalize_command(priv);
 452 
 453         mutex_unlock(&priv->lock);
 454 
 455         if (ret)
 456                 return ret;
 457 
 458         /* Verify response */
 459         chksum = get_msg_chksum(result, chksum_idx);
 460         if (chksum != result[chksum_idx])
 461                 resp = DCPU_RET_ERR_CHKSUM;
 462 
 463         if (resp != DCPU_RET_SUCCESS) {
 464                 resp &= ~DCPU_RET_ERROR_BIT;
 465                 ret = -ffs(resp);
 466         }
 467 
 468         return ret;
 469 }
 470 
 471 /* Ensure that the firmware file loaded meets all the requirements. */
 472 static int __verify_firmware(struct init_data *init,
 473                              const struct firmware *fw)
 474 {
 475         const struct dpfe_firmware_header *header = (void *)fw->data;
 476         unsigned int dmem_size, imem_size, total_size;
 477         bool is_big_endian = false;
 478         const u32 *chksum_ptr;
 479 
 480         if (header->magic == DPFE_BE_MAGIC)
 481                 is_big_endian = true;
 482         else if (header->magic != DPFE_LE_MAGIC)
 483                 return ERR_INVALID_MAGIC;
 484 
 485         if (is_big_endian) {
 486                 dmem_size = be32_to_cpu(header->dmem_size);
 487                 imem_size = be32_to_cpu(header->imem_size);
 488         } else {
 489                 dmem_size = le32_to_cpu(header->dmem_size);
 490                 imem_size = le32_to_cpu(header->imem_size);
 491         }
 492 
 493         /* Data and instruction sections are 32 bit words. */
 494         if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
 495                 return ERR_INVALID_SIZE;
 496 
 497         /*
 498          * The header + the data section + the instruction section + the
 499          * checksum must be equal to the total firmware size.
 500          */
 501         total_size = dmem_size + imem_size + sizeof(*header) +
 502                 sizeof(*chksum_ptr);
 503         if (total_size != fw->size)
 504                 return ERR_INVALID_SIZE;
 505 
 506         /* The checksum comes at the very end. */
 507         chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
 508 
 509         init->is_big_endian = is_big_endian;
 510         init->dmem_len = dmem_size;
 511         init->imem_len = imem_size;
 512         init->chksum = (is_big_endian)
 513                 ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
 514 
 515         return 0;
 516 }
 517 
 518 /* Verify checksum by reading back the firmware from co-processor RAM. */
 519 static int __verify_fw_checksum(struct init_data *init,
 520                                 struct private_data *priv,
 521                                 const struct dpfe_firmware_header *header,
 522                                 u32 checksum)
 523 {
 524         u32 magic, sequence, version, sum;
 525         u32 __iomem *dmem = priv->dmem;
 526         u32 __iomem *imem = priv->imem;
 527         unsigned int i;
 528 
 529         if (init->is_big_endian) {
 530                 magic = be32_to_cpu(header->magic);
 531                 sequence = be32_to_cpu(header->sequence);
 532                 version = be32_to_cpu(header->version);
 533         } else {
 534                 magic = le32_to_cpu(header->magic);
 535                 sequence = le32_to_cpu(header->sequence);
 536                 version = le32_to_cpu(header->version);
 537         }
 538 
 539         sum = magic + sequence + version + init->dmem_len + init->imem_len;
 540 
 541         for (i = 0; i < init->dmem_len / sizeof(u32); i++)
 542                 sum += readl_relaxed(dmem + i);
 543 
 544         for (i = 0; i < init->imem_len / sizeof(u32); i++)
 545                 sum += readl_relaxed(imem + i);
 546 
 547         return (sum == checksum) ? 0 : -1;
 548 }
 549 
 550 static int __write_firmware(u32 __iomem *mem, const u32 *fw,
 551                             unsigned int size, bool is_big_endian)
 552 {
 553         unsigned int i;
 554 
 555         /* Convert size to 32-bit words. */
 556         size /= sizeof(u32);
 557 
 558         /* It is recommended to clear the firmware area first. */
 559         for (i = 0; i < size; i++)
 560                 writel_relaxed(0, mem + i);
 561 
 562         /* Now copy it. */
 563         if (is_big_endian) {
 564                 for (i = 0; i < size; i++)
 565                         writel_relaxed(be32_to_cpu(fw[i]), mem + i);
 566         } else {
 567                 for (i = 0; i < size; i++)
 568                         writel_relaxed(le32_to_cpu(fw[i]), mem + i);
 569         }
 570 
 571         return 0;
 572 }
 573 
 574 static int brcmstb_dpfe_download_firmware(struct platform_device *pdev,
 575                                           struct init_data *init)
 576 {
 577         const struct dpfe_firmware_header *header;
 578         unsigned int dmem_size, imem_size;
 579         struct device *dev = &pdev->dev;
 580         bool is_big_endian = false;
 581         struct private_data *priv;
 582         const struct firmware *fw;
 583         const u32 *dmem, *imem;
 584         const void *fw_blob;
 585         int ret;
 586 
 587         priv = platform_get_drvdata(pdev);
 588 
 589         /*
 590          * Skip downloading the firmware if the DCPU is already running and
 591          * responding to commands.
 592          */
 593         if (is_dcpu_enabled(priv->regs)) {
 594                 u32 response[MSG_FIELD_MAX];
 595 
 596                 ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
 597                 if (!ret)
 598                         return 0;
 599         }
 600 
 601         /*
 602          * If the firmware filename is NULL it means the boot firmware has to
 603          * download the DCPU firmware for us. If that didn't work, we have to
 604          * bail, since downloading it ourselves wouldn't work either.
 605          */
 606         if (!priv->dpfe_api->fw_name)
 607                 return -ENODEV;
 608 
 609         ret = request_firmware(&fw, priv->dpfe_api->fw_name, dev);
 610         /* request_firmware() prints its own error messages. */
 611         if (ret)
 612                 return ret;
 613 
 614         ret = __verify_firmware(init, fw);
 615         if (ret)
 616                 return -EFAULT;
 617 
 618         __disable_dcpu(priv->regs);
 619 
 620         is_big_endian = init->is_big_endian;
 621         dmem_size = init->dmem_len;
 622         imem_size = init->imem_len;
 623 
 624         /* At the beginning of the firmware blob is a header. */
 625         header = (struct dpfe_firmware_header *)fw->data;
 626         /* Void pointer to the beginning of the actual firmware. */
 627         fw_blob = fw->data + sizeof(*header);
 628         /* IMEM comes right after the header. */
 629         imem = fw_blob;
 630         /* DMEM follows after IMEM. */
 631         dmem = fw_blob + imem_size;
 632 
 633         ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
 634         if (ret)
 635                 return ret;
 636         ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
 637         if (ret)
 638                 return ret;
 639 
 640         ret = __verify_fw_checksum(init, priv, header, init->chksum);
 641         if (ret)
 642                 return ret;
 643 
 644         __enable_dcpu(priv->regs);
 645 
 646         return 0;
 647 }
 648 
 649 static ssize_t generic_show(unsigned int command, u32 response[],
 650                             struct private_data *priv, char *buf)
 651 {
 652         int ret;
 653 
 654         if (!priv)
 655                 return sprintf(buf, "ERROR: driver private data not set\n");
 656 
 657         ret = __send_command(priv, command, response);
 658         if (ret < 0)
 659                 return sprintf(buf, "ERROR: %s\n", error_text[-ret]);
 660 
 661         return 0;
 662 }
 663 
 664 static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
 665                          char *buf)
 666 {
 667         u32 response[MSG_FIELD_MAX];
 668         struct private_data *priv;
 669         unsigned int info;
 670         ssize_t ret;
 671 
 672         priv = dev_get_drvdata(dev);
 673         ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
 674         if (ret)
 675                 return ret;
 676 
 677         info = response[MSG_ARG0];
 678 
 679         return sprintf(buf, "%u.%u.%u.%u\n",
 680                        (info >> 24) & 0xff,
 681                        (info >> 16) & 0xff,
 682                        (info >> 8) & 0xff,
 683                        info & 0xff);
 684 }
 685 
 686 static ssize_t show_refresh(struct device *dev,
 687                             struct device_attribute *devattr, char *buf)
 688 {
 689         u32 response[MSG_FIELD_MAX];
 690         void __iomem *info;
 691         struct private_data *priv;
 692         u8 refresh, sr_abort, ppre, thermal_offs, tuf;
 693         u32 mr4;
 694         ssize_t ret;
 695 
 696         priv = dev_get_drvdata(dev);
 697         ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
 698         if (ret)
 699                 return ret;
 700 
 701         info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
 702         if (!info)
 703                 return ret;
 704 
 705         mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
 706                DRAM_INFO_MR4_MASK;
 707 
 708         refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
 709         sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
 710         ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
 711         thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
 712         tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
 713 
 714         return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
 715                        readl_relaxed(info + DRAM_INFO_INTERVAL),
 716                        refresh, sr_abort, ppre, thermal_offs, tuf,
 717                        readl_relaxed(info + DRAM_INFO_ERROR));
 718 }
 719 
 720 static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
 721                           const char *buf, size_t count)
 722 {
 723         u32 response[MSG_FIELD_MAX];
 724         struct private_data *priv;
 725         void __iomem *info;
 726         unsigned long val;
 727         int ret;
 728 
 729         if (kstrtoul(buf, 0, &val) < 0)
 730                 return -EINVAL;
 731 
 732         priv = dev_get_drvdata(dev);
 733         ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
 734         if (ret)
 735                 return ret;
 736 
 737         info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
 738         if (!info)
 739                 return -EIO;
 740 
 741         writel_relaxed(val, info + DRAM_INFO_INTERVAL);
 742 
 743         return count;
 744 }
 745 
 746 static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
 747                            char *buf)
 748 {
 749         u32 response[MSG_FIELD_MAX];
 750         struct private_data *priv;
 751         void __iomem *info;
 752         ssize_t ret;
 753         u32 mr5, mr6, mr7, mr8, err;
 754 
 755         priv = dev_get_drvdata(dev);
 756         ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
 757         if (ret)
 758                 return ret;
 759 
 760         info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
 761         if (!info)
 762                 return ret;
 763 
 764         mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
 765                 DRAM_VENDOR_MASK;
 766         mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
 767                 DRAM_VENDOR_MASK;
 768         mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
 769                 DRAM_VENDOR_MASK;
 770         mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
 771                 DRAM_VENDOR_MASK;
 772         err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
 773 
 774         return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
 775 }
 776 
 777 static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
 778                          char *buf)
 779 {
 780         u32 response[MSG_FIELD_MAX];
 781         struct private_data *priv;
 782         ssize_t ret;
 783         u32 mr4, mr5, mr6, mr7, mr8, err;
 784 
 785         priv = dev_get_drvdata(dev);
 786         ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
 787         if (ret)
 788                 return ret;
 789 
 790         mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
 791         mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
 792         mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
 793         mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
 794         mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
 795         err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
 796 
 797         return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
 798                         mr8, err);
 799 }
 800 
 801 static int brcmstb_dpfe_resume(struct platform_device *pdev)
 802 {
 803         struct init_data init;
 804 
 805         return brcmstb_dpfe_download_firmware(pdev, &init);
 806 }
 807 
 808 static int brcmstb_dpfe_probe(struct platform_device *pdev)
 809 {
 810         struct device *dev = &pdev->dev;
 811         struct private_data *priv;
 812         struct init_data init;
 813         struct resource *res;
 814         int ret;
 815 
 816         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 817         if (!priv)
 818                 return -ENOMEM;
 819 
 820         mutex_init(&priv->lock);
 821         platform_set_drvdata(pdev, priv);
 822 
 823         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
 824         priv->regs = devm_ioremap_resource(dev, res);
 825         if (IS_ERR(priv->regs)) {
 826                 dev_err(dev, "couldn't map DCPU registers\n");
 827                 return -ENODEV;
 828         }
 829 
 830         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
 831         priv->dmem = devm_ioremap_resource(dev, res);
 832         if (IS_ERR(priv->dmem)) {
 833                 dev_err(dev, "Couldn't map DCPU data memory\n");
 834                 return -ENOENT;
 835         }
 836 
 837         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
 838         priv->imem = devm_ioremap_resource(dev, res);
 839         if (IS_ERR(priv->imem)) {
 840                 dev_err(dev, "Couldn't map DCPU instruction memory\n");
 841                 return -ENOENT;
 842         }
 843 
 844         priv->dpfe_api = of_device_get_match_data(dev);
 845         if (unlikely(!priv->dpfe_api)) {
 846                 /*
 847                  * It should be impossible to end up here, but to be safe we
 848                  * check anyway.
 849                  */
 850                 dev_err(dev, "Couldn't determine API\n");
 851                 return -ENOENT;
 852         }
 853 
 854         ret = brcmstb_dpfe_download_firmware(pdev, &init);
 855         if (ret) {
 856                 dev_err(dev, "Couldn't download firmware -- %d\n", ret);
 857                 return ret;
 858         }
 859 
 860         ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
 861         if (!ret)
 862                 dev_info(dev, "registered with API v%d.\n",
 863                          priv->dpfe_api->version);
 864 
 865         return ret;
 866 }
 867 
 868 static int brcmstb_dpfe_remove(struct platform_device *pdev)
 869 {
 870         struct private_data *priv = dev_get_drvdata(&pdev->dev);
 871 
 872         sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
 873 
 874         return 0;
 875 }
 876 
 877 static const struct of_device_id brcmstb_dpfe_of_match[] = {
 878         /* Use legacy API v2 for a select number of chips */
 879         { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_v2 },
 880         { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_v2 },
 881         { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_v2 },
 882         { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_v2 },
 883         /* API v3 is the default going forward */
 884         { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
 885         {}
 886 };
 887 MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
 888 
 889 static struct platform_driver brcmstb_dpfe_driver = {
 890         .driver = {
 891                 .name = DRVNAME,
 892                 .of_match_table = brcmstb_dpfe_of_match,
 893         },
 894         .probe = brcmstb_dpfe_probe,
 895         .remove = brcmstb_dpfe_remove,
 896         .resume = brcmstb_dpfe_resume,
 897 };
 898 
 899 module_platform_driver(brcmstb_dpfe_driver);
 900 
 901 MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
 902 MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
 903 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/memory/brcmstb_dpfe.c

DEFINITIONS
