root/drivers/char/hw_random/iproc-rng200.c

DEFINITIONS

1. iproc_rng200_restart
2. iproc_rng200_read
3. iproc_rng200_init
4. iproc_rng200_cleanup
5. iproc_rng200_probe

   1 /*
   2 * Copyright (C) 2015 Broadcom Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation version 2.
   7 *
   8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9 * kind, whether express or implied; without even the implied warranty
  10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 /*
  14  * DESCRIPTION: The Broadcom iProc RNG200 Driver
  15  */
  16 
  17 #include <linux/hw_random.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/delay.h>
  26 
  27 /* Registers */
  28 #define RNG_CTRL_OFFSET                                 0x00
  29 #define RNG_CTRL_RNG_RBGEN_MASK                         0x00001FFF
  30 #define RNG_CTRL_RNG_RBGEN_ENABLE                       0x00000001
  31 #define RNG_CTRL_RNG_RBGEN_DISABLE                      0x00000000
  32 
  33 #define RNG_SOFT_RESET_OFFSET                           0x04
  34 #define RNG_SOFT_RESET                                  0x00000001
  35 
  36 #define RBG_SOFT_RESET_OFFSET                           0x08
  37 #define RBG_SOFT_RESET                                  0x00000001
  38 
  39 #define RNG_INT_STATUS_OFFSET                           0x18
  40 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK     0x80000000
  41 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
  42 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK               0x00000020
  43 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK        0x00000001
  44 
  45 #define RNG_FIFO_DATA_OFFSET                            0x20
  46 
  47 #define RNG_FIFO_COUNT_OFFSET                           0x24
  48 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK              0x000000FF
  49 
  50 struct iproc_rng200_dev {
  51         struct hwrng rng;
  52         void __iomem *base;
  53 };
  54 
  55 #define to_rng_priv(rng)        container_of(rng, struct iproc_rng200_dev, rng)
  56 
  57 static void iproc_rng200_restart(void __iomem *rng_base)
  58 {
  59         uint32_t val;
  60 
  61         /* Disable RBG */
  62         val = ioread32(rng_base + RNG_CTRL_OFFSET);
  63         val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  64         val |= RNG_CTRL_RNG_RBGEN_DISABLE;
  65         iowrite32(val, rng_base + RNG_CTRL_OFFSET);
  66 
  67         /* Clear all interrupt status */
  68         iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
  69 
  70         /* Reset RNG and RBG */
  71         val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  72         val |= RBG_SOFT_RESET;
  73         iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  74 
  75         val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  76         val |= RNG_SOFT_RESET;
  77         iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  78 
  79         val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  80         val &= ~RNG_SOFT_RESET;
  81         iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  82 
  83         val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  84         val &= ~RBG_SOFT_RESET;
  85         iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  86 
  87         /* Enable RBG */
  88         val = ioread32(rng_base + RNG_CTRL_OFFSET);
  89         val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  90         val |= RNG_CTRL_RNG_RBGEN_ENABLE;
  91         iowrite32(val, rng_base + RNG_CTRL_OFFSET);
  92 }
  93 
  94 static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
  95                              bool wait)
  96 {
  97         struct iproc_rng200_dev *priv = to_rng_priv(rng);
  98         uint32_t num_remaining = max;
  99         uint32_t status;
 100 
 101         #define MAX_RESETS_PER_READ     1
 102         uint32_t num_resets = 0;
 103 
 104         #define MAX_IDLE_TIME   (1 * HZ)
 105         unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
 106 
 107         while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
 108 
 109                 /* Is RNG sane? If not, reset it. */
 110                 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
 111                 if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
 112                         RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
 113 
 114                         if (num_resets >= MAX_RESETS_PER_READ)
 115                                 return max - num_remaining;
 116 
 117                         iproc_rng200_restart(priv->base);
 118                         num_resets++;
 119                 }
 120 
 121                 /* Are there any random numbers available? */
 122                 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
 123                                 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
 124 
 125                         if (num_remaining >= sizeof(uint32_t)) {
 126                                 /* Buffer has room to store entire word */
 127                                 *(uint32_t *)buf = ioread32(priv->base +
 128                                                         RNG_FIFO_DATA_OFFSET);
 129                                 buf += sizeof(uint32_t);
 130                                 num_remaining -= sizeof(uint32_t);
 131                         } else {
 132                                 /* Buffer can only store partial word */
 133                                 uint32_t rnd_number = ioread32(priv->base +
 134                                                         RNG_FIFO_DATA_OFFSET);
 135                                 memcpy(buf, &rnd_number, num_remaining);
 136                                 buf += num_remaining;
 137                                 num_remaining = 0;
 138                         }
 139 
 140                         /* Reset the IDLE timeout */
 141                         idle_endtime = jiffies + MAX_IDLE_TIME;
 142                 } else {
 143                         if (!wait)
 144                                 /* Cannot wait, return immediately */
 145                                 return max - num_remaining;
 146 
 147                         /* Can wait, give others chance to run */
 148                         usleep_range(min(num_remaining * 10, 500U), 500);
 149                 }
 150         }
 151 
 152         return max - num_remaining;
 153 }
 154 
 155 static int iproc_rng200_init(struct hwrng *rng)
 156 {
 157         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 158         uint32_t val;
 159 
 160         /* Setup RNG. */
 161         val = ioread32(priv->base + RNG_CTRL_OFFSET);
 162         val &= ~RNG_CTRL_RNG_RBGEN_MASK;
 163         val |= RNG_CTRL_RNG_RBGEN_ENABLE;
 164         iowrite32(val, priv->base + RNG_CTRL_OFFSET);
 165 
 166         return 0;
 167 }
 168 
 169 static void iproc_rng200_cleanup(struct hwrng *rng)
 170 {
 171         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 172         uint32_t val;
 173 
 174         /* Disable RNG hardware */
 175         val = ioread32(priv->base + RNG_CTRL_OFFSET);
 176         val &= ~RNG_CTRL_RNG_RBGEN_MASK;
 177         val |= RNG_CTRL_RNG_RBGEN_DISABLE;
 178         iowrite32(val, priv->base + RNG_CTRL_OFFSET);
 179 }
 180 
 181 static int iproc_rng200_probe(struct platform_device *pdev)
 182 {
 183         struct iproc_rng200_dev *priv;
 184         struct resource *res;
 185         struct device *dev = &pdev->dev;
 186         int ret;
 187 
 188         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 189         if (!priv)
 190                 return -ENOMEM;
 191 
 192         /* Map peripheral */
 193         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 194         if (!res) {
 195                 dev_err(dev, "failed to get rng resources\n");
 196                 return -EINVAL;
 197         }
 198 
 199         priv->base = devm_ioremap_resource(dev, res);
 200         if (IS_ERR(priv->base)) {
 201                 dev_err(dev, "failed to remap rng regs\n");
 202                 return PTR_ERR(priv->base);
 203         }
 204 
 205         priv->rng.name = "iproc-rng200",
 206         priv->rng.read = iproc_rng200_read,
 207         priv->rng.init = iproc_rng200_init,
 208         priv->rng.cleanup = iproc_rng200_cleanup,
 209 
 210         /* Register driver */
 211         ret = devm_hwrng_register(dev, &priv->rng);
 212         if (ret) {
 213                 dev_err(dev, "hwrng registration failed\n");
 214                 return ret;
 215         }
 216 
 217         dev_info(dev, "hwrng registered\n");
 218 
 219         return 0;
 220 }
 221 
 222 static const struct of_device_id iproc_rng200_of_match[] = {
 223         { .compatible = "brcm,bcm7211-rng200", },
 224         { .compatible = "brcm,bcm7278-rng200", },
 225         { .compatible = "brcm,iproc-rng200", },
 226         {},
 227 };
 228 MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
 229 
 230 static struct platform_driver iproc_rng200_driver = {
 231         .driver = {
 232                 .name           = "iproc-rng200",
 233                 .of_match_table = iproc_rng200_of_match,
 234         },
 235         .probe          = iproc_rng200_probe,
 236 };
 237 module_platform_driver(iproc_rng200_driver);
 238 
 239 MODULE_AUTHOR("Broadcom");
 240 MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
 241 MODULE_LICENSE("GPL v2");