This source file includes following definitions.
- rtw8822be_efuse_parsing
- rtw8822b_read_efuse
- rtw8822b_phy_rfe_init
- rtw8822b_phy_set_param
- rtw8822b_mac_init
- rtw8822b_set_channel_rfe_efem
- rtw8822b_set_channel_rfe_ifem
- rtw8822b_get_cca_val
- rtw8822b_set_channel_cca
- rtw8822b_set_channel_rf
- rtw8822b_toggle_igi
- rtw8822b_set_channel_rxdfir
- rtw8822b_set_channel_bb
- rtw8822b_set_channel
- rtw8822b_config_trx_mode
- query_phy_status_page0
- query_phy_status_page1
- query_phy_status
- rtw8822b_query_rx_desc
- rtw8822b_set_tx_power_index_by_rate
- rtw8822b_set_tx_power_index
- rtw8822b_check_rf_path
- rtw8822b_set_antenna
- rtw8822b_cfg_ldo25
- rtw8822b_false_alarm_statistics
- rtw8822b_do_iqk
- rtw8822b_phy_calibration
- rtw8822b_coex_cfg_init
- rtw8822b_coex_cfg_ant_switch
- rtw8822b_coex_cfg_gnt_fix
- rtw8822b_coex_cfg_gnt_debug
- rtw8822b_coex_cfg_rfe_type
- rtw8822b_coex_cfg_wl_tx_power
- rtw8822b_coex_cfg_wl_rx_gain
1
2
3
4
5 #include "main.h"
6 #include "coex.h"
7 #include "fw.h"
8 #include "tx.h"
9 #include "rx.h"
10 #include "phy.h"
11 #include "rtw8822b.h"
12 #include "rtw8822b_table.h"
13 #include "mac.h"
14 #include "reg.h"
15 #include "debug.h"
16
17 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
18 u8 rx_path, bool is_tx2_path);
19
20 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse,
21 struct rtw8822b_efuse *map)
22 {
23 ether_addr_copy(efuse->addr, map->e.mac_addr);
24 }
25
26 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
27 {
28 struct rtw_efuse *efuse = &rtwdev->efuse;
29 struct rtw8822b_efuse *map;
30 int i;
31
32 map = (struct rtw8822b_efuse *)log_map;
33
34 efuse->rfe_option = map->rfe_option;
35 efuse->rf_board_option = map->rf_board_option;
36 efuse->crystal_cap = map->xtal_k;
37 efuse->pa_type_2g = map->pa_type;
38 efuse->pa_type_5g = map->pa_type;
39 efuse->lna_type_2g = map->lna_type_2g[0];
40 efuse->lna_type_5g = map->lna_type_5g[0];
41 efuse->channel_plan = map->channel_plan;
42 efuse->country_code[0] = map->country_code[0];
43 efuse->country_code[1] = map->country_code[1];
44 efuse->bt_setting = map->rf_bt_setting;
45 efuse->regd = map->rf_board_option & 0x7;
46
47 for (i = 0; i < 4; i++)
48 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
49
50 switch (rtw_hci_type(rtwdev)) {
51 case RTW_HCI_TYPE_PCIE:
52 rtw8822be_efuse_parsing(efuse, map);
53 break;
54 default:
55
56 return -ENOTSUPP;
57 }
58
59 return 0;
60 }
61
62 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev)
63 {
64
65 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
66 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
67 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
68
69
70 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
71 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
72
73
74 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
75 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
76 }
77
78 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
79 {
80 struct rtw_hal *hal = &rtwdev->hal;
81 u8 crystal_cap;
82 bool is_tx2_path;
83
84
85 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
86 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
87 rtw_write8_set(rtwdev, REG_RF_CTRL,
88 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
89 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
90
91
92 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
93
94 rtw_phy_load_tables(rtwdev);
95
96 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
97 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
98 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
99
100
101 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
102
103 is_tx2_path = false;
104 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
105 is_tx2_path);
106 rtw_phy_init(rtwdev);
107
108 rtw8822b_phy_rfe_init(rtwdev);
109 }
110
111 #define WLAN_SLOT_TIME 0x09
112 #define WLAN_PIFS_TIME 0x19
113 #define WLAN_SIFS_CCK_CONT_TX 0xA
114 #define WLAN_SIFS_OFDM_CONT_TX 0xE
115 #define WLAN_SIFS_CCK_TRX 0x10
116 #define WLAN_SIFS_OFDM_TRX 0x10
117 #define WLAN_VO_TXOP_LIMIT 0x186
118 #define WLAN_VI_TXOP_LIMIT 0x3BC
119 #define WLAN_RDG_NAV 0x05
120 #define WLAN_TXOP_NAV 0x1B
121 #define WLAN_CCK_RX_TSF 0x30
122 #define WLAN_OFDM_RX_TSF 0x30
123 #define WLAN_TBTT_PROHIBIT 0x04
124 #define WLAN_TBTT_HOLD_TIME 0x064
125 #define WLAN_DRV_EARLY_INT 0x04
126 #define WLAN_BCN_DMA_TIME 0x02
127
128 #define WLAN_RX_FILTER0 0x0FFFFFFF
129 #define WLAN_RX_FILTER2 0xFFFF
130 #define WLAN_RCR_CFG 0xE400220E
131 #define WLAN_RXPKT_MAX_SZ 12288
132 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
133
134 #define WLAN_AMPDU_MAX_TIME 0x70
135 #define WLAN_RTS_LEN_TH 0xFF
136 #define WLAN_RTS_TX_TIME_TH 0x08
137 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
138 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
139 #define FAST_EDCA_VO_TH 0x06
140 #define FAST_EDCA_VI_TH 0x06
141 #define FAST_EDCA_BE_TH 0x06
142 #define FAST_EDCA_BK_TH 0x06
143 #define WLAN_BAR_RETRY_LIMIT 0x01
144 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
145
146 #define WLAN_TX_FUNC_CFG1 0x30
147 #define WLAN_TX_FUNC_CFG2 0x30
148 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
149 #define WLAN_MAC_OPT_LB_FUNC1 0x80
150 #define WLAN_MAC_OPT_FUNC2 0x30810041
151
152 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
153 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
154 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
155 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
156
157 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
158 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
159
160 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
161 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
162
163 static int rtw8822b_mac_init(struct rtw_dev *rtwdev)
164 {
165 u32 value32;
166
167
168 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD);
169 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
170 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
171 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
172 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
173 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
174 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
175 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
176 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
177 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
178 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
179 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
180 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
181
182 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
183 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
184 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
185 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
186 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
187 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
188 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
189 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
190 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
191
192 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
193
194 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
195 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
196 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
197 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
198
199 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
200 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
201 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
202 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
203 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
204 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
205 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
206 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
207
208 return 0;
209 }
210
211 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel)
212 {
213 struct rtw_hal *hal = &rtwdev->hal;
214 bool is_channel_2g = (channel <= 14) ? true : false;
215
216 if (is_channel_2g) {
217 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770);
218 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
219 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
220 } else {
221 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517);
222 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
223 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
224 }
225
226 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
227
228 if (hal->antenna_rx == BB_PATH_AB ||
229 hal->antenna_tx == BB_PATH_AB) {
230
231 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
232 } else if (hal->antenna_rx == hal->antenna_tx) {
233
234 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
235 } else {
236
237 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
238 }
239 }
240
241 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel)
242 {
243 struct rtw_hal *hal = &rtwdev->hal;
244 bool is_channel_2g = (channel <= 14) ? true : false;
245
246 if (is_channel_2g) {
247
248 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774);
249 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
250 } else {
251
252 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547);
253 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
254 }
255
256 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
257
258 if (is_channel_2g) {
259 if (hal->antenna_rx == BB_PATH_AB ||
260 hal->antenna_tx == BB_PATH_AB) {
261
262 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
263 } else if (hal->antenna_rx == hal->antenna_tx) {
264
265 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
266 } else {
267
268 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
269 }
270 } else {
271 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
272 }
273 }
274
275 enum {
276 CCUT_IDX_1R_2G,
277 CCUT_IDX_2R_2G,
278 CCUT_IDX_1R_5G,
279 CCUT_IDX_2R_5G,
280 CCUT_IDX_NR,
281 };
282
283 struct cca_ccut {
284 u32 reg82c[CCUT_IDX_NR];
285 u32 reg830[CCUT_IDX_NR];
286 u32 reg838[CCUT_IDX_NR];
287 };
288
289 static const struct cca_ccut cca_ifem_ccut = {
290 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010},
291 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa},
292 {0x87765541, 0x87746341, 0x87765541, 0x87746341},
293 };
294
295 static const struct cca_ccut cca_efem_ccut = {
296 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010},
297 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa},
298 {0x87766451, 0x87766431, 0x87766451, 0x87766431},
299 };
300
301 static const struct cca_ccut cca_ifem_ccut_ext = {
302 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010},
303 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa},
304 {0x87765541, 0x86666341, 0x87765561, 0x86666361},
305 };
306
307 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col,
308 u32 *reg82c, u32 *reg830, u32 *reg838)
309 {
310 *reg82c = cca_ccut->reg82c[col];
311 *reg830 = cca_ccut->reg830[col];
312 *reg838 = cca_ccut->reg838[col];
313 }
314
315 struct rtw8822b_rfe_info {
316 const struct cca_ccut *cca_ccut_2g;
317 const struct cca_ccut *cca_ccut_5g;
318 enum rtw_rfe_fem fem;
319 bool ifem_ext;
320 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel);
321 };
322
323 #define I2GE5G_CCUT(set_ch) { \
324 .cca_ccut_2g = &cca_ifem_ccut, \
325 .cca_ccut_5g = &cca_efem_ccut, \
326 .fem = RTW_RFE_IFEM2G_EFEM5G, \
327 .ifem_ext = false, \
328 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
329 }
330 #define IFEM_EXT_CCUT(set_ch) { \
331 .cca_ccut_2g = &cca_ifem_ccut_ext, \
332 .cca_ccut_5g = &cca_ifem_ccut_ext, \
333 .fem = RTW_RFE_IFEM, \
334 .ifem_ext = true, \
335 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
336 }
337
338 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = {
339 [2] = I2GE5G_CCUT(efem),
340 [5] = IFEM_EXT_CCUT(ifem),
341 };
342
343 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw,
344 const struct rtw8822b_rfe_info *rfe_info)
345 {
346 struct rtw_hal *hal = &rtwdev->hal;
347 struct rtw_efuse *efuse = &rtwdev->efuse;
348 const struct cca_ccut *cca_ccut;
349 u8 col;
350 u32 reg82c, reg830, reg838;
351 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false;
352
353 if (channel <= 14) {
354 cca_ccut = rfe_info->cca_ccut_2g;
355
356 if (hal->antenna_rx == BB_PATH_A ||
357 hal->antenna_rx == BB_PATH_B)
358 col = CCUT_IDX_1R_2G;
359 else
360 col = CCUT_IDX_2R_2G;
361 } else {
362 cca_ccut = rfe_info->cca_ccut_5g;
363
364 if (hal->antenna_rx == BB_PATH_A ||
365 hal->antenna_rx == BB_PATH_B)
366 col = CCUT_IDX_1R_5G;
367 else
368 col = CCUT_IDX_2R_5G;
369 }
370
371 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838);
372
373 switch (rfe_info->fem) {
374 case RTW_RFE_IFEM:
375 default:
376 is_ifem_cca = true;
377 if (rfe_info->ifem_ext)
378 is_rfe_type = true;
379 break;
380 case RTW_RFE_EFEM:
381 is_efem_cca = true;
382 break;
383 case RTW_RFE_IFEM2G_EFEM5G:
384 if (channel <= 14)
385 is_ifem_cca = true;
386 else
387 is_efem_cca = true;
388 break;
389 }
390
391 if (is_ifem_cca) {
392 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
393 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) &&
394 bw == RTW_CHANNEL_WIDTH_40) ||
395 (!is_rfe_type && col == CCUT_IDX_2R_5G &&
396 bw == RTW_CHANNEL_WIDTH_40) ||
397 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
398 reg830 = 0x79a0ea28;
399 }
400
401 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c);
402 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830);
403 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838);
404
405 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
406 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9);
407
408 if (bw == RTW_CHANNEL_WIDTH_20 &&
409 ((channel >= 52 && channel <= 64) ||
410 (channel >= 100 && channel <= 144)))
411 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4);
412 }
413
414 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
415 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
416 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
417 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
418 0x6, 0x5, 0x0, 0x0, 0x7};
419 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
420 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
421
422 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
423 {
424 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
425 #define RF18_BAND_2G (0)
426 #define RF18_BAND_5G (BIT(16) | BIT(8))
427 #define RF18_CHANNEL_MASK (MASKBYTE0)
428 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
429 #define RF18_RFSI_GE_CH80 (BIT(17))
430 #define RF18_RFSI_GT_CH144 (BIT(18))
431 #define RF18_BW_MASK (BIT(11) | BIT(10))
432 #define RF18_BW_20M (BIT(11) | BIT(10))
433 #define RF18_BW_40M (BIT(11))
434 #define RF18_BW_80M (BIT(10))
435 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
436
437 struct rtw_hal *hal = &rtwdev->hal;
438 u32 rf_reg18, rf_reg_be;
439
440 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
441
442 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
443 RF18_BW_MASK);
444
445 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
446 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
447 if (channel > 144)
448 rf_reg18 |= RF18_RFSI_GT_CH144;
449 else if (channel >= 80)
450 rf_reg18 |= RF18_RFSI_GE_CH80;
451
452 switch (bw) {
453 case RTW_CHANNEL_WIDTH_5:
454 case RTW_CHANNEL_WIDTH_10:
455 case RTW_CHANNEL_WIDTH_20:
456 default:
457 rf_reg18 |= RF18_BW_20M;
458 break;
459 case RTW_CHANNEL_WIDTH_40:
460 rf_reg18 |= RF18_BW_40M;
461 break;
462 case RTW_CHANNEL_WIDTH_80:
463 rf_reg18 |= RF18_BW_80M;
464 break;
465 }
466
467 if (channel <= 14)
468 rf_reg_be = 0x0;
469 else if (channel >= 36 && channel <= 64)
470 rf_reg_be = low_band[(channel - 36) >> 1];
471 else if (channel >= 100 && channel <= 144)
472 rf_reg_be = middle_band[(channel - 100) >> 1];
473 else if (channel >= 149 && channel <= 177)
474 rf_reg_be = high_band[(channel - 149) >> 1];
475 else
476 goto err;
477
478 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be);
479
480
481 if (channel == 144)
482 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
483 else
484 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
485
486 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
487 if (hal->rf_type > RF_1T1R)
488 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18);
489
490 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
491 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
492
493 return;
494
495 err:
496 WARN_ON(1);
497 }
498
499 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev)
500 {
501 struct rtw_hal *hal = &rtwdev->hal;
502 u32 igi;
503
504 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
505 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
506 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi);
507 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
508 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi);
509
510 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0);
511 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0,
512 hal->antenna_rx | (hal->antenna_rx << 4));
513 }
514
515 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
516 {
517 if (bw == RTW_CHANNEL_WIDTH_40) {
518
519 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
520 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
521 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
522 } else if (bw == RTW_CHANNEL_WIDTH_80) {
523
524 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
525 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
526 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
527 } else {
528
529 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
530 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
531 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
532 }
533 }
534
535 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
536 u8 primary_ch_idx)
537 {
538 struct rtw_efuse *efuse = &rtwdev->efuse;
539 u8 rfe_option = efuse->rfe_option;
540 u32 val32;
541
542 if (channel <= 14) {
543 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
544 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
545 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
546 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
547
548 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0);
549 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
550 if (channel == 14) {
551 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577);
552 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
553 } else {
554 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577);
555 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
556 }
557
558 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2);
559 } else if (channel > 35) {
560 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
561 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
562 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
563 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34);
564
565 if (channel >= 36 && channel <= 64)
566 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1);
567 else if (channel >= 100 && channel <= 144)
568 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2);
569 else if (channel >= 149)
570 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3);
571
572 if (channel >= 36 && channel <= 48)
573 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
574 else if (channel >= 52 && channel <= 64)
575 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
576 else if (channel >= 100 && channel <= 116)
577 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
578 else if (channel >= 118 && channel <= 177)
579 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
580
581 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1);
582 }
583
584 switch (bw) {
585 case RTW_CHANNEL_WIDTH_20:
586 default:
587 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
588 val32 &= 0xFFCFFC00;
589 val32 |= (RTW_CHANNEL_WIDTH_20);
590 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
591
592 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
593 break;
594 case RTW_CHANNEL_WIDTH_40:
595 if (primary_ch_idx == 1)
596 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
597 else
598 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
599
600 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
601 val32 &= 0xFF3FF300;
602 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40);
603 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
604
605 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
606 break;
607 case RTW_CHANNEL_WIDTH_80:
608 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
609 val32 &= 0xFCEFCF00;
610 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80);
611 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
612
613 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
614
615 if (rfe_option == 2) {
616 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6);
617 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
618 }
619 break;
620 case RTW_CHANNEL_WIDTH_5:
621 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
622 val32 &= 0xEFEEFE00;
623 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
624 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
625
626 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
627 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
628 break;
629 case RTW_CHANNEL_WIDTH_10:
630 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
631 val32 &= 0xEFFEFF00;
632 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
633 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
634
635 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
636 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
637 break;
638 }
639 }
640
641 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
642 u8 primary_chan_idx)
643 {
644 struct rtw_efuse *efuse = &rtwdev->efuse;
645 const struct rtw8822b_rfe_info *rfe_info;
646
647 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
648 "rfe_option %d is out of boundary\n", efuse->rfe_option))
649 return;
650
651 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
652
653 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
654 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
655 rtw8822b_set_channel_rf(rtwdev, channel, bw);
656 rtw8822b_set_channel_rxdfir(rtwdev, bw);
657 rtw8822b_toggle_igi(rtwdev);
658 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info);
659 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
660 }
661
662 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
663 u8 rx_path, bool is_tx2_path)
664 {
665 struct rtw_efuse *efuse = &rtwdev->efuse;
666 const struct rtw8822b_rfe_info *rfe_info;
667 u8 ch = rtwdev->hal.current_channel;
668 u8 tx_path_sel, rx_path_sel;
669 int counter;
670
671 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
672 "rfe_option %d is out of boundary\n", efuse->rfe_option))
673 return;
674
675 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
676
677 if ((tx_path | rx_path) & BB_PATH_A)
678 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
679 else
680 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
681
682 if ((tx_path | rx_path) & BB_PATH_B)
683 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
684 else
685 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
686
687 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
688 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
689 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
690
691 if (tx_path & BB_PATH_A) {
692 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001);
693 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8);
694 } else if (tx_path & BB_PATH_B) {
695 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002);
696 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4);
697 }
698
699 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B)
700 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01);
701 else
702 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43);
703
704 tx_path_sel = (tx_path << 4) | tx_path;
705 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel);
706
707 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) {
708 if (is_tx2_path || rtwdev->mp_mode) {
709 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043);
710 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc);
711 }
712 }
713
714 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
715 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
716
717 if (rx_path & BB_PATH_A)
718 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0);
719 else if (rx_path & BB_PATH_B)
720 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5);
721
722 rx_path_sel = (rx_path << 4) | rx_path;
723 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel);
724
725 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
726 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
727 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
728 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
729 } else {
730 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
731 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
732 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
733 }
734
735 for (counter = 100; counter > 0; counter--) {
736 u32 rf_reg33;
737
738 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
739 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
740
741 udelay(2);
742 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK);
743
744 if (rf_reg33 == 0x00001)
745 break;
746 }
747
748 if (WARN(counter <= 0, "write RF mode table fail\n"))
749 return;
750
751 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
752 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
753 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034);
754 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c);
755 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
756 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
757
758 rtw8822b_toggle_igi(rtwdev);
759 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info);
760 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
761 }
762
763 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
764 struct rtw_rx_pkt_stat *pkt_stat)
765 {
766 s8 min_rx_power = -120;
767 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
768
769
770 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
771 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
772 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
773 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
774 min_rx_power);
775 }
776
777 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
778 struct rtw_rx_pkt_stat *pkt_stat)
779 {
780 u8 rxsc, bw;
781 s8 min_rx_power = -120;
782
783 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
784 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
785 else
786 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
787
788 if (rxsc >= 1 && rxsc <= 8)
789 bw = RTW_CHANNEL_WIDTH_20;
790 else if (rxsc >= 9 && rxsc <= 12)
791 bw = RTW_CHANNEL_WIDTH_40;
792 else if (rxsc >= 13)
793 bw = RTW_CHANNEL_WIDTH_80;
794 else
795 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
796
797 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
798 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
799 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
800 pkt_stat->bw = bw;
801 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
802 pkt_stat->rx_power[RF_PATH_B],
803 min_rx_power);
804 }
805
806 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
807 struct rtw_rx_pkt_stat *pkt_stat)
808 {
809 u8 page;
810
811 page = *phy_status & 0xf;
812
813 switch (page) {
814 case 0:
815 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
816 break;
817 case 1:
818 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
819 break;
820 default:
821 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
822 return;
823 }
824 }
825
826 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
827 struct rtw_rx_pkt_stat *pkt_stat,
828 struct ieee80211_rx_status *rx_status)
829 {
830 struct ieee80211_hdr *hdr;
831 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
832 u8 *phy_status = NULL;
833
834 memset(pkt_stat, 0, sizeof(*pkt_stat));
835
836 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
837 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
838 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
839 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc);
840 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
841 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
842 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
843 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
844 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
845 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
846 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
847 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
848
849
850 pkt_stat->drv_info_sz *= 8;
851
852
853 if (pkt_stat->is_c2h)
854 return;
855
856 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
857 pkt_stat->drv_info_sz);
858 if (pkt_stat->phy_status) {
859 phy_status = rx_desc + desc_sz + pkt_stat->shift;
860 query_phy_status(rtwdev, phy_status, pkt_stat);
861 }
862
863 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
864 }
865
866 static void
867 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
868 {
869 struct rtw_hal *hal = &rtwdev->hal;
870 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
871 static u32 phy_pwr_idx;
872 u8 rate, rate_idx, pwr_index, shift;
873 int j;
874
875 for (j = 0; j < rtw_rate_size[rs]; j++) {
876 rate = rtw_rate_section[rs][j];
877 pwr_index = hal->tx_pwr_tbl[path][rate];
878 shift = rate & 0x3;
879 phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
880 if (shift == 0x3) {
881 rate_idx = rate & 0xfc;
882 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
883 phy_pwr_idx);
884 phy_pwr_idx = 0;
885 }
886 }
887 }
888
889 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev)
890 {
891 struct rtw_hal *hal = &rtwdev->hal;
892 int rs, path;
893
894 for (path = 0; path < hal->rf_path_num; path++) {
895 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
896 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs);
897 }
898 }
899
900 static bool rtw8822b_check_rf_path(u8 antenna)
901 {
902 switch (antenna) {
903 case BB_PATH_A:
904 case BB_PATH_B:
905 case BB_PATH_AB:
906 return true;
907 default:
908 return false;
909 }
910 }
911
912 static void rtw8822b_set_antenna(struct rtw_dev *rtwdev, u8 antenna_tx,
913 u8 antenna_rx)
914 {
915 struct rtw_hal *hal = &rtwdev->hal;
916
917 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
918 antenna_tx, antenna_rx);
919
920 if (!rtw8822b_check_rf_path(antenna_tx)) {
921 rtw_info(rtwdev, "unsupport tx path, set to default path ab\n");
922 antenna_tx = BB_PATH_AB;
923 }
924 if (!rtw8822b_check_rf_path(antenna_rx)) {
925 rtw_info(rtwdev, "unsupport rx path, set to default path ab\n");
926 antenna_rx = BB_PATH_AB;
927 }
928 hal->antenna_tx = antenna_tx;
929 hal->antenna_rx = antenna_rx;
930 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
931 }
932
933 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
934 {
935 u8 ldo_pwr;
936
937 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
938 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
939 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
940 }
941
942 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
943 {
944 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
945 u32 cck_enable;
946 u32 cck_fa_cnt;
947 u32 ofdm_fa_cnt;
948 u32 crc32_cnt;
949
950 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
951 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
952 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48);
953
954 dm_info->cck_fa_cnt = cck_fa_cnt;
955 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
956 dm_info->total_fa_cnt = ofdm_fa_cnt;
957 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
958
959 crc32_cnt = rtw_read32(rtwdev, 0xf04);
960 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
961 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
962 crc32_cnt = rtw_read32(rtwdev, 0xf14);
963 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
964 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
965 crc32_cnt = rtw_read32(rtwdev, 0xf10);
966 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
967 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
968 crc32_cnt = rtw_read32(rtwdev, 0xf0c);
969 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
970 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
971
972 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
973 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
974 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
975 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
976 rtw_write32_set(rtwdev, 0xb58, BIT(0));
977 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
978 }
979
980 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
981 {
982 static int do_iqk_cnt;
983 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
984 u32 rf_reg, iqk_fail_mask;
985 int counter;
986 bool reload;
987
988 rtw_fw_do_iqk(rtwdev, ¶);
989
990 for (counter = 0; counter < 300; counter++) {
991 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
992 if (rf_reg == 0xabcde)
993 break;
994 msleep(20);
995 }
996 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
997
998 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
999 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
1000 rtw_dbg(rtwdev, RTW_DBG_PHY,
1001 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
1002 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
1003 }
1004
1005 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev)
1006 {
1007 rtw8822b_do_iqk(rtwdev);
1008 }
1009
1010 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev)
1011 {
1012
1013 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1014
1015
1016
1017 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
1018
1019
1020 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1021
1022
1023 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1024 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
1025
1026
1027 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1028
1029 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
1030
1031 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
1032 }
1033
1034 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,
1035 u8 ctrl_type, u8 pos_type)
1036 {
1037 struct rtw_coex *coex = &rtwdev->coex;
1038 struct rtw_coex_dm *coex_dm = &coex->dm;
1039 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1040 bool polarity_inverse;
1041 u8 regval = 0;
1042
1043 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1044 return;
1045
1046 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1047
1048 if (coex_rfe->ant_switch_diversity &&
1049 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
1050 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
1051
1052 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1053
1054 switch (ctrl_type) {
1055 default:
1056 case COEX_SWITCH_CTRL_BY_BBSW:
1057
1058 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1059
1060 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1061
1062 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
1063
1064 if (pos_type == COEX_SWITCH_TO_WLG_BT) {
1065 if (coex_rfe->rfe_module_type != 0x4 &&
1066 coex_rfe->rfe_module_type != 0x2)
1067 regval = 0x3;
1068 else
1069 regval = (!polarity_inverse ? 0x2 : 0x1);
1070 } else if (pos_type == COEX_SWITCH_TO_WLG) {
1071 regval = (!polarity_inverse ? 0x2 : 0x1);
1072 } else {
1073 regval = (!polarity_inverse ? 0x1 : 0x2);
1074 }
1075
1076 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1077 break;
1078 case COEX_SWITCH_CTRL_BY_PTA:
1079
1080 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1081
1082 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1083
1084 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
1085
1086 regval = (!polarity_inverse ? 0x2 : 0x1);
1087 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1088 break;
1089 case COEX_SWITCH_CTRL_BY_ANTDIV:
1090
1091 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1092
1093 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1094 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
1095 break;
1096 case COEX_SWITCH_CTRL_BY_MAC:
1097
1098 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
1099
1100 regval = (!polarity_inverse ? 0x0 : 0x1);
1101 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);
1102 break;
1103 case COEX_SWITCH_CTRL_BY_FW:
1104
1105 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1106
1107 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1108 break;
1109 case COEX_SWITCH_CTRL_BY_BT:
1110
1111 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1112
1113 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
1114 break;
1115 }
1116 }
1117
1118 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1119 {
1120 }
1121
1122 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1123 {
1124 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
1125 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
1126 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
1127 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
1128 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
1129 }
1130
1131 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1132 {
1133 struct rtw_coex *coex = &rtwdev->coex;
1134 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1135 struct rtw_efuse *efuse = &rtwdev->efuse;
1136 bool is_ext_fem = false;
1137
1138 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1139 coex_rfe->ant_switch_polarity = 0;
1140 coex_rfe->ant_switch_diversity = false;
1141 if (coex_rfe->rfe_module_type == 0x12 ||
1142 coex_rfe->rfe_module_type == 0x15 ||
1143 coex_rfe->rfe_module_type == 0x16)
1144 coex_rfe->ant_switch_exist = false;
1145 else
1146 coex_rfe->ant_switch_exist = true;
1147
1148 if (coex_rfe->rfe_module_type == 2 ||
1149 coex_rfe->rfe_module_type == 4) {
1150 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true);
1151 is_ext_fem = true;
1152 } else {
1153 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false);
1154 }
1155
1156 coex_rfe->wlg_at_btg = false;
1157
1158 if (efuse->share_ant &&
1159 coex_rfe->ant_switch_exist && !is_ext_fem)
1160 coex_rfe->ant_switch_with_bt = true;
1161 else
1162 coex_rfe->ant_switch_with_bt = false;
1163
1164
1165 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
1166 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
1167 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
1168
1169
1170 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
1171
1172
1173 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1174
1175
1176 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1177 }
1178
1179 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1180 {
1181 struct rtw_coex *coex = &rtwdev->coex;
1182 struct rtw_coex_dm *coex_dm = &coex->dm;
1183 static const u16 reg_addr[] = {0xc58, 0xe58};
1184 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
1185 u8 i, pwr;
1186
1187 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1188 return;
1189
1190 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1191
1192 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1193 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1194
1195 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1196
1197 for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
1198 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
1199 }
1200
1201 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1202 {
1203 struct rtw_coex *coex = &rtwdev->coex;
1204 struct rtw_coex_dm *coex_dm = &coex->dm;
1205
1206 static const u32 wl_rx_low_gain_on[] = {
1207 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
1208 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
1209 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
1210 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
1211 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
1212 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
1213 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
1214 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
1215 0x007e0403
1216 };
1217
1218
1219 static const u32 wl_rx_low_gain_off[] = {
1220 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
1221 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
1222 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
1223 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
1224 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
1225 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
1226 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
1227 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
1228 0x007e0403
1229 };
1230 u8 i;
1231
1232 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1233 return;
1234
1235 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1236
1237 if (coex_dm->cur_wl_rx_low_gain_en) {
1238 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1239 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]);
1240
1241
1242 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
1243 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
1244 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
1245 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
1246 } else {
1247 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1248 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
1249
1250
1251 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
1252 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
1253 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
1254 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
1255 }
1256 }
1257
1258 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
1259 {0x0086,
1260 RTW_PWR_CUT_ALL_MSK,
1261 RTW_PWR_INTF_SDIO_MSK,
1262 RTW_PWR_ADDR_SDIO,
1263 RTW_PWR_CMD_WRITE, BIT(0), 0},
1264 {0x0086,
1265 RTW_PWR_CUT_ALL_MSK,
1266 RTW_PWR_INTF_SDIO_MSK,
1267 RTW_PWR_ADDR_SDIO,
1268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1269 {0x004A,
1270 RTW_PWR_CUT_ALL_MSK,
1271 RTW_PWR_INTF_USB_MSK,
1272 RTW_PWR_ADDR_MAC,
1273 RTW_PWR_CMD_WRITE, BIT(0), 0},
1274 {0x0005,
1275 RTW_PWR_CUT_ALL_MSK,
1276 RTW_PWR_INTF_ALL_MSK,
1277 RTW_PWR_ADDR_MAC,
1278 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1279 {0x0300,
1280 RTW_PWR_CUT_ALL_MSK,
1281 RTW_PWR_INTF_PCI_MSK,
1282 RTW_PWR_ADDR_MAC,
1283 RTW_PWR_CMD_WRITE, 0xFF, 0},
1284 {0x0301,
1285 RTW_PWR_CUT_ALL_MSK,
1286 RTW_PWR_INTF_PCI_MSK,
1287 RTW_PWR_ADDR_MAC,
1288 RTW_PWR_CMD_WRITE, 0xFF, 0},
1289 {0xFFFF,
1290 RTW_PWR_CUT_ALL_MSK,
1291 RTW_PWR_INTF_ALL_MSK,
1292 0,
1293 RTW_PWR_CMD_END, 0, 0},
1294 };
1295
1296 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = {
1297 {0x0012,
1298 RTW_PWR_CUT_ALL_MSK,
1299 RTW_PWR_INTF_ALL_MSK,
1300 RTW_PWR_ADDR_MAC,
1301 RTW_PWR_CMD_WRITE, BIT(1), 0},
1302 {0x0012,
1303 RTW_PWR_CUT_ALL_MSK,
1304 RTW_PWR_INTF_ALL_MSK,
1305 RTW_PWR_ADDR_MAC,
1306 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1307 {0x0020,
1308 RTW_PWR_CUT_ALL_MSK,
1309 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1310 RTW_PWR_ADDR_MAC,
1311 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1312 {0x0001,
1313 RTW_PWR_CUT_ALL_MSK,
1314 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1315 RTW_PWR_ADDR_MAC,
1316 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1317 {0x0000,
1318 RTW_PWR_CUT_ALL_MSK,
1319 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1320 RTW_PWR_ADDR_MAC,
1321 RTW_PWR_CMD_WRITE, BIT(5), 0},
1322 {0x0005,
1323 RTW_PWR_CUT_ALL_MSK,
1324 RTW_PWR_INTF_ALL_MSK,
1325 RTW_PWR_ADDR_MAC,
1326 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1327 {0x0075,
1328 RTW_PWR_CUT_ALL_MSK,
1329 RTW_PWR_INTF_PCI_MSK,
1330 RTW_PWR_ADDR_MAC,
1331 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1332 {0x0006,
1333 RTW_PWR_CUT_ALL_MSK,
1334 RTW_PWR_INTF_ALL_MSK,
1335 RTW_PWR_ADDR_MAC,
1336 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1337 {0x0075,
1338 RTW_PWR_CUT_ALL_MSK,
1339 RTW_PWR_INTF_PCI_MSK,
1340 RTW_PWR_ADDR_MAC,
1341 RTW_PWR_CMD_WRITE, BIT(0), 0},
1342 {0xFF1A,
1343 RTW_PWR_CUT_ALL_MSK,
1344 RTW_PWR_INTF_USB_MSK,
1345 RTW_PWR_ADDR_MAC,
1346 RTW_PWR_CMD_WRITE, 0xFF, 0},
1347 {0x0006,
1348 RTW_PWR_CUT_ALL_MSK,
1349 RTW_PWR_INTF_ALL_MSK,
1350 RTW_PWR_ADDR_MAC,
1351 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1352 {0x0005,
1353 RTW_PWR_CUT_ALL_MSK,
1354 RTW_PWR_INTF_ALL_MSK,
1355 RTW_PWR_ADDR_MAC,
1356 RTW_PWR_CMD_WRITE, BIT(7), 0},
1357 {0x0005,
1358 RTW_PWR_CUT_ALL_MSK,
1359 RTW_PWR_INTF_ALL_MSK,
1360 RTW_PWR_ADDR_MAC,
1361 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1362 {0x10C3,
1363 RTW_PWR_CUT_ALL_MSK,
1364 RTW_PWR_INTF_USB_MSK,
1365 RTW_PWR_ADDR_MAC,
1366 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1367 {0x0005,
1368 RTW_PWR_CUT_ALL_MSK,
1369 RTW_PWR_INTF_ALL_MSK,
1370 RTW_PWR_ADDR_MAC,
1371 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1372 {0x0005,
1373 RTW_PWR_CUT_ALL_MSK,
1374 RTW_PWR_INTF_ALL_MSK,
1375 RTW_PWR_ADDR_MAC,
1376 RTW_PWR_CMD_POLLING, BIT(0), 0},
1377 {0x0020,
1378 RTW_PWR_CUT_ALL_MSK,
1379 RTW_PWR_INTF_ALL_MSK,
1380 RTW_PWR_ADDR_MAC,
1381 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1382 {0x10A8,
1383 RTW_PWR_CUT_C_MSK,
1384 RTW_PWR_INTF_ALL_MSK,
1385 RTW_PWR_ADDR_MAC,
1386 RTW_PWR_CMD_WRITE, 0xFF, 0},
1387 {0x10A9,
1388 RTW_PWR_CUT_C_MSK,
1389 RTW_PWR_INTF_ALL_MSK,
1390 RTW_PWR_ADDR_MAC,
1391 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1392 {0x10AA,
1393 RTW_PWR_CUT_C_MSK,
1394 RTW_PWR_INTF_ALL_MSK,
1395 RTW_PWR_ADDR_MAC,
1396 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1397 {0x0068,
1398 RTW_PWR_CUT_C_MSK,
1399 RTW_PWR_INTF_SDIO_MSK,
1400 RTW_PWR_ADDR_MAC,
1401 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1402 {0x0029,
1403 RTW_PWR_CUT_ALL_MSK,
1404 RTW_PWR_INTF_ALL_MSK,
1405 RTW_PWR_ADDR_MAC,
1406 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1407 {0x0024,
1408 RTW_PWR_CUT_ALL_MSK,
1409 RTW_PWR_INTF_ALL_MSK,
1410 RTW_PWR_ADDR_MAC,
1411 RTW_PWR_CMD_WRITE, BIT(2), 0},
1412 {0x0074,
1413 RTW_PWR_CUT_ALL_MSK,
1414 RTW_PWR_INTF_PCI_MSK,
1415 RTW_PWR_ADDR_MAC,
1416 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1417 {0x00AF,
1418 RTW_PWR_CUT_ALL_MSK,
1419 RTW_PWR_INTF_ALL_MSK,
1420 RTW_PWR_ADDR_MAC,
1421 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1422 {0xFFFF,
1423 RTW_PWR_CUT_ALL_MSK,
1424 RTW_PWR_INTF_ALL_MSK,
1425 0,
1426 RTW_PWR_CMD_END, 0, 0},
1427 };
1428
1429 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = {
1430 {0x0003,
1431 RTW_PWR_CUT_ALL_MSK,
1432 RTW_PWR_INTF_SDIO_MSK,
1433 RTW_PWR_ADDR_MAC,
1434 RTW_PWR_CMD_WRITE, BIT(2), 0},
1435 {0x0093,
1436 RTW_PWR_CUT_ALL_MSK,
1437 RTW_PWR_INTF_ALL_MSK,
1438 RTW_PWR_ADDR_MAC,
1439 RTW_PWR_CMD_WRITE, BIT(3), 0},
1440 {0x001F,
1441 RTW_PWR_CUT_ALL_MSK,
1442 RTW_PWR_INTF_ALL_MSK,
1443 RTW_PWR_ADDR_MAC,
1444 RTW_PWR_CMD_WRITE, 0xFF, 0},
1445 {0x00EF,
1446 RTW_PWR_CUT_ALL_MSK,
1447 RTW_PWR_INTF_ALL_MSK,
1448 RTW_PWR_ADDR_MAC,
1449 RTW_PWR_CMD_WRITE, 0xFF, 0},
1450 {0xFF1A,
1451 RTW_PWR_CUT_ALL_MSK,
1452 RTW_PWR_INTF_USB_MSK,
1453 RTW_PWR_ADDR_MAC,
1454 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1455 {0x0049,
1456 RTW_PWR_CUT_ALL_MSK,
1457 RTW_PWR_INTF_ALL_MSK,
1458 RTW_PWR_ADDR_MAC,
1459 RTW_PWR_CMD_WRITE, BIT(1), 0},
1460 {0x0006,
1461 RTW_PWR_CUT_ALL_MSK,
1462 RTW_PWR_INTF_ALL_MSK,
1463 RTW_PWR_ADDR_MAC,
1464 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1465 {0x0002,
1466 RTW_PWR_CUT_ALL_MSK,
1467 RTW_PWR_INTF_ALL_MSK,
1468 RTW_PWR_ADDR_MAC,
1469 RTW_PWR_CMD_WRITE, BIT(1), 0},
1470 {0x10C3,
1471 RTW_PWR_CUT_ALL_MSK,
1472 RTW_PWR_INTF_USB_MSK,
1473 RTW_PWR_ADDR_MAC,
1474 RTW_PWR_CMD_WRITE, BIT(0), 0},
1475 {0x0005,
1476 RTW_PWR_CUT_ALL_MSK,
1477 RTW_PWR_INTF_ALL_MSK,
1478 RTW_PWR_ADDR_MAC,
1479 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1480 {0x0005,
1481 RTW_PWR_CUT_ALL_MSK,
1482 RTW_PWR_INTF_ALL_MSK,
1483 RTW_PWR_ADDR_MAC,
1484 RTW_PWR_CMD_POLLING, BIT(1), 0},
1485 {0x0020,
1486 RTW_PWR_CUT_ALL_MSK,
1487 RTW_PWR_INTF_ALL_MSK,
1488 RTW_PWR_ADDR_MAC,
1489 RTW_PWR_CMD_WRITE, BIT(3), 0},
1490 {0x0000,
1491 RTW_PWR_CUT_ALL_MSK,
1492 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1493 RTW_PWR_ADDR_MAC,
1494 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1495 {0xFFFF,
1496 RTW_PWR_CUT_ALL_MSK,
1497 RTW_PWR_INTF_ALL_MSK,
1498 0,
1499 RTW_PWR_CMD_END, 0, 0},
1500 };
1501
1502 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = {
1503 {0x0005,
1504 RTW_PWR_CUT_ALL_MSK,
1505 RTW_PWR_INTF_SDIO_MSK,
1506 RTW_PWR_ADDR_MAC,
1507 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1508 {0x0007,
1509 RTW_PWR_CUT_ALL_MSK,
1510 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1511 RTW_PWR_ADDR_MAC,
1512 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1513 {0x0067,
1514 RTW_PWR_CUT_ALL_MSK,
1515 RTW_PWR_INTF_ALL_MSK,
1516 RTW_PWR_ADDR_MAC,
1517 RTW_PWR_CMD_WRITE, BIT(5), 0},
1518 {0x0005,
1519 RTW_PWR_CUT_ALL_MSK,
1520 RTW_PWR_INTF_PCI_MSK,
1521 RTW_PWR_ADDR_MAC,
1522 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1523 {0x004A,
1524 RTW_PWR_CUT_ALL_MSK,
1525 RTW_PWR_INTF_USB_MSK,
1526 RTW_PWR_ADDR_MAC,
1527 RTW_PWR_CMD_WRITE, BIT(0), 0},
1528 {0x0067,
1529 RTW_PWR_CUT_ALL_MSK,
1530 RTW_PWR_INTF_SDIO_MSK,
1531 RTW_PWR_ADDR_MAC,
1532 RTW_PWR_CMD_WRITE, BIT(5), 0},
1533 {0x0067,
1534 RTW_PWR_CUT_ALL_MSK,
1535 RTW_PWR_INTF_SDIO_MSK,
1536 RTW_PWR_ADDR_MAC,
1537 RTW_PWR_CMD_WRITE, BIT(4), 0},
1538 {0x004F,
1539 RTW_PWR_CUT_ALL_MSK,
1540 RTW_PWR_INTF_SDIO_MSK,
1541 RTW_PWR_ADDR_MAC,
1542 RTW_PWR_CMD_WRITE, BIT(0), 0},
1543 {0x0067,
1544 RTW_PWR_CUT_ALL_MSK,
1545 RTW_PWR_INTF_SDIO_MSK,
1546 RTW_PWR_ADDR_MAC,
1547 RTW_PWR_CMD_WRITE, BIT(1), 0},
1548 {0x0046,
1549 RTW_PWR_CUT_ALL_MSK,
1550 RTW_PWR_INTF_SDIO_MSK,
1551 RTW_PWR_ADDR_MAC,
1552 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1553 {0x0067,
1554 RTW_PWR_CUT_ALL_MSK,
1555 RTW_PWR_INTF_SDIO_MSK,
1556 RTW_PWR_ADDR_MAC,
1557 RTW_PWR_CMD_WRITE, BIT(2), 0},
1558 {0x0046,
1559 RTW_PWR_CUT_ALL_MSK,
1560 RTW_PWR_INTF_SDIO_MSK,
1561 RTW_PWR_ADDR_MAC,
1562 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1563 {0x0062,
1564 RTW_PWR_CUT_ALL_MSK,
1565 RTW_PWR_INTF_SDIO_MSK,
1566 RTW_PWR_ADDR_MAC,
1567 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1568 {0x0081,
1569 RTW_PWR_CUT_ALL_MSK,
1570 RTW_PWR_INTF_ALL_MSK,
1571 RTW_PWR_ADDR_MAC,
1572 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1573 {0x0005,
1574 RTW_PWR_CUT_ALL_MSK,
1575 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1576 RTW_PWR_ADDR_MAC,
1577 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1578 {0x0086,
1579 RTW_PWR_CUT_ALL_MSK,
1580 RTW_PWR_INTF_SDIO_MSK,
1581 RTW_PWR_ADDR_SDIO,
1582 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1583 {0x0086,
1584 RTW_PWR_CUT_ALL_MSK,
1585 RTW_PWR_INTF_SDIO_MSK,
1586 RTW_PWR_ADDR_SDIO,
1587 RTW_PWR_CMD_POLLING, BIT(1), 0},
1588 {0x0090,
1589 RTW_PWR_CUT_ALL_MSK,
1590 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1591 RTW_PWR_ADDR_MAC,
1592 RTW_PWR_CMD_WRITE, BIT(1), 0},
1593 {0x0044,
1594 RTW_PWR_CUT_ALL_MSK,
1595 RTW_PWR_INTF_SDIO_MSK,
1596 RTW_PWR_ADDR_SDIO,
1597 RTW_PWR_CMD_WRITE, 0xFF, 0},
1598 {0x0040,
1599 RTW_PWR_CUT_ALL_MSK,
1600 RTW_PWR_INTF_SDIO_MSK,
1601 RTW_PWR_ADDR_SDIO,
1602 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1603 {0x0041,
1604 RTW_PWR_CUT_ALL_MSK,
1605 RTW_PWR_INTF_SDIO_MSK,
1606 RTW_PWR_ADDR_SDIO,
1607 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1608 {0x0042,
1609 RTW_PWR_CUT_ALL_MSK,
1610 RTW_PWR_INTF_SDIO_MSK,
1611 RTW_PWR_ADDR_SDIO,
1612 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1613 {0xFFFF,
1614 RTW_PWR_CUT_ALL_MSK,
1615 RTW_PWR_INTF_ALL_MSK,
1616 0,
1617 RTW_PWR_CMD_END, 0, 0},
1618 };
1619
1620 static struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = {
1621 trans_carddis_to_cardemu_8822b,
1622 trans_cardemu_to_act_8822b,
1623 NULL
1624 };
1625
1626 static struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = {
1627 trans_act_to_cardemu_8822b,
1628 trans_cardemu_to_carddis_8822b,
1629 NULL
1630 };
1631
1632 static struct rtw_intf_phy_para usb2_param_8822b[] = {
1633 {0xFFFF, 0x00,
1634 RTW_IP_SEL_PHY,
1635 RTW_INTF_PHY_CUT_ALL,
1636 RTW_INTF_PHY_PLATFORM_ALL},
1637 };
1638
1639 static struct rtw_intf_phy_para usb3_param_8822b[] = {
1640 {0x0001, 0xA841,
1641 RTW_IP_SEL_PHY,
1642 RTW_INTF_PHY_CUT_D,
1643 RTW_INTF_PHY_PLATFORM_ALL},
1644 {0xFFFF, 0x0000,
1645 RTW_IP_SEL_PHY,
1646 RTW_INTF_PHY_CUT_ALL,
1647 RTW_INTF_PHY_PLATFORM_ALL},
1648 };
1649
1650 static struct rtw_intf_phy_para pcie_gen1_param_8822b[] = {
1651 {0x0001, 0xA841,
1652 RTW_IP_SEL_PHY,
1653 RTW_INTF_PHY_CUT_C,
1654 RTW_INTF_PHY_PLATFORM_ALL},
1655 {0x0002, 0x60C6,
1656 RTW_IP_SEL_PHY,
1657 RTW_INTF_PHY_CUT_C,
1658 RTW_INTF_PHY_PLATFORM_ALL},
1659 {0x0008, 0x3596,
1660 RTW_IP_SEL_PHY,
1661 RTW_INTF_PHY_CUT_C,
1662 RTW_INTF_PHY_PLATFORM_ALL},
1663 {0x0009, 0x321C,
1664 RTW_IP_SEL_PHY,
1665 RTW_INTF_PHY_CUT_C,
1666 RTW_INTF_PHY_PLATFORM_ALL},
1667 {0x000A, 0x9623,
1668 RTW_IP_SEL_PHY,
1669 RTW_INTF_PHY_CUT_C,
1670 RTW_INTF_PHY_PLATFORM_ALL},
1671 {0x0020, 0x94FF,
1672 RTW_IP_SEL_PHY,
1673 RTW_INTF_PHY_CUT_C,
1674 RTW_INTF_PHY_PLATFORM_ALL},
1675 {0x0021, 0xFFCF,
1676 RTW_IP_SEL_PHY,
1677 RTW_INTF_PHY_CUT_C,
1678 RTW_INTF_PHY_PLATFORM_ALL},
1679 {0x0026, 0xC006,
1680 RTW_IP_SEL_PHY,
1681 RTW_INTF_PHY_CUT_C,
1682 RTW_INTF_PHY_PLATFORM_ALL},
1683 {0x0029, 0xFF0E,
1684 RTW_IP_SEL_PHY,
1685 RTW_INTF_PHY_CUT_C,
1686 RTW_INTF_PHY_PLATFORM_ALL},
1687 {0x002A, 0x1840,
1688 RTW_IP_SEL_PHY,
1689 RTW_INTF_PHY_CUT_C,
1690 RTW_INTF_PHY_PLATFORM_ALL},
1691 {0xFFFF, 0x0000,
1692 RTW_IP_SEL_PHY,
1693 RTW_INTF_PHY_CUT_ALL,
1694 RTW_INTF_PHY_PLATFORM_ALL},
1695 };
1696
1697 static struct rtw_intf_phy_para pcie_gen2_param_8822b[] = {
1698 {0x0001, 0xA841,
1699 RTW_IP_SEL_PHY,
1700 RTW_INTF_PHY_CUT_C,
1701 RTW_INTF_PHY_PLATFORM_ALL},
1702 {0x0002, 0x60C6,
1703 RTW_IP_SEL_PHY,
1704 RTW_INTF_PHY_CUT_C,
1705 RTW_INTF_PHY_PLATFORM_ALL},
1706 {0x0008, 0x3597,
1707 RTW_IP_SEL_PHY,
1708 RTW_INTF_PHY_CUT_C,
1709 RTW_INTF_PHY_PLATFORM_ALL},
1710 {0x0009, 0x321C,
1711 RTW_IP_SEL_PHY,
1712 RTW_INTF_PHY_CUT_C,
1713 RTW_INTF_PHY_PLATFORM_ALL},
1714 {0x000A, 0x9623,
1715 RTW_IP_SEL_PHY,
1716 RTW_INTF_PHY_CUT_C,
1717 RTW_INTF_PHY_PLATFORM_ALL},
1718 {0x0020, 0x94FF,
1719 RTW_IP_SEL_PHY,
1720 RTW_INTF_PHY_CUT_C,
1721 RTW_INTF_PHY_PLATFORM_ALL},
1722 {0x0021, 0xFFCF,
1723 RTW_IP_SEL_PHY,
1724 RTW_INTF_PHY_CUT_C,
1725 RTW_INTF_PHY_PLATFORM_ALL},
1726 {0x0026, 0xC006,
1727 RTW_IP_SEL_PHY,
1728 RTW_INTF_PHY_CUT_C,
1729 RTW_INTF_PHY_PLATFORM_ALL},
1730 {0x0029, 0xFF0E,
1731 RTW_IP_SEL_PHY,
1732 RTW_INTF_PHY_CUT_C,
1733 RTW_INTF_PHY_PLATFORM_ALL},
1734 {0x002A, 0x3040,
1735 RTW_IP_SEL_PHY,
1736 RTW_INTF_PHY_CUT_C,
1737 RTW_INTF_PHY_PLATFORM_ALL},
1738 {0xFFFF, 0x0000,
1739 RTW_IP_SEL_PHY,
1740 RTW_INTF_PHY_CUT_ALL,
1741 RTW_INTF_PHY_PLATFORM_ALL},
1742 };
1743
1744 static struct rtw_intf_phy_para_table phy_para_table_8822b = {
1745 .usb2_para = usb2_param_8822b,
1746 .usb3_para = usb3_param_8822b,
1747 .gen1_para = pcie_gen1_param_8822b,
1748 .gen2_para = pcie_gen2_param_8822b,
1749 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b),
1750 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b),
1751 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b),
1752 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b),
1753 };
1754
1755 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = {
1756 [2] = RTW_DEF_RFE(8822b, 2, 2),
1757 [5] = RTW_DEF_RFE(8822b, 5, 5),
1758 };
1759
1760 static struct rtw_hw_reg rtw8822b_dig[] = {
1761 [0] = { .addr = 0xc50, .mask = 0x7f },
1762 [1] = { .addr = 0xe50, .mask = 0x7f },
1763 };
1764
1765 static struct rtw_page_table page_table_8822b[] = {
1766 {64, 64, 64, 64, 1},
1767 {64, 64, 64, 64, 1},
1768 {64, 64, 0, 0, 1},
1769 {64, 64, 64, 0, 1},
1770 {64, 64, 64, 64, 1},
1771 };
1772
1773 static struct rtw_rqpn rqpn_table_8822b[] = {
1774 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1775 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1776 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1777 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1778 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1779 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1780 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1781 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1782 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1783 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1784 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1785 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1786 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1787 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1788 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1789 };
1790
1791 static struct rtw_chip_ops rtw8822b_ops = {
1792 .phy_set_param = rtw8822b_phy_set_param,
1793 .read_efuse = rtw8822b_read_efuse,
1794 .query_rx_desc = rtw8822b_query_rx_desc,
1795 .set_channel = rtw8822b_set_channel,
1796 .mac_init = rtw8822b_mac_init,
1797 .read_rf = rtw_phy_read_rf,
1798 .write_rf = rtw_phy_write_rf_reg_sipi,
1799 .set_tx_power_index = rtw8822b_set_tx_power_index,
1800 .set_antenna = rtw8822b_set_antenna,
1801 .cfg_ldo25 = rtw8822b_cfg_ldo25,
1802 .false_alarm_statistics = rtw8822b_false_alarm_statistics,
1803 .phy_calibration = rtw8822b_phy_calibration,
1804
1805 .coex_set_init = rtw8822b_coex_cfg_init,
1806 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch,
1807 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix,
1808 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug,
1809 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type,
1810 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power,
1811 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain,
1812 };
1813
1814
1815 static const struct coex_table_para table_sant_8822b[] = {
1816 {0xffffffff, 0xffffffff},
1817 {0x55555555, 0x55555555},
1818 {0x66555555, 0x66555555},
1819 {0xaaaaaaaa, 0xaaaaaaaa},
1820 {0x5a5a5a5a, 0x5a5a5a5a},
1821 {0xfafafafa, 0xfafafafa},
1822 {0x6a5a6a5a, 0xaaaaaaaa},
1823 {0x6a5a56aa, 0x6a5a56aa},
1824 {0x6a5a5a5a, 0x6a5a5a5a},
1825 {0x66555555, 0x5a5a5a5a},
1826 {0x66555555, 0x6a5a5a5a},
1827 {0x66555555, 0xfafafafa},
1828 {0x66555555, 0x6a5a5aaa},
1829 {0x66555555, 0x5aaa5aaa},
1830 {0x66555555, 0xaaaa5aaa},
1831 {0x66555555, 0xaaaaaaaa},
1832 {0xffff55ff, 0xfafafafa},
1833 {0xffff55ff, 0x6afa5afa},
1834 {0xaaffffaa, 0xfafafafa},
1835 {0xaa5555aa, 0x5a5a5a5a},
1836 {0xaa5555aa, 0x6a5a5a5a},
1837 {0xaa5555aa, 0xaaaaaaaa},
1838 {0xffffffff, 0x5a5a5a5a},
1839 {0xffffffff, 0x6a5a5a5a},
1840 {0xffffffff, 0x55555555},
1841 {0xffffffff, 0x6a5a5aaa},
1842 {0x55555555, 0x5a5a5a5a},
1843 {0x55555555, 0xaaaaaaaa},
1844 {0x55555555, 0x6a5a6a5a},
1845 {0x66556655, 0x66556655}
1846 };
1847
1848
1849 static const struct coex_table_para table_nsant_8822b[] = {
1850 {0xffffffff, 0xffffffff},
1851 {0x55555555, 0x55555555},
1852 {0x66555555, 0x66555555},
1853 {0xaaaaaaaa, 0xaaaaaaaa},
1854 {0x5a5a5a5a, 0x5a5a5a5a},
1855 {0xfafafafa, 0xfafafafa},
1856 {0x5afa5afa, 0x5afa5afa},
1857 {0x55555555, 0xfafafafa},
1858 {0x66555555, 0xfafafafa},
1859 {0x66555555, 0x5a5a5a5a},
1860 {0x66555555, 0x6a5a5a5a},
1861 {0x66555555, 0xaaaaaaaa},
1862 {0xffff55ff, 0xfafafafa},
1863 {0xffff55ff, 0x5afa5afa},
1864 {0xffff55ff, 0xaaaaaaaa},
1865 {0xaaffffaa, 0xfafafafa},
1866 {0xaaffffaa, 0x5afa5afa},
1867 {0xaaffffaa, 0xaaaaaaaa},
1868 {0xffffffff, 0xfafafafa},
1869 {0xffffffff, 0x5afa5afa},
1870 {0xffffffff, 0xaaaaaaaa},
1871 {0x55ff55ff, 0x5afa5afa},
1872 {0x55ff55ff, 0xaaaaaaaa},
1873 {0x55ff55ff, 0x55ff55ff}
1874 };
1875
1876
1877 static const struct coex_tdma_para tdma_sant_8822b[] = {
1878 { {0x00, 0x00, 0x00, 0x00, 0x00} },
1879 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1880 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1881 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1882 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1883 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1884 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1885 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1886 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1887 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1888 { {0x61, 0x10, 0x03, 0x11, 0x10} },
1889 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1890 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1891 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1892 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1893 { {0x51, 0x08, 0x07, 0x10, 0x54} },
1894 { {0x51, 0x45, 0x03, 0x10, 0x10} },
1895 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1896 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1897 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1898 { {0x51, 0x10, 0x03, 0x10, 0x50} },
1899 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1900 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1901 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1902 { {0x65, 0x10, 0x03, 0x11, 0x11} },
1903 { {0x51, 0x10, 0x03, 0x10, 0x51} },
1904 { {0x51, 0x08, 0x03, 0x10, 0x50} }
1905 };
1906
1907
1908 static const struct coex_tdma_para tdma_nsant_8822b[] = {
1909 { {0x00, 0x00, 0x00, 0x00, 0x00} },
1910 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1911 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1912 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1913 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1914 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1915 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1916 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1917 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1918 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1919 { {0x61, 0x10, 0x03, 0x11, 0x10} },
1920 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1921 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1922 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1923 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1924 { {0x51, 0x08, 0x07, 0x10, 0x54} },
1925 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1926 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1927 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1928 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1929 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1930 };
1931
1932
1933 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30};
1934 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30};
1935 static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} };
1936
1937
1938 static const struct coex_rf_para rf_para_tx_8822b[] = {
1939 {0, 0, false, 7},
1940 {0, 16, false, 7},
1941 {4, 0, true, 1},
1942 {3, 6, true, 1},
1943 {2, 9, true, 1},
1944 {1, 13, true, 1}
1945 };
1946
1947 static const struct coex_rf_para rf_para_rx_8822b[] = {
1948 {0, 0, false, 7},
1949 {0, 16, false, 7},
1950 {4, 0, true, 1},
1951 {3, 6, true, 1},
1952 {2, 9, true, 1},
1953 {1, 13, true, 1}
1954 };
1955
1956 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b));
1957
1958 struct rtw_chip_info rtw8822b_hw_spec = {
1959 .ops = &rtw8822b_ops,
1960 .id = RTW_CHIP_TYPE_8822B,
1961 .fw_name = "rtw88/rtw8822b_fw.bin",
1962 .tx_pkt_desc_sz = 48,
1963 .tx_buf_desc_sz = 16,
1964 .rx_pkt_desc_sz = 24,
1965 .rx_buf_desc_sz = 8,
1966 .phy_efuse_size = 1024,
1967 .log_efuse_size = 768,
1968 .ptct_efuse_size = 96,
1969 .txff_size = 262144,
1970 .rxff_size = 24576,
1971 .txgi_factor = 1,
1972 .is_pwr_by_rate_dec = true,
1973 .max_power_index = 0x3f,
1974 .csi_buf_pg_num = 0,
1975 .band = RTW_BAND_2G | RTW_BAND_5G,
1976 .page_size = 128,
1977 .dig_min = 0x1c,
1978 .ht_supported = true,
1979 .vht_supported = true,
1980 .sys_func_en = 0xDC,
1981 .pwr_on_seq = card_enable_flow_8822b,
1982 .pwr_off_seq = card_disable_flow_8822b,
1983 .page_table = page_table_8822b,
1984 .rqpn_table = rqpn_table_8822b,
1985 .intf_table = &phy_para_table_8822b,
1986 .dig = rtw8822b_dig,
1987 .rf_base_addr = {0x2800, 0x2c00},
1988 .rf_sipi_addr = {0xc90, 0xe90},
1989 .mac_tbl = &rtw8822b_mac_tbl,
1990 .agc_tbl = &rtw8822b_agc_tbl,
1991 .bb_tbl = &rtw8822b_bb_tbl,
1992 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
1993 .rfe_defs = rtw8822b_rfe_defs,
1994 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
1995
1996 .coex_para_ver = 0x19062706,
1997 .bt_desired_ver = 0x6,
1998 .scbd_support = true,
1999 .new_scbd10_def = false,
2000 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2001 .bt_rssi_type = COEX_BTRSSI_RATIO,
2002 .ant_isolation = 15,
2003 .rssi_tolerance = 2,
2004 .wl_rssi_step = wl_rssi_step_8822b,
2005 .bt_rssi_step = bt_rssi_step_8822b,
2006 .table_sant_num = ARRAY_SIZE(table_sant_8822b),
2007 .table_sant = table_sant_8822b,
2008 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b),
2009 .table_nsant = table_nsant_8822b,
2010 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b),
2011 .tdma_sant = tdma_sant_8822b,
2012 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b),
2013 .tdma_nsant = tdma_nsant_8822b,
2014 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b),
2015 .wl_rf_para_tx = rf_para_tx_8822b,
2016 .wl_rf_para_rx = rf_para_rx_8822b,
2017 .bt_afh_span_bw20 = 0x24,
2018 .bt_afh_span_bw40 = 0x36,
2019 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b),
2020 .afh_5g = afh_5g_8822b,
2021 };
2022 EXPORT_SYMBOL(rtw8822b_hw_spec);
2023
2024 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin");