This source file includes following definitions.
- b43_nphy_ipa
- b43_nphy_get_rx_core_state
- b43_nphy_force_rf_sequence
- b43_nphy_rf_ctl_override_rev19
- b43_nphy_rf_ctl_override_rev7
- b43_nphy_rf_ctl_override_one_to_many
- b43_nphy_rf_ctl_override
- b43_nphy_rf_ctl_intc_override_rev7
- b43_nphy_rf_ctl_intc_override
- b43_nphy_write_clip_detection
- b43_nphy_read_clip_detection
- b43_nphy_classifier
- b43_nphy_reset_cca
- b43_nphy_stay_in_carrier_search
- b43_nphy_read_lpf_ctl
- b43_nphy_adjust_lna_gain_table
- b43_nphy_set_rf_sequence
- b43_radio_2057_chantab_upload
- b43_radio_2057_setup
- b43_radio_2057_rcal
- b43_radio_2057_rccal
- b43_radio_2057_init_pre
- b43_radio_2057_init_post
- b43_radio_2057_init
- b43_chantab_radio_2056_upload
- b43_radio_2056_setup
- b43_radio_2056_rcal
- b43_radio_init2056_pre
- b43_radio_init2056_post
- b43_radio_init2056
- b43_chantab_radio_upload
- b43_radio_2055_setup
- b43_radio_init2055_pre
- b43_radio_init2055_post
- b43_radio_init2055
- b43_nphy_load_samples
- b43_nphy_gen_load_samples
- b43_nphy_run_samples
- b43_nphy_scale_offset_rssi
- b43_nphy_rssi_select_rev19
- b43_nphy_rev3_rssi_select
- b43_nphy_rev2_rssi_select
- b43_nphy_rssi_select
- b43_nphy_set_rssi_2055_vcm
- b43_nphy_poll_rssi
- b43_nphy_rev3_rssi_cal
- b43_nphy_rev2_rssi_cal
- b43_nphy_rssi_cal
- b43_nphy_gain_ctl_workarounds_rev19
- b43_nphy_gain_ctl_workarounds_rev7
- b43_nphy_gain_ctl_workarounds_rev3
- b43_nphy_gain_ctl_workarounds_rev1_2
- b43_nphy_gain_ctl_workarounds
- b43_nphy_workarounds_rev7plus
- b43_nphy_workarounds_rev3plus
- b43_nphy_workarounds_rev1_2
- b43_nphy_workarounds
- b43_nphy_tx_tone
- b43_nphy_update_txrx_chain
- b43_nphy_stop_playback
- b43_nphy_iq_cal_gain_params
- b43_nphy_tx_power_ctrl
- b43_nphy_tx_power_fix
- b43_nphy_ipa_internal_tssi_setup
- b43_nphy_tx_power_ctl_idle_tssi
- b43_nphy_tx_prepare_adjusted_power_table
- b43_nphy_tx_power_ctl_setup
- b43_nphy_tx_gain_table_upload
- b43_nphy_pa_override
- b43_nphy_tx_lpf_bw
- b43_nphy_rx_iq_est
- b43_nphy_rx_iq_coeffs
- b43_nphy_rx_cal_phy_cleanup
- b43_nphy_rx_cal_phy_setup
- b43_nphy_calc_rx_iq_comp
- b43_nphy_tx_iq_workaround
- b43_nphy_spur_workaround
- b43_nphy_tx_pwr_ctrl_coef_setup
- b43_nphy_restore_rssi_cal
- b43_nphy_tx_cal_radio_setup_rev19
- b43_nphy_tx_cal_radio_setup_rev7
- b43_nphy_tx_cal_radio_setup
- b43_nphy_update_tx_cal_ladder
- b43_nphy_pa_set_tx_dig_filter
- b43_nphy_ext_pa_set_tx_dig_filters
- b43_nphy_int_pa_set_tx_dig_filters
- b43_nphy_get_tx_gains
- b43_nphy_tx_cal_phy_cleanup
- b43_nphy_tx_cal_phy_setup
- b43_nphy_save_cal
- b43_nphy_restore_cal
- b43_nphy_cal_tx_iq_lo
- b43_nphy_reapply_tx_cal_coeffs
- b43_nphy_rev2_cal_rx_iq
- b43_nphy_rev3_cal_rx_iq
- b43_nphy_cal_rx_iq
- b43_nphy_set_rx_core_state
- b43_nphy_op_recalc_txpower
- b43_nphy_update_mimo_config
- b43_nphy_bphy_init
- b43_nphy_superswitch_init
- b43_phy_initn
- b43_chantab_phy_upload
- b43_nphy_pmu_spur_avoid
- b43_nphy_channel_setup
- b43_nphy_set_channel
- b43_nphy_op_allocate
- b43_nphy_op_prepare_structs
- b43_nphy_op_free
- b43_nphy_op_init
- check_phyreg
- b43_nphy_op_maskset
- b43_nphy_op_radio_read
- b43_nphy_op_radio_write
- b43_nphy_op_software_rfkill
- b43_nphy_op_switch_analog
- b43_nphy_op_switch_channel
- b43_nphy_op_get_default_chan
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13 #include <linux/cordic.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/types.h>
17
18 #include "b43.h"
19 #include "phy_n.h"
20 #include "tables_nphy.h"
21 #include "radio_2055.h"
22 #include "radio_2056.h"
23 #include "radio_2057.h"
24 #include "main.h"
25 #include "ppr.h"
26
27 struct nphy_txgains {
28 u16 tx_lpf[2];
29 u16 txgm[2];
30 u16 pga[2];
31 u16 pad[2];
32 u16 ipa[2];
33 };
34
35 struct nphy_iqcal_params {
36 u16 tx_lpf;
37 u16 txgm;
38 u16 pga;
39 u16 pad;
40 u16 ipa;
41 u16 cal_gain;
42 u16 ncorr[5];
43 };
44
45 struct nphy_iq_est {
46 s32 iq0_prod;
47 u32 i0_pwr;
48 u32 q0_pwr;
49 s32 iq1_prod;
50 u32 i1_pwr;
51 u32 q1_pwr;
52 };
53
54 enum b43_nphy_rf_sequence {
55 B43_RFSEQ_RX2TX,
56 B43_RFSEQ_TX2RX,
57 B43_RFSEQ_RESET2RX,
58 B43_RFSEQ_UPDATE_GAINH,
59 B43_RFSEQ_UPDATE_GAINL,
60 B43_RFSEQ_UPDATE_GAINU,
61 };
62
63 enum n_rf_ctl_over_cmd {
64 N_RF_CTL_OVER_CMD_RXRF_PU = 0,
65 N_RF_CTL_OVER_CMD_RX_PU = 1,
66 N_RF_CTL_OVER_CMD_TX_PU = 2,
67 N_RF_CTL_OVER_CMD_RX_GAIN = 3,
68 N_RF_CTL_OVER_CMD_TX_GAIN = 4,
69 };
70
71 enum n_intc_override {
72 N_INTC_OVERRIDE_OFF = 0,
73 N_INTC_OVERRIDE_TRSW = 1,
74 N_INTC_OVERRIDE_PA = 2,
75 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
76 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
77 };
78
79 enum n_rssi_type {
80 N_RSSI_W1 = 0,
81 N_RSSI_W2,
82 N_RSSI_NB,
83 N_RSSI_IQ,
84 N_RSSI_TSSI_2G,
85 N_RSSI_TSSI_5G,
86 N_RSSI_TBD,
87 };
88
89 enum n_rail_type {
90 N_RAIL_I = 0,
91 N_RAIL_Q = 1,
92 };
93
94 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
95 {
96 enum nl80211_band band = b43_current_band(dev->wl);
97 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) ||
98 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ));
99 }
100
101
102 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
103 {
104 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
105 B43_NPHY_RFSEQCA_RXEN_SHIFT;
106 }
107
108
109
110
111
112
113 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
114 enum b43_nphy_rf_sequence seq)
115 {
116 static const u16 trigger[] = {
117 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
118 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
119 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
120 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
121 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
122 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
123 };
124 int i;
125 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
126
127 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
128
129 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
130 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
131 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
132 for (i = 0; i < 200; i++) {
133 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
134 goto ok;
135 msleep(1);
136 }
137 b43err(dev->wl, "RF sequence status timeout\n");
138 ok:
139 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
140 }
141
142 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field,
143 u16 value, u8 core, bool off,
144 u8 override_id)
145 {
146
147 }
148
149
150 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
151 u16 value, u8 core, bool off,
152 u8 override)
153 {
154 struct b43_phy *phy = &dev->phy;
155 const struct nphy_rf_control_override_rev7 *e;
156 u16 en_addrs[3][2] = {
157 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
158 };
159 u16 en_addr;
160 u16 en_mask = field;
161 u16 val_addr;
162 u8 i;
163
164 if (phy->rev >= 19 || phy->rev < 3) {
165 B43_WARN_ON(1);
166 return;
167 }
168
169
170 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
171
172 for (i = 0; i < 2; i++) {
173 if (override >= ARRAY_SIZE(en_addrs)) {
174 b43err(dev->wl, "Invalid override value %d\n", override);
175 return;
176 }
177 en_addr = en_addrs[override][i];
178
179 if (e)
180 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
181
182 if (off) {
183 b43_phy_mask(dev, en_addr, ~en_mask);
184 if (e)
185 b43_phy_mask(dev, val_addr, ~e->val_mask);
186 } else {
187 if (!core || (core & (1 << i))) {
188 b43_phy_set(dev, en_addr, en_mask);
189 if (e)
190 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
191 }
192 }
193 }
194 }
195
196
197 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev,
198 enum n_rf_ctl_over_cmd cmd,
199 u16 value, u8 core, bool off)
200 {
201 struct b43_phy *phy = &dev->phy;
202 u16 tmp;
203
204 B43_WARN_ON(phy->rev < 7);
205
206 switch (cmd) {
207 case N_RF_CTL_OVER_CMD_RXRF_PU:
208 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1);
209 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1);
210 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1);
211 break;
212 case N_RF_CTL_OVER_CMD_RX_PU:
213 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1);
214 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
215 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1);
216 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2);
217 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1);
218 break;
219 case N_RF_CTL_OVER_CMD_TX_PU:
220 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0);
221 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
222 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2);
223 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1);
224 break;
225 case N_RF_CTL_OVER_CMD_RX_GAIN:
226 tmp = value & 0xFF;
227 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0);
228 tmp = value >> 8;
229 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0);
230 break;
231 case N_RF_CTL_OVER_CMD_TX_GAIN:
232 tmp = value & 0x7FFF;
233 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0);
234 tmp = value >> 14;
235 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0);
236 break;
237 }
238 }
239
240
241 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
242 u16 value, u8 core, bool off)
243 {
244 int i;
245 u8 index = fls(field);
246 u8 addr, en_addr, val_addr;
247
248 B43_WARN_ON(field & (~(1 << (index - 1))));
249
250 if (dev->phy.rev >= 3) {
251 const struct nphy_rf_control_override_rev3 *rf_ctrl;
252 for (i = 0; i < 2; i++) {
253 if (index == 0 || index == 16) {
254 b43err(dev->wl,
255 "Unsupported RF Ctrl Override call\n");
256 return;
257 }
258
259 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
260 en_addr = B43_PHY_N((i == 0) ?
261 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
262 val_addr = B43_PHY_N((i == 0) ?
263 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
264
265 if (off) {
266 b43_phy_mask(dev, en_addr, ~(field));
267 b43_phy_mask(dev, val_addr,
268 ~(rf_ctrl->val_mask));
269 } else {
270 if (core == 0 || ((1 << i) & core)) {
271 b43_phy_set(dev, en_addr, field);
272 b43_phy_maskset(dev, val_addr,
273 ~(rf_ctrl->val_mask),
274 (value << rf_ctrl->val_shift));
275 }
276 }
277 }
278 } else {
279 const struct nphy_rf_control_override_rev2 *rf_ctrl;
280 if (off) {
281 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
282 value = 0;
283 } else {
284 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
285 }
286
287 for (i = 0; i < 2; i++) {
288 if (index <= 1 || index == 16) {
289 b43err(dev->wl,
290 "Unsupported RF Ctrl Override call\n");
291 return;
292 }
293
294 if (index == 2 || index == 10 ||
295 (index >= 13 && index <= 15)) {
296 core = 1;
297 }
298
299 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
300 addr = B43_PHY_N((i == 0) ?
301 rf_ctrl->addr0 : rf_ctrl->addr1);
302
303 if ((1 << i) & core)
304 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
305 (value << rf_ctrl->shift));
306
307 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
308 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
309 B43_NPHY_RFCTL_CMD_START);
310 udelay(1);
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
312 }
313 }
314 }
315
316 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
317 enum n_intc_override intc_override,
318 u16 value, u8 core_sel)
319 {
320 u16 reg, tmp, tmp2, val;
321 int core;
322
323
324
325 for (core = 0; core < 2; core++) {
326 if ((core_sel == 1 && core != 0) ||
327 (core_sel == 2 && core != 1))
328 continue;
329
330 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
331
332 switch (intc_override) {
333 case N_INTC_OVERRIDE_OFF:
334 b43_phy_write(dev, reg, 0);
335 b43_phy_mask(dev, 0x2ff, ~0x2000);
336 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
337 break;
338 case N_INTC_OVERRIDE_TRSW:
339 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
340 b43_phy_set(dev, reg, 0x400);
341
342 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
343 b43_phy_set(dev, 0x2ff, 0x2000);
344 b43_phy_set(dev, 0x2ff, 0x0001);
345 break;
346 case N_INTC_OVERRIDE_PA:
347 tmp = 0x0030;
348 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
349 val = value << 5;
350 else
351 val = value << 4;
352 b43_phy_maskset(dev, reg, ~tmp, val);
353 b43_phy_set(dev, reg, 0x1000);
354 break;
355 case N_INTC_OVERRIDE_EXT_LNA_PU:
356 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
357 tmp = 0x0001;
358 tmp2 = 0x0004;
359 val = value;
360 } else {
361 tmp = 0x0004;
362 tmp2 = 0x0001;
363 val = value << 2;
364 }
365 b43_phy_maskset(dev, reg, ~tmp, val);
366 b43_phy_mask(dev, reg, ~tmp2);
367 break;
368 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
369 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
370 tmp = 0x0002;
371 tmp2 = 0x0008;
372 val = value << 1;
373 } else {
374 tmp = 0x0008;
375 tmp2 = 0x0002;
376 val = value << 3;
377 }
378 b43_phy_maskset(dev, reg, ~tmp, val);
379 b43_phy_mask(dev, reg, ~tmp2);
380 break;
381 }
382 }
383 }
384
385
386 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
387 enum n_intc_override intc_override,
388 u16 value, u8 core)
389 {
390 u8 i, j;
391 u16 reg, tmp, val;
392
393 if (dev->phy.rev >= 7) {
394 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
395 core);
396 return;
397 }
398
399 B43_WARN_ON(dev->phy.rev < 3);
400
401 for (i = 0; i < 2; i++) {
402 if ((core == 1 && i == 1) || (core == 2 && !i))
403 continue;
404
405 reg = (i == 0) ?
406 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
407 b43_phy_set(dev, reg, 0x400);
408
409 switch (intc_override) {
410 case N_INTC_OVERRIDE_OFF:
411 b43_phy_write(dev, reg, 0);
412 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
413 break;
414 case N_INTC_OVERRIDE_TRSW:
415 if (!i) {
416 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
417 0xFC3F, (value << 6));
418 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
419 0xFFFE, 1);
420 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
421 B43_NPHY_RFCTL_CMD_START);
422 for (j = 0; j < 100; j++) {
423 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
424 j = 0;
425 break;
426 }
427 udelay(10);
428 }
429 if (j)
430 b43err(dev->wl,
431 "intc override timeout\n");
432 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
433 0xFFFE);
434 } else {
435 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
436 0xFC3F, (value << 6));
437 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
438 0xFFFE, 1);
439 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
440 B43_NPHY_RFCTL_CMD_RXTX);
441 for (j = 0; j < 100; j++) {
442 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
443 j = 0;
444 break;
445 }
446 udelay(10);
447 }
448 if (j)
449 b43err(dev->wl,
450 "intc override timeout\n");
451 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
452 0xFFFE);
453 }
454 break;
455 case N_INTC_OVERRIDE_PA:
456 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
457 tmp = 0x0020;
458 val = value << 5;
459 } else {
460 tmp = 0x0010;
461 val = value << 4;
462 }
463 b43_phy_maskset(dev, reg, ~tmp, val);
464 break;
465 case N_INTC_OVERRIDE_EXT_LNA_PU:
466 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
467 tmp = 0x0001;
468 val = value;
469 } else {
470 tmp = 0x0004;
471 val = value << 2;
472 }
473 b43_phy_maskset(dev, reg, ~tmp, val);
474 break;
475 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
476 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
477 tmp = 0x0002;
478 val = value << 1;
479 } else {
480 tmp = 0x0008;
481 val = value << 3;
482 }
483 b43_phy_maskset(dev, reg, ~tmp, val);
484 break;
485 }
486 }
487 }
488
489
490
491
492
493
494 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
495 const u16 *clip_st)
496 {
497 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
498 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
499 }
500
501
502 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
503 {
504 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
505 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
506 }
507
508
509 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
510 {
511 u16 tmp;
512
513 if (dev->dev->core_rev == 16)
514 b43_mac_suspend(dev);
515
516 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
517 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
518 B43_NPHY_CLASSCTL_WAITEDEN);
519 tmp &= ~mask;
520 tmp |= (val & mask);
521 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
522
523 if (dev->dev->core_rev == 16)
524 b43_mac_enable(dev);
525
526 return tmp;
527 }
528
529
530 static void b43_nphy_reset_cca(struct b43_wldev *dev)
531 {
532 u16 bbcfg;
533
534 b43_phy_force_clock(dev, 1);
535 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
536 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
537 udelay(1);
538 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
539 b43_phy_force_clock(dev, 0);
540 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
541 }
542
543
544 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
545 {
546 struct b43_phy *phy = &dev->phy;
547 struct b43_phy_n *nphy = phy->n;
548
549 if (enable) {
550 static const u16 clip[] = { 0xFFFF, 0xFFFF };
551 if (nphy->deaf_count++ == 0) {
552 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
553 b43_nphy_classifier(dev, 0x7,
554 B43_NPHY_CLASSCTL_WAITEDEN);
555 b43_nphy_read_clip_detection(dev, nphy->clip_state);
556 b43_nphy_write_clip_detection(dev, clip);
557 }
558 b43_nphy_reset_cca(dev);
559 } else {
560 if (--nphy->deaf_count == 0) {
561 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
562 b43_nphy_write_clip_detection(dev, nphy->clip_state);
563 }
564 }
565 }
566
567
568 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
569 {
570 if (!offset)
571 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
572 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
573 }
574
575
576 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
577 {
578 struct b43_phy_n *nphy = dev->phy.n;
579
580 u8 i;
581 s16 tmp;
582 u16 data[4];
583 s16 gain[2];
584 u16 minmax[2];
585 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
586
587 if (nphy->hang_avoid)
588 b43_nphy_stay_in_carrier_search(dev, 1);
589
590 if (nphy->gain_boost) {
591 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
592 gain[0] = 6;
593 gain[1] = 6;
594 } else {
595 tmp = 40370 - 315 * dev->phy.channel;
596 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
597 tmp = 23242 - 224 * dev->phy.channel;
598 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
599 }
600 } else {
601 gain[0] = 0;
602 gain[1] = 0;
603 }
604
605 for (i = 0; i < 2; i++) {
606 if (nphy->elna_gain_config) {
607 data[0] = 19 + gain[i];
608 data[1] = 25 + gain[i];
609 data[2] = 25 + gain[i];
610 data[3] = 25 + gain[i];
611 } else {
612 data[0] = lna_gain[0] + gain[i];
613 data[1] = lna_gain[1] + gain[i];
614 data[2] = lna_gain[2] + gain[i];
615 data[3] = lna_gain[3] + gain[i];
616 }
617 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
618
619 minmax[i] = 23 + gain[i];
620 }
621
622 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
623 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
624 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
625 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
626
627 if (nphy->hang_avoid)
628 b43_nphy_stay_in_carrier_search(dev, 0);
629 }
630
631
632 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
633 u8 *events, u8 *delays, u8 length)
634 {
635 struct b43_phy_n *nphy = dev->phy.n;
636 u8 i;
637 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
638 u16 offset1 = cmd << 4;
639 u16 offset2 = offset1 + 0x80;
640
641 if (nphy->hang_avoid)
642 b43_nphy_stay_in_carrier_search(dev, true);
643
644 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
645 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
646
647 for (i = length; i < 16; i++) {
648 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
649 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
650 }
651
652 if (nphy->hang_avoid)
653 b43_nphy_stay_in_carrier_search(dev, false);
654 }
655
656
657
658
659
660 static void b43_radio_2057_chantab_upload(struct b43_wldev *dev,
661 const struct b43_nphy_chantabent_rev7 *e_r7,
662 const struct b43_nphy_chantabent_rev7_2g *e_r7_2g)
663 {
664 if (e_r7_2g) {
665 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
666 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
667 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
668 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
669 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
670 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
671 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
672 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
673 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
674 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
675 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
676 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
677 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
678 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
679 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
680 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
681 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
682 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
683
684 } else {
685 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
686 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
687 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
688 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
689 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
690 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
691 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
692 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
693 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
694 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
695 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
696 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
697 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
698 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
699 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
700 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
701 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
702 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
703 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
704 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
705 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
706 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
707 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
708 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
709 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
710 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
711 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
712 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
713 }
714 }
715
716 static void b43_radio_2057_setup(struct b43_wldev *dev,
717 const struct b43_nphy_chantabent_rev7 *tabent_r7,
718 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g)
719 {
720 struct b43_phy *phy = &dev->phy;
721
722 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g);
723
724 switch (phy->radio_rev) {
725 case 0 ... 4:
726 case 6:
727 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
728 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
729 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
730 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
731 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
732 } else {
733 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
734 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
735 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
736 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
737 }
738 break;
739 case 9:
740 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20);
741 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18);
742 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
743 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38);
744 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f);
745
746 if (b43_is_40mhz(dev)) {
747
748 } else {
749 b43_radio_write(dev,
750 R2057_PAD_BIAS_FILTER_BWS_CORE0,
751 0x3c);
752 b43_radio_write(dev,
753 R2057_PAD_BIAS_FILTER_BWS_CORE1,
754 0x3c);
755 }
756 }
757 break;
758 case 14:
759 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b);
760 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
761 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f);
762 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f);
763 break;
764 }
765
766 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
767 u16 txmix2g_tune_boost_pu = 0;
768 u16 pad2g_tune_pus = 0;
769
770 if (b43_nphy_ipa(dev)) {
771 switch (phy->radio_rev) {
772 case 9:
773 txmix2g_tune_boost_pu = 0x0041;
774
775 break;
776 case 14:
777 txmix2g_tune_boost_pu = 0x21;
778 pad2g_tune_pus = 0x23;
779 break;
780 }
781 }
782
783 if (txmix2g_tune_boost_pu)
784 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
785 txmix2g_tune_boost_pu);
786 if (pad2g_tune_pus)
787 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0,
788 pad2g_tune_pus);
789 if (txmix2g_tune_boost_pu)
790 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
791 txmix2g_tune_boost_pu);
792 if (pad2g_tune_pus)
793 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1,
794 pad2g_tune_pus);
795 }
796
797 usleep_range(50, 100);
798
799
800 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01);
801 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
802 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
803 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
804 usleep_range(300, 600);
805 }
806
807
808
809
810 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
811 {
812 struct b43_phy *phy = &dev->phy;
813 u16 saved_regs_phy[12];
814 u16 saved_regs_phy_rf[6];
815 u16 saved_regs_radio[2] = { };
816 static const u16 phy_to_store[] = {
817 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2,
818 B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2,
819 B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2,
820 B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2,
821 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
822 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
823 };
824 static const u16 phy_to_store_rf[] = {
825 B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1,
826 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
827 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
828 };
829 u16 tmp;
830 int i;
831
832
833 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
834 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]);
835 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
836 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]);
837
838
839 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
840 b43_phy_write(dev, phy_to_store[i], 0);
841 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff);
842 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff);
843 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff);
844 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff);
845 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f);
846 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f);
847
848 switch (phy->radio_rev) {
849 case 5:
850 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2);
851 udelay(10);
852 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
853 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1);
854 break;
855 case 9:
856 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
857 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
858 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
859 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11);
860 break;
861 case 14:
862 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU);
863 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2);
864 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
865 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2);
866 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2);
867 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1);
868 break;
869 }
870
871
872 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
873 udelay(10);
874
875
876 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
877 usleep_range(100, 200);
878
879
880 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
881
882
883 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
884 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
885 return 0;
886 }
887 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
888
889
890 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
891
892
893 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++)
894 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]);
895 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++)
896 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]);
897
898 switch (phy->radio_rev) {
899 case 0 ... 4:
900 case 6:
901 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
902 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
903 tmp << 2);
904 break;
905 case 5:
906 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
907 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2);
908 break;
909 case 9:
910 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
911 break;
912 case 14:
913 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
914 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]);
915 break;
916 }
917
918 return tmp & 0x3e;
919 }
920
921
922
923
924 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
925 {
926 struct b43_phy *phy = &dev->phy;
927 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
928 phy->radio_rev == 6);
929 u16 tmp;
930
931
932 if (special) {
933 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
934 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
935 } else {
936 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61);
937 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9);
938 }
939 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
940
941
942 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
943 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
944 5000000))
945 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
946 usleep_range(35, 70);
947 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
948 usleep_range(70, 140);
949
950
951 if (special) {
952 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
953 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
954 } else {
955 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69);
956 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
957 }
958 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
959
960
961 usleep_range(35, 70);
962 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
963 usleep_range(70, 140);
964 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
965 5000000))
966 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
967 usleep_range(35, 70);
968 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
969 usleep_range(70, 140);
970
971
972 if (special) {
973 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
974 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
975 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
976 } else {
977 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73);
978 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
979 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
980 }
981
982
983 usleep_range(35, 70);
984 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
985 usleep_range(70, 140);
986 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
987 5000000)) {
988 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
989 return 0;
990 }
991 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
992 usleep_range(35, 70);
993 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
994 usleep_range(70, 140);
995
996 if (special)
997 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1);
998 else
999 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1);
1000
1001 return tmp;
1002 }
1003
1004 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
1005 {
1006 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1007
1008 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
1009 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1010 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
1011 }
1012
1013 static void b43_radio_2057_init_post(struct b43_wldev *dev)
1014 {
1015 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
1016
1017 if (0)
1018 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2);
1019
1020 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
1021 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
1022 usleep_range(2000, 3000);
1023 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
1024 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
1025
1026 if (dev->phy.do_full_init) {
1027 b43_radio_2057_rcal(dev);
1028 b43_radio_2057_rccal(dev);
1029 }
1030 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
1031 }
1032
1033
1034 static void b43_radio_2057_init(struct b43_wldev *dev)
1035 {
1036 b43_radio_2057_init_pre(dev);
1037 r2057_upload_inittabs(dev);
1038 b43_radio_2057_init_post(dev);
1039 }
1040
1041
1042
1043
1044
1045 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
1046 const struct b43_nphy_channeltab_entry_rev3 *e)
1047 {
1048 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
1049 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
1050 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
1051 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
1052 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
1053 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
1054 e->radio_syn_pll_loopfilter1);
1055 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
1056 e->radio_syn_pll_loopfilter2);
1057 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
1058 e->radio_syn_pll_loopfilter3);
1059 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
1060 e->radio_syn_pll_loopfilter4);
1061 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
1062 e->radio_syn_pll_loopfilter5);
1063 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
1064 e->radio_syn_reserved_addr27);
1065 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
1066 e->radio_syn_reserved_addr28);
1067 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
1068 e->radio_syn_reserved_addr29);
1069 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
1070 e->radio_syn_logen_vcobuf1);
1071 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
1072 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
1073 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
1074
1075 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
1076 e->radio_rx0_lnaa_tune);
1077 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
1078 e->radio_rx0_lnag_tune);
1079
1080 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
1081 e->radio_tx0_intpaa_boost_tune);
1082 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
1083 e->radio_tx0_intpag_boost_tune);
1084 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
1085 e->radio_tx0_pada_boost_tune);
1086 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
1087 e->radio_tx0_padg_boost_tune);
1088 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
1089 e->radio_tx0_pgaa_boost_tune);
1090 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
1091 e->radio_tx0_pgag_boost_tune);
1092 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
1093 e->radio_tx0_mixa_boost_tune);
1094 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
1095 e->radio_tx0_mixg_boost_tune);
1096
1097 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
1098 e->radio_rx1_lnaa_tune);
1099 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
1100 e->radio_rx1_lnag_tune);
1101
1102 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
1103 e->radio_tx1_intpaa_boost_tune);
1104 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
1105 e->radio_tx1_intpag_boost_tune);
1106 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
1107 e->radio_tx1_pada_boost_tune);
1108 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
1109 e->radio_tx1_padg_boost_tune);
1110 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
1111 e->radio_tx1_pgaa_boost_tune);
1112 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
1113 e->radio_tx1_pgag_boost_tune);
1114 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
1115 e->radio_tx1_mixa_boost_tune);
1116 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
1117 e->radio_tx1_mixg_boost_tune);
1118 }
1119
1120
1121 static void b43_radio_2056_setup(struct b43_wldev *dev,
1122 const struct b43_nphy_channeltab_entry_rev3 *e)
1123 {
1124 struct b43_phy *phy = &dev->phy;
1125 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1126 enum nl80211_band band = b43_current_band(dev->wl);
1127 u16 offset;
1128 u8 i;
1129 u16 bias, cbias;
1130 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
1131 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
1132 bool is_pkg_fab_smic;
1133
1134 B43_WARN_ON(dev->phy.rev < 3);
1135
1136 is_pkg_fab_smic =
1137 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
1138 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
1139 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
1140 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
1141
1142 b43_chantab_radio_2056_upload(dev, e);
1143 b2056_upload_syn_pll_cp2(dev, band == NL80211_BAND_5GHZ);
1144
1145 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1146 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
1147 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1148 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1149 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1150 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
1151 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
1152 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
1153 } else {
1154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
1155 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
1156 }
1157 }
1158 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
1159 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
1161 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
1162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
1163 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
1164 }
1165 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1166 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
1167 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1168 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1169 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
1170 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
1171 }
1172
1173 if (dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) {
1174 for (i = 0; i < 2; i++) {
1175 offset = i ? B2056_TX1 : B2056_TX0;
1176 if (dev->phy.rev >= 5) {
1177 b43_radio_write(dev,
1178 offset | B2056_TX_PADG_IDAC, 0xcc);
1179
1180 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1181 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
1182 bias = 0x40;
1183 cbias = 0x45;
1184 pag_boost = 0x5;
1185 pgag_boost = 0x33;
1186 mixg_boost = 0x55;
1187 } else {
1188 bias = 0x25;
1189 cbias = 0x20;
1190 if (is_pkg_fab_smic) {
1191 bias = 0x2a;
1192 cbias = 0x38;
1193 }
1194 pag_boost = 0x4;
1195 pgag_boost = 0x03;
1196 mixg_boost = 0x65;
1197 }
1198 padg_boost = 0x77;
1199
1200 b43_radio_write(dev,
1201 offset | B2056_TX_INTPAG_IMAIN_STAT,
1202 bias);
1203 b43_radio_write(dev,
1204 offset | B2056_TX_INTPAG_IAUX_STAT,
1205 bias);
1206 b43_radio_write(dev,
1207 offset | B2056_TX_INTPAG_CASCBIAS,
1208 cbias);
1209 b43_radio_write(dev,
1210 offset | B2056_TX_INTPAG_BOOST_TUNE,
1211 pag_boost);
1212 b43_radio_write(dev,
1213 offset | B2056_TX_PGAG_BOOST_TUNE,
1214 pgag_boost);
1215 b43_radio_write(dev,
1216 offset | B2056_TX_PADG_BOOST_TUNE,
1217 padg_boost);
1218 b43_radio_write(dev,
1219 offset | B2056_TX_MIXG_BOOST_TUNE,
1220 mixg_boost);
1221 } else {
1222 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
1223 b43_radio_write(dev,
1224 offset | B2056_TX_INTPAG_IMAIN_STAT,
1225 bias);
1226 b43_radio_write(dev,
1227 offset | B2056_TX_INTPAG_IAUX_STAT,
1228 bias);
1229 b43_radio_write(dev,
1230 offset | B2056_TX_INTPAG_CASCBIAS,
1231 0x30);
1232 }
1233 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
1234 }
1235 } else if (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ) {
1236 u16 freq = phy->chandef->chan->center_freq;
1237 if (freq < 5100) {
1238 paa_boost = 0xA;
1239 pada_boost = 0x77;
1240 pgaa_boost = 0xF;
1241 mixa_boost = 0xF;
1242 } else if (freq < 5340) {
1243 paa_boost = 0x8;
1244 pada_boost = 0x77;
1245 pgaa_boost = 0xFB;
1246 mixa_boost = 0xF;
1247 } else if (freq < 5650) {
1248 paa_boost = 0x0;
1249 pada_boost = 0x77;
1250 pgaa_boost = 0xB;
1251 mixa_boost = 0xF;
1252 } else {
1253 paa_boost = 0x0;
1254 pada_boost = 0x77;
1255 if (freq != 5825)
1256 pgaa_boost = -(freq - 18) / 36 + 168;
1257 else
1258 pgaa_boost = 6;
1259 mixa_boost = 0xF;
1260 }
1261
1262 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
1263
1264 for (i = 0; i < 2; i++) {
1265 offset = i ? B2056_TX1 : B2056_TX0;
1266
1267 b43_radio_write(dev,
1268 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
1269 b43_radio_write(dev,
1270 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
1271 b43_radio_write(dev,
1272 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
1273 b43_radio_write(dev,
1274 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
1275 b43_radio_write(dev,
1276 offset | B2056_TX_TXSPARE1, 0x30);
1277 b43_radio_write(dev,
1278 offset | B2056_TX_PA_SPARE2, 0xee);
1279 b43_radio_write(dev,
1280 offset | B2056_TX_PADA_CASCBIAS, 0x03);
1281 b43_radio_write(dev,
1282 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
1283 b43_radio_write(dev,
1284 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
1285 b43_radio_write(dev,
1286 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
1287 }
1288 }
1289
1290 udelay(50);
1291
1292 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
1293 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1294 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
1295 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1296 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
1297 udelay(300);
1298 }
1299
1300 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
1301 {
1302 struct b43_phy *phy = &dev->phy;
1303 u16 mast2, tmp;
1304
1305 if (phy->rev != 3)
1306 return 0;
1307
1308 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
1309 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1310
1311 udelay(10);
1312 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1313 udelay(10);
1314 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
1315
1316 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1317 1000000)) {
1318 b43err(dev->wl, "Radio recalibration timeout\n");
1319 return 0;
1320 }
1321
1322 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1323 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1325
1326 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1327
1328 return tmp & 0x1f;
1329 }
1330
1331 static void b43_radio_init2056_pre(struct b43_wldev *dev)
1332 {
1333 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1334 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1335
1336 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1337 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1338 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1339 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1340 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1341 B43_NPHY_RFCTL_CMD_CHIP0PU);
1342 }
1343
1344 static void b43_radio_init2056_post(struct b43_wldev *dev)
1345 {
1346 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1347 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1348 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1349 msleep(1);
1350 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1351 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1352 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
1353 if (dev->phy.do_full_init)
1354 b43_radio_2056_rcal(dev);
1355 }
1356
1357
1358
1359
1360
1361 static void b43_radio_init2056(struct b43_wldev *dev)
1362 {
1363 b43_radio_init2056_pre(dev);
1364 b2056_upload_inittabs(dev, 0, 0);
1365 b43_radio_init2056_post(dev);
1366 }
1367
1368
1369
1370
1371
1372 static void b43_chantab_radio_upload(struct b43_wldev *dev,
1373 const struct b43_nphy_channeltab_entry_rev2 *e)
1374 {
1375 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1376 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1377 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1378 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1379 b43_read32(dev, B43_MMIO_MACCTL);
1380
1381 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1382 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1383 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1384 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1385 b43_read32(dev, B43_MMIO_MACCTL);
1386
1387 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1388 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1389 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1390 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1391 b43_read32(dev, B43_MMIO_MACCTL);
1392
1393 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1394 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1395 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1396 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1397 b43_read32(dev, B43_MMIO_MACCTL);
1398
1399 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1400 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1401 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1402 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1403 b43_read32(dev, B43_MMIO_MACCTL);
1404
1405 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1406 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1407 }
1408
1409
1410 static void b43_radio_2055_setup(struct b43_wldev *dev,
1411 const struct b43_nphy_channeltab_entry_rev2 *e)
1412 {
1413 B43_WARN_ON(dev->phy.rev >= 3);
1414
1415 b43_chantab_radio_upload(dev, e);
1416 udelay(50);
1417 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1418 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1419 b43_read32(dev, B43_MMIO_MACCTL);
1420 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1421 udelay(300);
1422 }
1423
1424 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1425 {
1426 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1427 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1428 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1429 B43_NPHY_RFCTL_CMD_CHIP0PU |
1430 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1431 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1432 B43_NPHY_RFCTL_CMD_PORFORCE);
1433 }
1434
1435 static void b43_radio_init2055_post(struct b43_wldev *dev)
1436 {
1437 struct b43_phy_n *nphy = dev->phy.n;
1438 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1439 bool workaround = false;
1440
1441 if (sprom->revision < 4)
1442 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1443 && dev->dev->board_type == SSB_BOARD_CB2_4321
1444 && dev->dev->board_rev >= 0x41);
1445 else
1446 workaround =
1447 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1448
1449 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1450 if (workaround) {
1451 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1452 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1453 }
1454 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1455 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1456 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1457 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1458 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1459 msleep(1);
1460 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1461 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1462 b43err(dev->wl, "radio post init timeout\n");
1463 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1464 b43_switch_channel(dev, dev->phy.channel);
1465 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1466 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1467 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1468 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1469 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1470 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1471 if (!nphy->gain_boost) {
1472 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1473 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1474 } else {
1475 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1476 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1477 }
1478 udelay(2);
1479 }
1480
1481
1482
1483
1484
1485 static void b43_radio_init2055(struct b43_wldev *dev)
1486 {
1487 b43_radio_init2055_pre(dev);
1488 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1489
1490 b2055_upload_inittab(dev, 0, 0);
1491 } else {
1492 bool ghz5 = b43_current_band(dev->wl) == NL80211_BAND_5GHZ;
1493 b2055_upload_inittab(dev, ghz5, 0);
1494 }
1495 b43_radio_init2055_post(dev);
1496 }
1497
1498
1499
1500
1501
1502
1503 static int b43_nphy_load_samples(struct b43_wldev *dev,
1504 struct cordic_iq *samples, u16 len) {
1505 struct b43_phy_n *nphy = dev->phy.n;
1506 u16 i;
1507 u32 *data;
1508
1509 data = kcalloc(len, sizeof(u32), GFP_KERNEL);
1510 if (!data) {
1511 b43err(dev->wl, "allocation for samples loading failed\n");
1512 return -ENOMEM;
1513 }
1514 if (nphy->hang_avoid)
1515 b43_nphy_stay_in_carrier_search(dev, 1);
1516
1517 for (i = 0; i < len; i++) {
1518 data[i] = (samples[i].i & 0x3FF << 10);
1519 data[i] |= samples[i].q & 0x3FF;
1520 }
1521 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1522
1523 kfree(data);
1524 if (nphy->hang_avoid)
1525 b43_nphy_stay_in_carrier_search(dev, 0);
1526 return 0;
1527 }
1528
1529
1530 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1531 bool test)
1532 {
1533 int i;
1534 u16 bw, len, rot, angle;
1535 struct cordic_iq *samples;
1536
1537 bw = b43_is_40mhz(dev) ? 40 : 20;
1538 len = bw << 3;
1539
1540 if (test) {
1541 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1542 bw = 82;
1543 else
1544 bw = 80;
1545
1546 if (b43_is_40mhz(dev))
1547 bw <<= 1;
1548
1549 len = bw << 1;
1550 }
1551
1552 samples = kcalloc(len, sizeof(struct cordic_iq), GFP_KERNEL);
1553 if (!samples) {
1554 b43err(dev->wl, "allocation for samples generation failed\n");
1555 return 0;
1556 }
1557 rot = (((freq * 36) / bw) << 16) / 100;
1558 angle = 0;
1559
1560 for (i = 0; i < len; i++) {
1561 samples[i] = cordic_calc_iq(CORDIC_FIXED(angle));
1562 angle += rot;
1563 samples[i].q = CORDIC_FLOAT(samples[i].q * max);
1564 samples[i].i = CORDIC_FLOAT(samples[i].i * max);
1565 }
1566
1567 i = b43_nphy_load_samples(dev, samples, len);
1568 kfree(samples);
1569 return (i < 0) ? 0 : len;
1570 }
1571
1572
1573 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1574 u16 wait, bool iqmode, bool dac_test,
1575 bool modify_bbmult)
1576 {
1577 struct b43_phy *phy = &dev->phy;
1578 struct b43_phy_n *nphy = dev->phy.n;
1579 int i;
1580 u16 seq_mode;
1581 u32 tmp;
1582
1583 b43_nphy_stay_in_carrier_search(dev, true);
1584
1585 if (phy->rev >= 7) {
1586 bool lpf_bw3, lpf_bw4;
1587
1588 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
1589 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80;
1590
1591 if (lpf_bw3 || lpf_bw4) {
1592
1593 } else {
1594 u16 value = b43_nphy_read_lpf_ctl(dev, 0);
1595 if (phy->rev >= 19)
1596 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value,
1597 0, false, 1);
1598 else
1599 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value,
1600 0, false, 1);
1601 nphy->lpf_bw_overrode_for_sample_play = true;
1602 }
1603 }
1604
1605 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1606 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1607 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1608 }
1609
1610 if (modify_bbmult) {
1611 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
1612 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1613 }
1614
1615 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1616
1617 if (loops != 0xFFFF)
1618 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1619 else
1620 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1621
1622 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1623
1624 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1625
1626 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1627 if (iqmode) {
1628 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1629 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1630 } else {
1631 tmp = dac_test ? 5 : 1;
1632 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
1633 }
1634 for (i = 0; i < 100; i++) {
1635 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1636 i = 0;
1637 break;
1638 }
1639 udelay(10);
1640 }
1641 if (i)
1642 b43err(dev->wl, "run samples timeout\n");
1643
1644 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1645
1646 b43_nphy_stay_in_carrier_search(dev, false);
1647 }
1648
1649
1650
1651
1652
1653
1654 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1655 s8 offset, u8 core,
1656 enum n_rail_type rail,
1657 enum n_rssi_type rssi_type)
1658 {
1659 u16 tmp;
1660 bool core1or5 = (core == 1) || (core == 5);
1661 bool core2or5 = (core == 2) || (core == 5);
1662
1663 offset = clamp_val(offset, -32, 31);
1664 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1665
1666 switch (rssi_type) {
1667 case N_RSSI_NB:
1668 if (core1or5 && rail == N_RAIL_I)
1669 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1670 if (core1or5 && rail == N_RAIL_Q)
1671 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1672 if (core2or5 && rail == N_RAIL_I)
1673 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1674 if (core2or5 && rail == N_RAIL_Q)
1675 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1676 break;
1677 case N_RSSI_W1:
1678 if (core1or5 && rail == N_RAIL_I)
1679 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1680 if (core1or5 && rail == N_RAIL_Q)
1681 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1682 if (core2or5 && rail == N_RAIL_I)
1683 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1684 if (core2or5 && rail == N_RAIL_Q)
1685 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1686 break;
1687 case N_RSSI_W2:
1688 if (core1or5 && rail == N_RAIL_I)
1689 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1690 if (core1or5 && rail == N_RAIL_Q)
1691 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1692 if (core2or5 && rail == N_RAIL_I)
1693 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1694 if (core2or5 && rail == N_RAIL_Q)
1695 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1696 break;
1697 case N_RSSI_TBD:
1698 if (core1or5 && rail == N_RAIL_I)
1699 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1700 if (core1or5 && rail == N_RAIL_Q)
1701 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1702 if (core2or5 && rail == N_RAIL_I)
1703 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1704 if (core2or5 && rail == N_RAIL_Q)
1705 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1706 break;
1707 case N_RSSI_IQ:
1708 if (core1or5 && rail == N_RAIL_I)
1709 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1710 if (core1or5 && rail == N_RAIL_Q)
1711 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1712 if (core2or5 && rail == N_RAIL_I)
1713 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1714 if (core2or5 && rail == N_RAIL_Q)
1715 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1716 break;
1717 case N_RSSI_TSSI_2G:
1718 if (core1or5)
1719 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1720 if (core2or5)
1721 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1722 break;
1723 case N_RSSI_TSSI_5G:
1724 if (core1or5)
1725 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1726 if (core2or5)
1727 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1728 break;
1729 }
1730 }
1731
1732 static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code,
1733 enum n_rssi_type rssi_type)
1734 {
1735
1736 }
1737
1738 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1739 enum n_rssi_type rssi_type)
1740 {
1741 u8 i;
1742 u16 reg, val;
1743
1744 if (code == 0) {
1745 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1746 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1747 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1748 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1749 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1750 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1751 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1752 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1753 } else {
1754 for (i = 0; i < 2; i++) {
1755 if ((code == 1 && i == 1) || (code == 2 && !i))
1756 continue;
1757
1758 reg = (i == 0) ?
1759 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1760 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1761
1762 if (rssi_type == N_RSSI_W1 ||
1763 rssi_type == N_RSSI_W2 ||
1764 rssi_type == N_RSSI_NB) {
1765 reg = (i == 0) ?
1766 B43_NPHY_AFECTL_C1 :
1767 B43_NPHY_AFECTL_C2;
1768 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1769
1770 reg = (i == 0) ?
1771 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1772 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1773 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1774
1775 if (rssi_type == N_RSSI_W1)
1776 val = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 4 : 8;
1777 else if (rssi_type == N_RSSI_W2)
1778 val = 16;
1779 else
1780 val = 32;
1781 b43_phy_set(dev, reg, val);
1782
1783 reg = (i == 0) ?
1784 B43_NPHY_TXF_40CO_B1S0 :
1785 B43_NPHY_TXF_40CO_B32S1;
1786 b43_phy_set(dev, reg, 0x0020);
1787 } else {
1788 if (rssi_type == N_RSSI_TBD)
1789 val = 0x0100;
1790 else if (rssi_type == N_RSSI_IQ)
1791 val = 0x0200;
1792 else
1793 val = 0x0300;
1794
1795 reg = (i == 0) ?
1796 B43_NPHY_AFECTL_C1 :
1797 B43_NPHY_AFECTL_C2;
1798
1799 b43_phy_maskset(dev, reg, 0xFCFF, val);
1800 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1801
1802 if (rssi_type != N_RSSI_IQ &&
1803 rssi_type != N_RSSI_TBD) {
1804 enum nl80211_band band =
1805 b43_current_band(dev->wl);
1806
1807 if (dev->phy.rev < 7) {
1808 if (b43_nphy_ipa(dev))
1809 val = (band == NL80211_BAND_5GHZ) ? 0xC : 0xE;
1810 else
1811 val = 0x11;
1812 reg = (i == 0) ? B2056_TX0 : B2056_TX1;
1813 reg |= B2056_TX_TX_SSI_MUX;
1814 b43_radio_write(dev, reg, val);
1815 }
1816
1817 reg = (i == 0) ?
1818 B43_NPHY_AFECTL_OVER1 :
1819 B43_NPHY_AFECTL_OVER;
1820 b43_phy_set(dev, reg, 0x0200);
1821 }
1822 }
1823 }
1824 }
1825 }
1826
1827 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1828 enum n_rssi_type rssi_type)
1829 {
1830 u16 val;
1831 bool rssi_w1_w2_nb = false;
1832
1833 switch (rssi_type) {
1834 case N_RSSI_W1:
1835 case N_RSSI_W2:
1836 case N_RSSI_NB:
1837 val = 0;
1838 rssi_w1_w2_nb = true;
1839 break;
1840 case N_RSSI_TBD:
1841 val = 1;
1842 break;
1843 case N_RSSI_IQ:
1844 val = 2;
1845 break;
1846 default:
1847 val = 3;
1848 }
1849
1850 val = (val << 12) | (val << 14);
1851 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1852 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1853
1854 if (rssi_w1_w2_nb) {
1855 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1856 (rssi_type + 1) << 4);
1857 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1858 (rssi_type + 1) << 4);
1859 }
1860
1861 if (code == 0) {
1862 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1863 if (rssi_w1_w2_nb) {
1864 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1865 ~(B43_NPHY_RFCTL_CMD_RXEN |
1866 B43_NPHY_RFCTL_CMD_CORESEL));
1867 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1868 ~(0x1 << 12 |
1869 0x1 << 5 |
1870 0x1 << 1 |
1871 0x1));
1872 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1873 ~B43_NPHY_RFCTL_CMD_START);
1874 udelay(20);
1875 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1876 }
1877 } else {
1878 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1879 if (rssi_w1_w2_nb) {
1880 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1881 ~(B43_NPHY_RFCTL_CMD_RXEN |
1882 B43_NPHY_RFCTL_CMD_CORESEL),
1883 (B43_NPHY_RFCTL_CMD_RXEN |
1884 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1885 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1886 (0x1 << 12 |
1887 0x1 << 5 |
1888 0x1 << 1 |
1889 0x1));
1890 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1891 B43_NPHY_RFCTL_CMD_START);
1892 udelay(20);
1893 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1894 }
1895 }
1896 }
1897
1898
1899 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1900 enum n_rssi_type type)
1901 {
1902 if (dev->phy.rev >= 19)
1903 b43_nphy_rssi_select_rev19(dev, code, type);
1904 else if (dev->phy.rev >= 3)
1905 b43_nphy_rev3_rssi_select(dev, code, type);
1906 else
1907 b43_nphy_rev2_rssi_select(dev, code, type);
1908 }
1909
1910
1911 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1912 enum n_rssi_type rssi_type, u8 *buf)
1913 {
1914 int i;
1915 for (i = 0; i < 2; i++) {
1916 if (rssi_type == N_RSSI_NB) {
1917 if (i == 0) {
1918 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1919 0xFC, buf[0]);
1920 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1921 0xFC, buf[1]);
1922 } else {
1923 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1924 0xFC, buf[2 * i]);
1925 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1926 0xFC, buf[2 * i + 1]);
1927 }
1928 } else {
1929 if (i == 0)
1930 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1931 0xF3, buf[0] << 2);
1932 else
1933 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1934 0xF3, buf[2 * i + 1] << 2);
1935 }
1936 }
1937 }
1938
1939
1940 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1941 s32 *buf, u8 nsamp)
1942 {
1943 int i;
1944 int out;
1945 u16 save_regs_phy[9];
1946 u16 s[2];
1947
1948
1949
1950 if (dev->phy.rev >= 3) {
1951 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1952 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1953 save_regs_phy[2] = b43_phy_read(dev,
1954 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1955 save_regs_phy[3] = b43_phy_read(dev,
1956 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1957 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1958 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1959 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1960 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1961 save_regs_phy[8] = 0;
1962 } else {
1963 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1964 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1965 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1966 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1967 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1968 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1969 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1970 save_regs_phy[7] = 0;
1971 save_regs_phy[8] = 0;
1972 }
1973
1974 b43_nphy_rssi_select(dev, 5, rssi_type);
1975
1976 if (dev->phy.rev < 2) {
1977 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1978 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1979 }
1980
1981 for (i = 0; i < 4; i++)
1982 buf[i] = 0;
1983
1984 for (i = 0; i < nsamp; i++) {
1985 if (dev->phy.rev < 2) {
1986 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1987 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1988 } else {
1989 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1990 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1991 }
1992
1993 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1994 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1995 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1996 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1997 }
1998 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1999 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2000
2001 if (dev->phy.rev < 2)
2002 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2003
2004 if (dev->phy.rev >= 3) {
2005 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2006 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2007 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2008 save_regs_phy[2]);
2009 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2010 save_regs_phy[3]);
2011 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2012 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2013 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2014 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2015 } else {
2016 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2017 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2018 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2019 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2020 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2021 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2022 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2023 }
2024
2025 return out;
2026 }
2027
2028
2029 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2030 {
2031 struct b43_phy *phy = &dev->phy;
2032 struct b43_phy_n *nphy = dev->phy.n;
2033
2034 u16 saved_regs_phy_rfctl[2];
2035 u16 saved_regs_phy[22];
2036 u16 regs_to_store_rev3[] = {
2037 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
2038 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
2039 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
2040 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
2041 B43_NPHY_RFCTL_CMD,
2042 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2043 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
2044 };
2045 u16 regs_to_store_rev7[] = {
2046 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
2047 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
2048 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
2049 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4,
2050 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6,
2051 0x2ff,
2052 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
2053 B43_NPHY_RFCTL_CMD,
2054 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2055 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4,
2056 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6,
2057 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
2058 };
2059 u16 *regs_to_store;
2060 int regs_amount;
2061
2062 u16 class;
2063
2064 u16 clip_state[2];
2065 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2066
2067 u8 vcm_final = 0;
2068 s32 offset[4];
2069 s32 results[8][4] = { };
2070 s32 results_min[4] = { };
2071 s32 poll_results[4] = { };
2072
2073 u16 *rssical_radio_regs = NULL;
2074 u16 *rssical_phy_regs = NULL;
2075
2076 u16 r;
2077 u8 rx_core_state;
2078 int core, i, j, vcm;
2079
2080 if (dev->phy.rev >= 7) {
2081 regs_to_store = regs_to_store_rev7;
2082 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
2083 } else {
2084 regs_to_store = regs_to_store_rev3;
2085 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
2086 }
2087 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
2088
2089 class = b43_nphy_classifier(dev, 0, 0);
2090 b43_nphy_classifier(dev, 7, 4);
2091 b43_nphy_read_clip_detection(dev, clip_state);
2092 b43_nphy_write_clip_detection(dev, clip_off);
2093
2094 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2095 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2096 for (i = 0; i < regs_amount; i++)
2097 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
2098
2099 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
2100 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
2101
2102 if (dev->phy.rev >= 7) {
2103 b43_nphy_rf_ctl_override_one_to_many(dev,
2104 N_RF_CTL_OVER_CMD_RXRF_PU,
2105 0, 0, false);
2106 b43_nphy_rf_ctl_override_one_to_many(dev,
2107 N_RF_CTL_OVER_CMD_RX_PU,
2108 1, 0, false);
2109 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
2110 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0);
2111 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
2112 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false,
2113 0);
2114 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false,
2115 0);
2116 } else {
2117 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false,
2118 0);
2119 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false,
2120 0);
2121 }
2122 } else {
2123 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
2124 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
2125 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
2126 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
2127 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
2128 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
2129 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
2130 } else {
2131 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
2132 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
2133 }
2134 }
2135
2136 rx_core_state = b43_nphy_get_rx_core_state(dev);
2137 for (core = 0; core < 2; core++) {
2138 if (!(rx_core_state & (1 << core)))
2139 continue;
2140 r = core ? B2056_RX1 : B2056_RX0;
2141 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
2142 N_RSSI_NB);
2143 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
2144 N_RSSI_NB);
2145
2146
2147 for (vcm = 0; vcm < 8; vcm++) {
2148 if (dev->phy.rev >= 7)
2149 b43_radio_maskset(dev,
2150 core ? R2057_NB_MASTER_CORE1 :
2151 R2057_NB_MASTER_CORE0,
2152 ~R2057_VCM_MASK, vcm);
2153 else
2154 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
2155 0xE3, vcm << 2);
2156 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
2157 }
2158
2159
2160 for (i = 0; i < 4; i += 2) {
2161 s32 currd;
2162 s32 mind = 0x100000;
2163 s32 minpoll = 249;
2164 u8 minvcm = 0;
2165 if (2 * core != i)
2166 continue;
2167 for (vcm = 0; vcm < 8; vcm++) {
2168 currd = results[vcm][i] * results[vcm][i] +
2169 results[vcm][i + 1] * results[vcm][i];
2170 if (currd < mind) {
2171 mind = currd;
2172 minvcm = vcm;
2173 }
2174 if (results[vcm][i] < minpoll)
2175 minpoll = results[vcm][i];
2176 }
2177 vcm_final = minvcm;
2178 results_min[i] = minpoll;
2179 }
2180
2181
2182 if (dev->phy.rev >= 7)
2183 b43_radio_maskset(dev,
2184 core ? R2057_NB_MASTER_CORE1 :
2185 R2057_NB_MASTER_CORE0,
2186 ~R2057_VCM_MASK, vcm);
2187 else
2188 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
2189 0xE3, vcm_final << 2);
2190
2191 for (i = 0; i < 4; i++) {
2192 if (core != i / 2)
2193 continue;
2194 offset[i] = -results[vcm_final][i];
2195 if (offset[i] < 0)
2196 offset[i] = -((abs(offset[i]) + 4) / 8);
2197 else
2198 offset[i] = (offset[i] + 4) / 8;
2199 if (results_min[i] == 248)
2200 offset[i] = -32;
2201 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
2202 (i / 2 == 0) ? 1 : 2,
2203 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
2204 N_RSSI_NB);
2205 }
2206 }
2207
2208 for (core = 0; core < 2; core++) {
2209 if (!(rx_core_state & (1 << core)))
2210 continue;
2211 for (i = 0; i < 2; i++) {
2212 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2213 N_RAIL_I, i);
2214 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2215 N_RAIL_Q, i);
2216 b43_nphy_poll_rssi(dev, i, poll_results, 8);
2217 for (j = 0; j < 4; j++) {
2218 if (j / 2 == core) {
2219 offset[j] = 232 - poll_results[j];
2220 if (offset[j] < 0)
2221 offset[j] = -(abs(offset[j] + 4) / 8);
2222 else
2223 offset[j] = (offset[j] + 4) / 8;
2224 b43_nphy_scale_offset_rssi(dev, 0,
2225 offset[2 * core], core + 1, j % 2, i);
2226 }
2227 }
2228 }
2229 }
2230
2231 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
2232 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
2233
2234 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2235
2236 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
2237 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
2238 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
2239
2240 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2241 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
2242 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2243
2244 for (i = 0; i < regs_amount; i++)
2245 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
2246
2247
2248 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
2249 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2250 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2251 } else {
2252 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2253 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2254 }
2255 if (dev->phy.rev >= 7) {
2256 rssical_radio_regs[0] = b43_radio_read(dev,
2257 R2057_NB_MASTER_CORE0);
2258 rssical_radio_regs[1] = b43_radio_read(dev,
2259 R2057_NB_MASTER_CORE1);
2260 } else {
2261 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
2262 B2056_RX_RSSI_MISC);
2263 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
2264 B2056_RX_RSSI_MISC);
2265 }
2266 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
2267 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
2268 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
2269 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
2270 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
2271 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
2272 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
2273 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
2274 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
2275 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
2276 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
2277 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
2278
2279
2280 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
2281 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
2282 else
2283 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
2284
2285
2286 b43_nphy_classifier(dev, 7, class);
2287 b43_nphy_write_clip_detection(dev, clip_state);
2288 }
2289
2290
2291 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
2292 {
2293 int i, j, vcm;
2294 u8 state[4];
2295 u8 code, val;
2296 u16 class, override;
2297 u8 regs_save_radio[2];
2298 u16 regs_save_phy[2];
2299
2300 s32 offset[4];
2301 u8 core;
2302 u8 rail;
2303
2304 u16 clip_state[2];
2305 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2306 s32 results_min[4] = { };
2307 u8 vcm_final[4] = { };
2308 s32 results[4][4] = { };
2309 s32 miniq[4][2] = { };
2310
2311 if (type == N_RSSI_NB) {
2312 code = 0;
2313 val = 6;
2314 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
2315 code = 25;
2316 val = 4;
2317 } else {
2318 B43_WARN_ON(1);
2319 return;
2320 }
2321
2322 class = b43_nphy_classifier(dev, 0, 0);
2323 b43_nphy_classifier(dev, 7, 4);
2324 b43_nphy_read_clip_detection(dev, clip_state);
2325 b43_nphy_write_clip_detection(dev, clip_off);
2326
2327 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
2328 override = 0x140;
2329 else
2330 override = 0x110;
2331
2332 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2333 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
2334 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2335 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
2336
2337 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2338 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
2339 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2340 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
2341
2342 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2343 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2344 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2345 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2346 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
2347 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
2348
2349 b43_nphy_rssi_select(dev, 5, type);
2350 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
2351 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
2352
2353 for (vcm = 0; vcm < 4; vcm++) {
2354 u8 tmp[4];
2355 for (j = 0; j < 4; j++)
2356 tmp[j] = vcm;
2357 if (type != N_RSSI_W2)
2358 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2359 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
2360 if (type == N_RSSI_W1 || type == N_RSSI_W2)
2361 for (j = 0; j < 2; j++)
2362 miniq[vcm][j] = min(results[vcm][2 * j],
2363 results[vcm][2 * j + 1]);
2364 }
2365
2366 for (i = 0; i < 4; i++) {
2367 s32 mind = 0x100000;
2368 u8 minvcm = 0;
2369 s32 minpoll = 249;
2370 s32 currd;
2371 for (vcm = 0; vcm < 4; vcm++) {
2372 if (type == N_RSSI_NB)
2373 currd = abs(results[vcm][i] - code * 8);
2374 else
2375 currd = abs(miniq[vcm][i / 2] - code * 8);
2376
2377 if (currd < mind) {
2378 mind = currd;
2379 minvcm = vcm;
2380 }
2381
2382 if (results[vcm][i] < minpoll)
2383 minpoll = results[vcm][i];
2384 }
2385 results_min[i] = minpoll;
2386 vcm_final[i] = minvcm;
2387 }
2388
2389 if (type != N_RSSI_W2)
2390 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2391
2392 for (i = 0; i < 4; i++) {
2393 offset[i] = (code * 8) - results[vcm_final[i]][i];
2394
2395 if (offset[i] < 0)
2396 offset[i] = -((abs(offset[i]) + 4) / 8);
2397 else
2398 offset[i] = (offset[i] + 4) / 8;
2399
2400 if (results_min[i] == 248)
2401 offset[i] = code - 32;
2402
2403 core = (i / 2) ? 2 : 1;
2404 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
2405
2406 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2407 type);
2408 }
2409
2410 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2411 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2412
2413 switch (state[2]) {
2414 case 1:
2415 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
2416 break;
2417 case 4:
2418 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
2419 break;
2420 case 2:
2421 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2422 break;
2423 default:
2424 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2425 break;
2426 }
2427
2428 switch (state[3]) {
2429 case 1:
2430 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
2431 break;
2432 case 4:
2433 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
2434 break;
2435 default:
2436 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
2437 break;
2438 }
2439
2440 b43_nphy_rssi_select(dev, 0, type);
2441
2442 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2443 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2444 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2445 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2446
2447 b43_nphy_classifier(dev, 7, class);
2448 b43_nphy_write_clip_detection(dev, clip_state);
2449
2450
2451 b43_nphy_reset_cca(dev);
2452 }
2453
2454
2455
2456
2457
2458 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2459 {
2460 if (dev->phy.rev >= 19) {
2461
2462 } else if (dev->phy.rev >= 3) {
2463 b43_nphy_rev3_rssi_cal(dev);
2464 } else {
2465 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2466 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2467 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
2468 }
2469 }
2470
2471
2472
2473
2474
2475 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev)
2476 {
2477
2478 }
2479
2480 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev)
2481 {
2482 struct b43_phy *phy = &dev->phy;
2483
2484 switch (phy->rev) {
2485
2486 }
2487 }
2488
2489 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev)
2490 {
2491 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2492
2493 bool ghz5;
2494 bool ext_lna;
2495 u16 rssi_gain;
2496 struct nphy_gain_ctl_workaround_entry *e;
2497 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2498 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2499
2500
2501 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2502 & B43_NPHY_BANDCTL_5GHZ;
2503 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2504 sprom->boardflags_lo & B43_BFL_EXTLNA;
2505 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2506 if (ghz5 && dev->phy.rev >= 5)
2507 rssi_gain = 0x90;
2508 else
2509 rssi_gain = 0x50;
2510
2511 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2512
2513
2514 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2515 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2516
2517 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2518 0x17);
2519 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2520 0x17);
2521 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2522 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2523 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2524 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2525 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2526 rssi_gain);
2527 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2528 rssi_gain);
2529 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2530 0x17);
2531 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2532 0x17);
2533 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2534 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2535
2536 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2537 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2538 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2539 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2540 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2541 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2542 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2543 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2544 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2545 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2546 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2547 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2548
2549 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2550 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2551
2552 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2553 e->rfseq_init);
2554
2555 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2556 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2557 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2558 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2559 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2560 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2561
2562 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2563 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2564 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2565 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2566 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2567 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2568 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2569 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2570 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2571 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2572 }
2573
2574 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2575 {
2576 struct b43_phy_n *nphy = dev->phy.n;
2577
2578 u8 i, j;
2579 u8 code;
2580 u16 tmp;
2581 u8 rfseq_events[3] = { 6, 8, 7 };
2582 u8 rfseq_delays[3] = { 10, 30, 1 };
2583
2584
2585 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2586 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2587
2588
2589 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2590 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2591
2592 if (!b43_is_40mhz(dev)) {
2593
2594 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2595 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2596 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2597 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2598 }
2599
2600
2601 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2602 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2603 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2604 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2605
2606 if (!b43_is_40mhz(dev)) {
2607 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2608 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2609 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2610 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2611 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2612 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2613 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2614 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2615 }
2616
2617 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2618
2619 if (nphy->gain_boost) {
2620 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ &&
2621 b43_is_40mhz(dev))
2622 code = 4;
2623 else
2624 code = 5;
2625 } else {
2626 code = b43_is_40mhz(dev) ? 6 : 7;
2627 }
2628
2629
2630 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2631 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2632 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2633 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2634
2635 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2636
2637 for (i = 0; i < 4; i++)
2638 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2639
2640 b43_nphy_adjust_lna_gain_table(dev);
2641
2642 if (nphy->elna_gain_config) {
2643 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2644 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2645 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2646 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2647 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2648
2649 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2650 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2651 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2652 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2653 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2654
2655 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2656
2657 for (i = 0; i < 4; i++)
2658 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2659 (code << 8 | 0x74));
2660 }
2661
2662 if (dev->phy.rev == 2) {
2663 for (i = 0; i < 4; i++) {
2664 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2665 (0x0400 * i) + 0x0020);
2666 for (j = 0; j < 21; j++) {
2667 tmp = j * (i < 2 ? 3 : 1);
2668 b43_phy_write(dev,
2669 B43_NPHY_TABLE_DATALO, tmp);
2670 }
2671 }
2672 }
2673
2674 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2675 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2676 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2677 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2678
2679 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
2680 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2681 }
2682
2683
2684 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2685 {
2686 if (dev->phy.rev >= 19)
2687 b43_nphy_gain_ctl_workarounds_rev19(dev);
2688 else if (dev->phy.rev >= 7)
2689 b43_nphy_gain_ctl_workarounds_rev7(dev);
2690 else if (dev->phy.rev >= 3)
2691 b43_nphy_gain_ctl_workarounds_rev3(dev);
2692 else
2693 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2694 }
2695
2696 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2697 {
2698 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2699 struct b43_phy *phy = &dev->phy;
2700
2701
2702 u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, };
2703 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, };
2704
2705 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2706 0x1F };
2707 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2708
2709 static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f };
2710 u8 ntab7_138_146[] = { 0x11, 0x11 };
2711 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2712
2713 u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2];
2714 u16 bcap_val;
2715 s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2];
2716 u16 scap_val;
2717 s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2];
2718 bool rccal_ovrd = false;
2719
2720 u16 bias, conv, filt;
2721
2722 u32 noise_tbl[2];
2723
2724 u32 tmp32;
2725 u8 core;
2726
2727 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2728 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3);
2729 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2730 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e);
2731 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd);
2732 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2733
2734 if (phy->rev == 7) {
2735 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2736 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2737 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2738 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2739 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2740 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2741 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2742 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2743 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2744 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2745 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2747 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2748 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2749 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2750 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2751 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2752 }
2753
2754 if (phy->rev >= 16) {
2755 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff);
2756 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff);
2757 } else if (phy->rev <= 8) {
2758 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2759 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2760 }
2761
2762 if (phy->rev >= 16)
2763 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0);
2764 else if (phy->rev >= 8)
2765 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2766
2767 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2768 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2769 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2770 tmp32 &= 0xffffff;
2771 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2772 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
2773 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
2774
2775 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2776 ARRAY_SIZE(tx2rx_events));
2777 if (b43_nphy_ipa(dev))
2778 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2779 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2780
2781 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2782 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2783
2784 for (core = 0; core < 2; core++) {
2785 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10);
2786 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10);
2787 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10);
2788 }
2789
2790 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL);
2791 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL);
2792
2793 if (b43_nphy_ipa(dev)) {
2794 bool ghz2 = b43_current_band(dev->wl) == NL80211_BAND_2GHZ;
2795
2796 switch (phy->radio_rev) {
2797 case 5:
2798
2799 if (phy->rev == 8 && b43_is_40mhz(dev)) {
2800 for (core = 0; core < 2; core++) {
2801 scap_val_11b[core] = scap_val;
2802 bcap_val_11b[core] = bcap_val;
2803 scap_val_11n_20[core] = scap_val;
2804 bcap_val_11n_20[core] = bcap_val;
2805 scap_val_11n_40[core] = 0xc;
2806 bcap_val_11n_40[core] = 0xc;
2807 }
2808
2809 rccal_ovrd = true;
2810 }
2811 if (phy->rev == 9) {
2812
2813 }
2814 break;
2815 case 7:
2816 case 8:
2817 for (core = 0; core < 2; core++) {
2818 scap_val_11b[core] = scap_val;
2819 bcap_val_11b[core] = bcap_val;
2820 lpf_ofdm_20mhz[core] = 4;
2821 lpf_11b[core] = 1;
2822 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
2823 scap_val_11n_20[core] = 0xc;
2824 bcap_val_11n_20[core] = 0xc;
2825 scap_val_11n_40[core] = 0xa;
2826 bcap_val_11n_40[core] = 0xa;
2827 } else {
2828 scap_val_11n_20[core] = 0x14;
2829 bcap_val_11n_20[core] = 0x14;
2830 scap_val_11n_40[core] = 0xf;
2831 bcap_val_11n_40[core] = 0xf;
2832 }
2833 }
2834
2835 rccal_ovrd = true;
2836 break;
2837 case 9:
2838 for (core = 0; core < 2; core++) {
2839 bcap_val_11b[core] = bcap_val;
2840 scap_val_11b[core] = scap_val;
2841 lpf_11b[core] = 1;
2842
2843 if (ghz2) {
2844 bcap_val_11n_20[core] = bcap_val + 13;
2845 scap_val_11n_20[core] = scap_val + 15;
2846 } else {
2847 bcap_val_11n_20[core] = bcap_val + 14;
2848 scap_val_11n_20[core] = scap_val + 15;
2849 }
2850 lpf_ofdm_20mhz[core] = 4;
2851
2852 if (ghz2) {
2853 bcap_val_11n_40[core] = bcap_val - 7;
2854 scap_val_11n_40[core] = scap_val - 5;
2855 } else {
2856 bcap_val_11n_40[core] = bcap_val + 2;
2857 scap_val_11n_40[core] = scap_val + 4;
2858 }
2859 lpf_ofdm_40mhz[core] = 4;
2860 }
2861
2862 rccal_ovrd = true;
2863 break;
2864 case 14:
2865 for (core = 0; core < 2; core++) {
2866 bcap_val_11b[core] = bcap_val;
2867 scap_val_11b[core] = scap_val;
2868 lpf_11b[core] = 1;
2869 }
2870
2871 bcap_val_11n_20[0] = bcap_val + 20;
2872 scap_val_11n_20[0] = scap_val + 20;
2873 lpf_ofdm_20mhz[0] = 3;
2874
2875 bcap_val_11n_20[1] = bcap_val + 16;
2876 scap_val_11n_20[1] = scap_val + 16;
2877 lpf_ofdm_20mhz[1] = 3;
2878
2879 bcap_val_11n_40[0] = bcap_val + 20;
2880 scap_val_11n_40[0] = scap_val + 20;
2881 lpf_ofdm_40mhz[0] = 4;
2882
2883 bcap_val_11n_40[1] = bcap_val + 10;
2884 scap_val_11n_40[1] = scap_val + 10;
2885 lpf_ofdm_40mhz[1] = 4;
2886
2887 rccal_ovrd = true;
2888 break;
2889 }
2890 } else {
2891 if (phy->radio_rev == 5) {
2892 for (core = 0; core < 2; core++) {
2893 lpf_ofdm_20mhz[core] = 1;
2894 lpf_ofdm_40mhz[core] = 3;
2895 scap_val_11b[core] = scap_val;
2896 bcap_val_11b[core] = bcap_val;
2897 scap_val_11n_20[core] = 0x11;
2898 scap_val_11n_40[core] = 0x11;
2899 bcap_val_11n_20[core] = 0x13;
2900 bcap_val_11n_40[core] = 0x13;
2901 }
2902
2903 rccal_ovrd = true;
2904 }
2905 }
2906 if (rccal_ovrd) {
2907 u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2];
2908 u8 rx2tx_lut_extra = 1;
2909
2910 for (core = 0; core < 2; core++) {
2911 bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f);
2912 scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f);
2913 bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f);
2914 scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f);
2915 bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f);
2916 scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f);
2917
2918 rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) |
2919 (bcap_val_11b[core] << 8) |
2920 (scap_val_11b[core] << 3) |
2921 lpf_11b[core];
2922 rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) |
2923 (bcap_val_11n_20[core] << 8) |
2924 (scap_val_11n_20[core] << 3) |
2925 lpf_ofdm_20mhz[core];
2926 rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) |
2927 (bcap_val_11n_40[core] << 8) |
2928 (scap_val_11n_40[core] << 3) |
2929 lpf_ofdm_40mhz[core];
2930 }
2931
2932 for (core = 0; core < 2; core++) {
2933 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2934 rx2tx_lut_20_11b[core]);
2935 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2936 rx2tx_lut_20_11n[core]);
2937 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2938 rx2tx_lut_20_11n[core]);
2939 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2940 rx2tx_lut_40_11n[core]);
2941 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2942 rx2tx_lut_40_11n[core]);
2943 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2944 rx2tx_lut_40_11n[core]);
2945 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2946 rx2tx_lut_40_11n[core]);
2947 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2948 rx2tx_lut_40_11n[core]);
2949 }
2950 }
2951
2952 b43_phy_write(dev, 0x32F, 0x3);
2953
2954 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2955 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2956
2957 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2958 if (sprom->revision &&
2959 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2960 b43_radio_write(dev, 0x5, 0x05);
2961 b43_radio_write(dev, 0x6, 0x30);
2962 b43_radio_write(dev, 0x7, 0x00);
2963 b43_radio_set(dev, 0x4f, 0x1);
2964 b43_radio_set(dev, 0xd4, 0x1);
2965 bias = 0x1f;
2966 conv = 0x6f;
2967 filt = 0xaa;
2968 } else {
2969 bias = 0x2b;
2970 conv = 0x7f;
2971 filt = 0xee;
2972 }
2973 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
2974 for (core = 0; core < 2; core++) {
2975 if (core == 0) {
2976 b43_radio_write(dev, 0x5F, bias);
2977 b43_radio_write(dev, 0x64, conv);
2978 b43_radio_write(dev, 0x66, filt);
2979 } else {
2980 b43_radio_write(dev, 0xE8, bias);
2981 b43_radio_write(dev, 0xE9, conv);
2982 b43_radio_write(dev, 0xEB, filt);
2983 }
2984 }
2985 }
2986 }
2987
2988 if (b43_nphy_ipa(dev)) {
2989 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
2990 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2991 phy->radio_rev == 6) {
2992 for (core = 0; core < 2; core++) {
2993 if (core == 0)
2994 b43_radio_write(dev, 0x51,
2995 0x7f);
2996 else
2997 b43_radio_write(dev, 0xd6,
2998 0x7f);
2999 }
3000 }
3001 switch (phy->radio_rev) {
3002 case 3:
3003 for (core = 0; core < 2; core++) {
3004 if (core == 0) {
3005 b43_radio_write(dev, 0x64,
3006 0x13);
3007 b43_radio_write(dev, 0x5F,
3008 0x1F);
3009 b43_radio_write(dev, 0x66,
3010 0xEE);
3011 b43_radio_write(dev, 0x59,
3012 0x8A);
3013 b43_radio_write(dev, 0x80,
3014 0x3E);
3015 } else {
3016 b43_radio_write(dev, 0x69,
3017 0x13);
3018 b43_radio_write(dev, 0xE8,
3019 0x1F);
3020 b43_radio_write(dev, 0xEB,
3021 0xEE);
3022 b43_radio_write(dev, 0xDE,
3023 0x8A);
3024 b43_radio_write(dev, 0x105,
3025 0x3E);
3026 }
3027 }
3028 break;
3029 case 7:
3030 case 8:
3031 if (!b43_is_40mhz(dev)) {
3032 b43_radio_write(dev, 0x5F, 0x14);
3033 b43_radio_write(dev, 0xE8, 0x12);
3034 } else {
3035 b43_radio_write(dev, 0x5F, 0x16);
3036 b43_radio_write(dev, 0xE8, 0x16);
3037 }
3038 break;
3039 case 14:
3040 for (core = 0; core < 2; core++) {
3041 int o = core ? 0x85 : 0;
3042
3043 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13);
3044 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21);
3045 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff);
3046 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88);
3047 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23);
3048 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16);
3049 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e);
3050 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10);
3051 }
3052 break;
3053 }
3054 } else {
3055 u16 freq = phy->chandef->chan->center_freq;
3056 if ((freq >= 5180 && freq <= 5230) ||
3057 (freq >= 5745 && freq <= 5805)) {
3058 b43_radio_write(dev, 0x7D, 0xFF);
3059 b43_radio_write(dev, 0xFE, 0xFF);
3060 }
3061 }
3062 } else {
3063 if (phy->radio_rev != 5) {
3064 for (core = 0; core < 2; core++) {
3065 if (core == 0) {
3066 b43_radio_write(dev, 0x5c, 0x61);
3067 b43_radio_write(dev, 0x51, 0x70);
3068 } else {
3069 b43_radio_write(dev, 0xe1, 0x61);
3070 b43_radio_write(dev, 0xd6, 0x70);
3071 }
3072 }
3073 }
3074 }
3075
3076 if (phy->radio_rev == 4) {
3077 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
3078 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
3079 for (core = 0; core < 2; core++) {
3080 if (core == 0) {
3081 b43_radio_write(dev, 0x1a1, 0x00);
3082 b43_radio_write(dev, 0x1a2, 0x3f);
3083 b43_radio_write(dev, 0x1a6, 0x3f);
3084 } else {
3085 b43_radio_write(dev, 0x1a7, 0x00);
3086 b43_radio_write(dev, 0x1ab, 0x3f);
3087 b43_radio_write(dev, 0x1ac, 0x3f);
3088 }
3089 }
3090 } else {
3091 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
3092 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
3093 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
3094 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
3095
3096 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
3097 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
3098 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
3099 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
3100 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0);
3101 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0);
3102
3103 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
3104 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
3105 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
3106 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
3107 }
3108
3109 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
3110
3111 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
3112 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146);
3113 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
3114 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133);
3115 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146);
3116 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
3117 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
3118
3119 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl);
3120 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
3121 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl);
3122
3123 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl);
3124 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
3125 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl);
3126
3127 b43_nphy_gain_ctl_workarounds(dev);
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139 }
3140
3141 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
3142 {
3143 struct b43_phy_n *nphy = dev->phy.n;
3144 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3145
3146
3147 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
3148 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
3149
3150 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
3151 0x1F };
3152 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
3153 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
3154 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
3155
3156 u16 vmids[5][4] = {
3157 { 0xa2, 0xb4, 0xb4, 0x89, },
3158 { 0xb4, 0xb4, 0xb4, 0x24, },
3159 { 0xa2, 0xb4, 0xb4, 0x74, },
3160 { 0xa2, 0xb4, 0xb4, 0x270, },
3161 { 0xa2, 0xb4, 0xb4, 0x00, },
3162 };
3163 u16 gains[5][4] = {
3164 { 0x02, 0x02, 0x02, 0x00, },
3165 { 0x02, 0x02, 0x02, 0x02, },
3166 { 0x02, 0x02, 0x02, 0x04, },
3167 { 0x02, 0x02, 0x02, 0x00, },
3168 { 0x02, 0x02, 0x02, 0x00, },
3169 };
3170 u16 *vmid, *gain;
3171
3172 u8 pdet_range;
3173 u16 tmp16;
3174 u32 tmp32;
3175
3176 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
3177 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
3178
3179 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
3180 tmp32 &= 0xffffff;
3181 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
3182
3183 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
3184 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
3185 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
3186 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
3187 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
3188 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
3189
3190 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
3191 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
3192
3193
3194 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
3195 ARRAY_SIZE(tx2rx_events));
3196
3197
3198 if (b43_nphy_ipa(dev))
3199 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
3200 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
3201 if (nphy->hw_phyrxchain != 3 &&
3202 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
3203 if (b43_nphy_ipa(dev)) {
3204 rx2tx_delays[5] = 59;
3205 rx2tx_delays[6] = 1;
3206 rx2tx_events[7] = 0x1F;
3207 }
3208 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
3209 ARRAY_SIZE(rx2tx_events));
3210 }
3211
3212 tmp16 = (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ?
3213 0x2 : 0x9C40;
3214 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
3215
3216 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
3217
3218 if (!b43_is_40mhz(dev)) {
3219 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
3220 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
3221 } else {
3222 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
3223 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
3224 }
3225
3226 b43_nphy_gain_ctl_workarounds(dev);
3227
3228 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
3229 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
3230
3231 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
3232 pdet_range = sprom->fem.ghz2.pdet_range;
3233 else
3234 pdet_range = sprom->fem.ghz5.pdet_range;
3235 vmid = vmids[min_t(u16, pdet_range, 4)];
3236 gain = gains[min_t(u16, pdet_range, 4)];
3237 switch (pdet_range) {
3238 case 3:
3239 if (!(dev->phy.rev >= 4 &&
3240 b43_current_band(dev->wl) == NL80211_BAND_2GHZ))
3241 break;
3242
3243 case 0:
3244 case 1:
3245 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3246 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3247 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3248 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3249 break;
3250 case 2:
3251 if (dev->phy.rev >= 6) {
3252 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
3253 vmid[3] = 0x94;
3254 else
3255 vmid[3] = 0x8e;
3256 gain[3] = 3;
3257 } else if (dev->phy.rev == 5) {
3258 vmid[3] = 0x84;
3259 gain[3] = 2;
3260 }
3261 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3262 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3263 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3264 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3265 break;
3266 case 4:
3267 case 5:
3268 if (b43_current_band(dev->wl) != NL80211_BAND_2GHZ) {
3269 if (pdet_range == 4) {
3270 vmid[3] = 0x8e;
3271 tmp16 = 0x96;
3272 gain[3] = 0x2;
3273 } else {
3274 vmid[3] = 0x89;
3275 tmp16 = 0x89;
3276 gain[3] = 0;
3277 }
3278 } else {
3279 if (pdet_range == 4) {
3280 vmid[3] = 0x89;
3281 tmp16 = 0x8b;
3282 gain[3] = 0x2;
3283 } else {
3284 vmid[3] = 0x74;
3285 tmp16 = 0x70;
3286 gain[3] = 0;
3287 }
3288 }
3289 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
3290 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
3291 vmid[3] = tmp16;
3292 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
3293 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
3294 break;
3295 }
3296
3297 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3298 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3299 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3300 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3301 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3302 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3303 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3304 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3305 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3306 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3307 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3308 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3309
3310
3311
3312 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
3313 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ||
3314 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
3315 b43_current_band(dev->wl) == NL80211_BAND_2GHZ))
3316 tmp32 = 0x00088888;
3317 else
3318 tmp32 = 0x88888888;
3319 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
3320 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
3321 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
3322
3323 if (dev->phy.rev == 4 &&
3324 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
3325 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
3326 0x70);
3327 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
3328 0x70);
3329 }
3330
3331
3332 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
3333 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
3334 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
3335 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
3336 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
3337 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
3338 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
3339 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
3340 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
3341 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
3342 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
3343 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
3344
3345 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
3346 ;
3347 }
3348
3349 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
3350 {
3351 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3352 struct b43_phy *phy = &dev->phy;
3353 struct b43_phy_n *nphy = phy->n;
3354
3355 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
3356 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
3357
3358 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
3359 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
3360
3361 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3362 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
3363 delays1[0] = 0x1;
3364 delays1[5] = 0x14;
3365 }
3366
3367 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ &&
3368 nphy->band5g_pwrgain) {
3369 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
3370 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
3371 } else {
3372 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
3373 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
3374 }
3375
3376 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
3377 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
3378 if (dev->phy.rev < 3) {
3379 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
3380 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
3381 }
3382
3383 if (dev->phy.rev < 2) {
3384 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
3385 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
3386 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
3387 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
3388 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
3389 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
3390 }
3391
3392 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3393 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3394 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3395 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3396
3397 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
3398 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
3399
3400 b43_nphy_gain_ctl_workarounds(dev);
3401
3402 if (dev->phy.rev < 2) {
3403 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
3404 b43_hf_write(dev, b43_hf_read(dev) |
3405 B43_HF_MLADVW);
3406 } else if (dev->phy.rev == 2) {
3407 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
3408 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
3409 }
3410
3411 if (dev->phy.rev < 2)
3412 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
3413 ~B43_NPHY_SCRAM_SIGCTL_SCM);
3414
3415
3416 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
3417 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
3418 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
3419 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
3420 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
3421 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
3422
3423 if (dev->phy.rev < 3) {
3424 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
3425 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
3426 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
3427 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
3428 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
3429 }
3430
3431 if (dev->phy.rev == 2)
3432 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
3433 B43_NPHY_FINERX2_CGC_DECGC);
3434 }
3435
3436
3437 static void b43_nphy_workarounds(struct b43_wldev *dev)
3438 {
3439 struct b43_phy *phy = &dev->phy;
3440 struct b43_phy_n *nphy = phy->n;
3441
3442 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
3443 b43_nphy_classifier(dev, 1, 0);
3444 else
3445 b43_nphy_classifier(dev, 1, 1);
3446
3447 if (nphy->hang_avoid)
3448 b43_nphy_stay_in_carrier_search(dev, 1);
3449
3450 b43_phy_set(dev, B43_NPHY_IQFLIP,
3451 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
3452
3453
3454 if (dev->phy.rev >= 7)
3455 b43_nphy_workarounds_rev7plus(dev);
3456 else if (dev->phy.rev >= 3)
3457 b43_nphy_workarounds_rev3plus(dev);
3458 else
3459 b43_nphy_workarounds_rev1_2(dev);
3460
3461 if (nphy->hang_avoid)
3462 b43_nphy_stay_in_carrier_search(dev, 0);
3463 }
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
3474 bool iqmode, bool dac_test, bool modify_bbmult)
3475 {
3476 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
3477 if (samp == 0)
3478 return -1;
3479 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
3480 modify_bbmult);
3481 return 0;
3482 }
3483
3484
3485 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
3486 {
3487 struct b43_phy_n *nphy = dev->phy.n;
3488
3489 bool override = false;
3490 u16 chain = 0x33;
3491
3492 if (nphy->txrx_chain == 0) {
3493 chain = 0x11;
3494 override = true;
3495 } else if (nphy->txrx_chain == 1) {
3496 chain = 0x22;
3497 override = true;
3498 }
3499
3500 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3501 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
3502 chain);
3503
3504 if (override)
3505 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
3506 B43_NPHY_RFSEQMODE_CAOVER);
3507 else
3508 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3509 ~B43_NPHY_RFSEQMODE_CAOVER);
3510 }
3511
3512
3513 static void b43_nphy_stop_playback(struct b43_wldev *dev)
3514 {
3515 struct b43_phy *phy = &dev->phy;
3516 struct b43_phy_n *nphy = dev->phy.n;
3517 u16 tmp;
3518
3519 if (nphy->hang_avoid)
3520 b43_nphy_stay_in_carrier_search(dev, 1);
3521
3522 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
3523 if (tmp & 0x1)
3524 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
3525 else if (tmp & 0x2)
3526 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3527
3528 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3529
3530 if (nphy->bb_mult_save & 0x80000000) {
3531 tmp = nphy->bb_mult_save & 0xFFFF;
3532 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3533 nphy->bb_mult_save = 0;
3534 }
3535
3536 if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) {
3537 if (phy->rev >= 19)
3538 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true,
3539 1);
3540 else
3541 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1);
3542 nphy->lpf_bw_overrode_for_sample_play = false;
3543 }
3544
3545 if (nphy->hang_avoid)
3546 b43_nphy_stay_in_carrier_search(dev, 0);
3547 }
3548
3549
3550 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3551 struct nphy_txgains target,
3552 struct nphy_iqcal_params *params)
3553 {
3554 struct b43_phy *phy = &dev->phy;
3555 int i, j, indx;
3556 u16 gain;
3557
3558 if (dev->phy.rev >= 3) {
3559 params->tx_lpf = target.tx_lpf[core];
3560 params->txgm = target.txgm[core];
3561 params->pga = target.pga[core];
3562 params->pad = target.pad[core];
3563 params->ipa = target.ipa[core];
3564 if (phy->rev >= 19) {
3565
3566 } else if (phy->rev >= 7) {
3567 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15);
3568 } else {
3569 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa);
3570 }
3571 for (j = 0; j < 5; j++)
3572 params->ncorr[j] = 0x79;
3573 } else {
3574 gain = (target.pad[core]) | (target.pga[core] << 4) |
3575 (target.txgm[core] << 8);
3576
3577 indx = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ?
3578 1 : 0;
3579 for (i = 0; i < 9; i++)
3580 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3581 break;
3582 i = min(i, 8);
3583
3584 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3585 params->pga = tbl_iqcal_gainparams[indx][i][2];
3586 params->pad = tbl_iqcal_gainparams[indx][i][3];
3587 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3588 (params->pad << 2);
3589 for (j = 0; j < 4; j++)
3590 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3591 }
3592 }
3593
3594
3595
3596
3597
3598
3599 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3600 {
3601 struct b43_phy *phy = &dev->phy;
3602 struct b43_phy_n *nphy = dev->phy.n;
3603 u8 i;
3604 u16 bmask, val, tmp;
3605 enum nl80211_band band = b43_current_band(dev->wl);
3606
3607 if (nphy->hang_avoid)
3608 b43_nphy_stay_in_carrier_search(dev, 1);
3609
3610 nphy->txpwrctrl = enable;
3611 if (!enable) {
3612 if (dev->phy.rev >= 3 &&
3613 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3614 (B43_NPHY_TXPCTL_CMD_COEFF |
3615 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3616 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3617
3618 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3619 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3620 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3621 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3622 }
3623
3624 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3625 for (i = 0; i < 84; i++)
3626 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3627
3628 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3629 for (i = 0; i < 84; i++)
3630 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3631
3632 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3633 if (dev->phy.rev >= 3)
3634 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3635 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
3636
3637 if (dev->phy.rev >= 3) {
3638 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3639 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3640 } else {
3641 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3642 }
3643
3644 if (dev->phy.rev == 2)
3645 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3646 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3647 else if (dev->phy.rev < 2)
3648 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3649 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
3650
3651 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3652 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
3653 } else {
3654 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3655 nphy->adj_pwr_tbl);
3656 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3657 nphy->adj_pwr_tbl);
3658
3659 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3660 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3661
3662 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3663 if (dev->phy.rev >= 3) {
3664 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3665 if (val)
3666 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3667 }
3668 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
3669
3670 if (band == NL80211_BAND_5GHZ) {
3671 if (phy->rev >= 19) {
3672
3673 } else if (phy->rev >= 7) {
3674 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3675 ~B43_NPHY_TXPCTL_CMD_INIT,
3676 0x32);
3677 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3678 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3679 0x32);
3680 } else {
3681 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3682 ~B43_NPHY_TXPCTL_CMD_INIT,
3683 0x64);
3684 if (phy->rev > 1)
3685 b43_phy_maskset(dev,
3686 B43_NPHY_TXPCTL_INIT,
3687 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3688 0x64);
3689 }
3690 }
3691
3692 if (dev->phy.rev >= 3) {
3693 if (nphy->tx_pwr_idx[0] != 128 &&
3694 nphy->tx_pwr_idx[1] != 128) {
3695
3696 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3697 ~B43_NPHY_TXPCTL_CMD_INIT,
3698 nphy->tx_pwr_idx[0]);
3699 if (dev->phy.rev > 1)
3700 b43_phy_maskset(dev,
3701 B43_NPHY_TXPCTL_INIT,
3702 ~0xff, nphy->tx_pwr_idx[1]);
3703 }
3704 }
3705
3706 if (phy->rev >= 7) {
3707
3708 }
3709
3710 if (dev->phy.rev >= 3) {
3711 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3712 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3713 } else {
3714 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3715 }
3716
3717 if (dev->phy.rev == 2)
3718 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3719 else if (dev->phy.rev < 2)
3720 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3721
3722 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3723 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
3724
3725 if (b43_nphy_ipa(dev)) {
3726 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3727 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
3728 }
3729 }
3730
3731 if (nphy->hang_avoid)
3732 b43_nphy_stay_in_carrier_search(dev, 0);
3733 }
3734
3735
3736 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
3737 {
3738 struct b43_phy *phy = &dev->phy;
3739 struct b43_phy_n *nphy = dev->phy.n;
3740 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3741
3742 u8 txpi[2], bbmult, i;
3743 u16 tmp, radio_gain, dac_gain;
3744 u16 freq = phy->chandef->chan->center_freq;
3745 u32 txgain;
3746
3747
3748 if (nphy->hang_avoid)
3749 b43_nphy_stay_in_carrier_search(dev, 1);
3750
3751
3752 if (dev->phy.rev >= 7) {
3753 txpi[0] = txpi[1] = 30;
3754 } else if (dev->phy.rev >= 3) {
3755 txpi[0] = 40;
3756 txpi[1] = 40;
3757 } else if (sprom->revision < 4) {
3758 txpi[0] = 72;
3759 txpi[1] = 72;
3760 } else {
3761 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
3762 txpi[0] = sprom->txpid2g[0];
3763 txpi[1] = sprom->txpid2g[1];
3764 } else if (freq >= 4900 && freq < 5100) {
3765 txpi[0] = sprom->txpid5gl[0];
3766 txpi[1] = sprom->txpid5gl[1];
3767 } else if (freq >= 5100 && freq < 5500) {
3768 txpi[0] = sprom->txpid5g[0];
3769 txpi[1] = sprom->txpid5g[1];
3770 } else if (freq >= 5500) {
3771 txpi[0] = sprom->txpid5gh[0];
3772 txpi[1] = sprom->txpid5gh[1];
3773 } else {
3774 txpi[0] = 91;
3775 txpi[1] = 91;
3776 }
3777 }
3778 if (dev->phy.rev < 7 &&
3779 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3780 txpi[0] = txpi[1] = 91;
3781
3782
3783
3784
3785
3786
3787
3788
3789 for (i = 0; i < 2; i++) {
3790 const u32 *table = b43_nphy_get_tx_gain_table(dev);
3791
3792 if (!table)
3793 break;
3794 txgain = *(table + txpi[i]);
3795
3796 if (dev->phy.rev >= 3)
3797 radio_gain = (txgain >> 16) & 0x1FFFF;
3798 else
3799 radio_gain = (txgain >> 16) & 0x1FFF;
3800
3801 if (dev->phy.rev >= 7)
3802 dac_gain = (txgain >> 8) & 0x7;
3803 else
3804 dac_gain = (txgain >> 8) & 0x3F;
3805 bbmult = txgain & 0xFF;
3806
3807 if (dev->phy.rev >= 3) {
3808 if (i == 0)
3809 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3810 else
3811 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3812 } else {
3813 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3814 }
3815
3816 if (i == 0)
3817 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3818 else
3819 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3820
3821 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3822
3823 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3824 if (i == 0)
3825 tmp = (tmp & 0x00FF) | (bbmult << 8);
3826 else
3827 tmp = (tmp & 0xFF00) | bbmult;
3828 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3829
3830 if (b43_nphy_ipa(dev)) {
3831 u32 tmp32;
3832 u16 reg = (i == 0) ?
3833 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3834 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3835 576 + txpi[i]));
3836 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3837 b43_phy_set(dev, reg, 0x4);
3838 }
3839 }
3840
3841 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3842
3843 if (nphy->hang_avoid)
3844 b43_nphy_stay_in_carrier_search(dev, 0);
3845 }
3846
3847 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3848 {
3849 struct b43_phy *phy = &dev->phy;
3850
3851 u8 core;
3852 u16 r;
3853
3854 if (phy->rev >= 19) {
3855
3856 } else if (phy->rev >= 7) {
3857 for (core = 0; core < 2; core++) {
3858 r = core ? 0x190 : 0x170;
3859 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
3860 b43_radio_write(dev, r + 0x5, 0x5);
3861 b43_radio_write(dev, r + 0x9, 0xE);
3862 if (phy->rev != 5)
3863 b43_radio_write(dev, r + 0xA, 0);
3864 if (phy->rev != 7)
3865 b43_radio_write(dev, r + 0xB, 1);
3866 else
3867 b43_radio_write(dev, r + 0xB, 0x31);
3868 } else {
3869 b43_radio_write(dev, r + 0x5, 0x9);
3870 b43_radio_write(dev, r + 0x9, 0xC);
3871 b43_radio_write(dev, r + 0xB, 0x0);
3872 if (phy->rev != 5)
3873 b43_radio_write(dev, r + 0xA, 1);
3874 else
3875 b43_radio_write(dev, r + 0xA, 0x31);
3876 }
3877 b43_radio_write(dev, r + 0x6, 0);
3878 b43_radio_write(dev, r + 0x7, 0);
3879 b43_radio_write(dev, r + 0x8, 3);
3880 b43_radio_write(dev, r + 0xC, 0);
3881 }
3882 } else {
3883 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
3884 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3885 else
3886 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3887 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3888 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3889
3890 for (core = 0; core < 2; core++) {
3891 r = core ? B2056_TX1 : B2056_TX0;
3892
3893 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3894 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3895 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3896 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3897 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3898 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3899 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3900 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
3901 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3902 0x5);
3903 if (phy->rev != 5)
3904 b43_radio_write(dev, r | B2056_TX_TSSIA,
3905 0x00);
3906 if (phy->rev >= 5)
3907 b43_radio_write(dev, r | B2056_TX_TSSIG,
3908 0x31);
3909 else
3910 b43_radio_write(dev, r | B2056_TX_TSSIG,
3911 0x11);
3912 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3913 0xE);
3914 } else {
3915 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3916 0x9);
3917 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3918 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3919 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3920 0xC);
3921 }
3922 }
3923 }
3924 }
3925
3926
3927
3928
3929
3930
3931 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3932 {
3933 struct b43_phy *phy = &dev->phy;
3934 struct b43_phy_n *nphy = dev->phy.n;
3935
3936 u32 tmp;
3937 s32 rssi[4] = { };
3938
3939 if (phy->chandef->chan->flags & IEEE80211_CHAN_NO_IR)
3940 return;
3941
3942 if (b43_nphy_ipa(dev))
3943 b43_nphy_ipa_internal_tssi_setup(dev);
3944
3945 if (phy->rev >= 19)
3946 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0);
3947 else if (phy->rev >= 7)
3948 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0);
3949 else if (phy->rev >= 3)
3950 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3951
3952 b43_nphy_stop_playback(dev);
3953 b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3954 udelay(20);
3955 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3956 b43_nphy_stop_playback(dev);
3957
3958 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3959
3960 if (phy->rev >= 19)
3961 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0);
3962 else if (phy->rev >= 7)
3963 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0);
3964 else if (phy->rev >= 3)
3965 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3966
3967 if (phy->rev >= 19) {
3968
3969 return;
3970 } else if (phy->rev >= 3) {
3971 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3972 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3973 } else {
3974 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3975 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3976 }
3977 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3978 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3979 }
3980
3981
3982 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3983 {
3984 struct b43_phy_n *nphy = dev->phy.n;
3985
3986 u8 idx, delta;
3987 u8 i, stf_mode;
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003 for (i = 0; i < 4; i++)
4004 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
4005
4006 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
4007 delta = 0;
4008 switch (stf_mode) {
4009 case 0:
4010 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
4011 idx = 68;
4012 } else {
4013 delta = 1;
4014 idx = b43_is_40mhz(dev) ? 52 : 4;
4015 }
4016 break;
4017 case 1:
4018 idx = b43_is_40mhz(dev) ? 76 : 28;
4019 break;
4020 case 2:
4021 idx = b43_is_40mhz(dev) ? 84 : 36;
4022 break;
4023 case 3:
4024 idx = b43_is_40mhz(dev) ? 92 : 44;
4025 break;
4026 }
4027
4028 for (i = 0; i < 20; i++) {
4029 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
4030 nphy->tx_power_offset[idx];
4031 if (i == 0)
4032 idx += delta;
4033 if (i == 14)
4034 idx += 1 - delta;
4035 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
4036 i == 13)
4037 idx += 1;
4038 }
4039 }
4040 }
4041
4042
4043 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
4044 {
4045 struct b43_phy *phy = &dev->phy;
4046 struct b43_phy_n *nphy = dev->phy.n;
4047 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4048
4049 s16 a1[2], b0[2], b1[2];
4050 u8 idle[2];
4051 u8 ppr_max;
4052 s8 target[2];
4053 s32 num, den, pwr;
4054 u32 regval[64];
4055
4056 u16 freq = phy->chandef->chan->center_freq;
4057 u16 tmp;
4058 u16 r;
4059 u8 i, c;
4060
4061 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
4062 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
4063 b43_read32(dev, B43_MMIO_MACCTL);
4064 udelay(1);
4065 }
4066
4067 if (nphy->hang_avoid)
4068 b43_nphy_stay_in_carrier_search(dev, true);
4069
4070 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
4071 if (dev->phy.rev >= 3)
4072 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
4073 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
4074 else
4075 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
4076 B43_NPHY_TXPCTL_CMD_PCTLEN);
4077
4078 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
4079 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
4080
4081 if (sprom->revision < 4) {
4082 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
4083 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
4084 target[0] = target[1] = 52;
4085 a1[0] = a1[1] = -424;
4086 b0[0] = b0[1] = 5612;
4087 b1[0] = b1[1] = -1393;
4088 } else {
4089 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
4090 for (c = 0; c < 2; c++) {
4091 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
4092 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
4093 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
4094 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
4095 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
4096 }
4097 } else if (freq >= 4900 && freq < 5100) {
4098 for (c = 0; c < 2; c++) {
4099 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4100 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
4101 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
4102 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
4103 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
4104 }
4105 } else if (freq >= 5100 && freq < 5500) {
4106 for (c = 0; c < 2; c++) {
4107 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4108 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
4109 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
4110 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
4111 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
4112 }
4113 } else if (freq >= 5500) {
4114 for (c = 0; c < 2; c++) {
4115 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
4116 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
4117 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
4118 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
4119 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
4120 }
4121 } else {
4122 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
4123 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
4124 target[0] = target[1] = 52;
4125 a1[0] = a1[1] = -424;
4126 b0[0] = b0[1] = 5612;
4127 b1[0] = b1[1] = -1393;
4128 }
4129 }
4130
4131 ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr);
4132 if (ppr_max) {
4133 target[0] = ppr_max;
4134 target[1] = ppr_max;
4135 }
4136
4137 if (dev->phy.rev >= 3) {
4138 if (sprom->fem.ghz2.tssipos)
4139 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
4140 if (dev->phy.rev >= 7) {
4141 for (c = 0; c < 2; c++) {
4142 r = c ? 0x190 : 0x170;
4143 if (b43_nphy_ipa(dev))
4144 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? 0xE : 0xC);
4145 }
4146 } else {
4147 if (b43_nphy_ipa(dev)) {
4148 tmp = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 0xC : 0xE;
4149 b43_radio_write(dev,
4150 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
4151 b43_radio_write(dev,
4152 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
4153 } else {
4154 b43_radio_write(dev,
4155 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
4156 b43_radio_write(dev,
4157 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
4158 }
4159 }
4160 }
4161
4162 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
4163 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
4164 b43_read32(dev, B43_MMIO_MACCTL);
4165 udelay(1);
4166 }
4167
4168 if (phy->rev >= 19) {
4169
4170 } else if (phy->rev >= 7) {
4171 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
4172 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
4173 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
4174 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
4175 } else {
4176 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
4177 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
4178 if (dev->phy.rev > 1)
4179 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
4180 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
4181 }
4182
4183 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
4184 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
4185
4186 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
4187 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
4188 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
4189 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
4190 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
4191 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
4192 B43_NPHY_TXPCTL_ITSSI_BINF);
4193 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
4194 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
4195 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
4196
4197 for (c = 0; c < 2; c++) {
4198 for (i = 0; i < 64; i++) {
4199 num = 8 * (16 * b0[c] + b1[c] * i);
4200 den = 32768 + a1[c] * i;
4201 pwr = max((4 * num + den / 2) / den, -8);
4202 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
4203 pwr = max(pwr, target[c] + 1);
4204 regval[i] = pwr;
4205 }
4206 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
4207 }
4208
4209 b43_nphy_tx_prepare_adjusted_power_table(dev);
4210 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
4211 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
4212
4213 if (nphy->hang_avoid)
4214 b43_nphy_stay_in_carrier_search(dev, false);
4215 }
4216
4217 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
4218 {
4219 struct b43_phy *phy = &dev->phy;
4220
4221 const u32 *table = NULL;
4222 u32 rfpwr_offset;
4223 u8 pga_gain, pad_gain;
4224 int i;
4225 const s16 *uninitialized_var(rf_pwr_offset_table);
4226
4227 table = b43_nphy_get_tx_gain_table(dev);
4228 if (!table)
4229 return;
4230
4231 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
4232 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
4233
4234 if (phy->rev < 3)
4235 return;
4236
4237 #if 0
4238 nphy->gmval = (table[0] >> 16) & 0x7000;
4239 #endif
4240
4241 if (phy->rev >= 19) {
4242 return;
4243 } else if (phy->rev >= 7) {
4244 rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev);
4245 if (!rf_pwr_offset_table)
4246 return;
4247
4248 return;
4249 }
4250
4251 for (i = 0; i < 128; i++) {
4252 if (phy->rev >= 19) {
4253
4254 return;
4255 } else if (phy->rev >= 7) {
4256 pga_gain = (table[i] >> 24) & 0xf;
4257 pad_gain = (table[i] >> 19) & 0x1f;
4258 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
4259 rfpwr_offset = rf_pwr_offset_table[pad_gain];
4260 else
4261 rfpwr_offset = rf_pwr_offset_table[pga_gain];
4262 } else {
4263 pga_gain = (table[i] >> 24) & 0xF;
4264 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
4265 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
4266 else
4267 rfpwr_offset = 0;
4268 }
4269
4270 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset);
4271 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset);
4272 }
4273 }
4274
4275
4276 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
4277 {
4278 struct b43_phy_n *nphy = dev->phy.n;
4279 enum nl80211_band band;
4280 u16 tmp;
4281
4282 if (!enable) {
4283 nphy->rfctrl_intc1_save = b43_phy_read(dev,
4284 B43_NPHY_RFCTL_INTC1);
4285 nphy->rfctrl_intc2_save = b43_phy_read(dev,
4286 B43_NPHY_RFCTL_INTC2);
4287 band = b43_current_band(dev->wl);
4288 if (dev->phy.rev >= 7) {
4289 tmp = 0x1480;
4290 } else if (dev->phy.rev >= 3) {
4291 if (band == NL80211_BAND_5GHZ)
4292 tmp = 0x600;
4293 else
4294 tmp = 0x480;
4295 } else {
4296 if (band == NL80211_BAND_5GHZ)
4297 tmp = 0x180;
4298 else
4299 tmp = 0x120;
4300 }
4301 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4302 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4303 } else {
4304 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
4305 nphy->rfctrl_intc1_save);
4306 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
4307 nphy->rfctrl_intc2_save);
4308 }
4309 }
4310
4311
4312
4313
4314
4315 static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev)
4316 {
4317 u16 tmp;
4318
4319 if (dev->phy.rev < 3 || dev->phy.rev >= 7)
4320 return;
4321
4322 if (b43_nphy_ipa(dev))
4323 tmp = b43_is_40mhz(dev) ? 5 : 4;
4324 else
4325 tmp = b43_is_40mhz(dev) ? 3 : 1;
4326 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
4327 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
4328
4329 if (b43_nphy_ipa(dev)) {
4330 tmp = b43_is_40mhz(dev) ? 4 : 1;
4331 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
4332 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
4333 }
4334 }
4335
4336
4337 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
4338 u16 samps, u8 time, bool wait)
4339 {
4340 int i;
4341 u16 tmp;
4342
4343 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
4344 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
4345 if (wait)
4346 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
4347 else
4348 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
4349
4350 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
4351
4352 for (i = 1000; i; i--) {
4353 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
4354 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
4355 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
4356 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
4357 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
4358 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
4359 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
4360 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
4361
4362 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
4363 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
4364 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
4365 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
4366 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
4367 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
4368 return;
4369 }
4370 udelay(10);
4371 }
4372 memset(est, 0, sizeof(*est));
4373 }
4374
4375
4376 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
4377 struct b43_phy_n_iq_comp *pcomp)
4378 {
4379 if (write) {
4380 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
4381 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
4382 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
4383 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
4384 } else {
4385 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
4386 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
4387 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
4388 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
4389 }
4390 }
4391
4392 #if 0
4393
4394
4395 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4396 {
4397 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4398
4399 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4400 if (core == 0) {
4401 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4402 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4403 } else {
4404 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4405 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4406 }
4407 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4408 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4409 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4410 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4411 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4412 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4413 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4414 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4415 }
4416
4417
4418 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4419 {
4420 u8 rxval, txval;
4421 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4422
4423 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4424 if (core == 0) {
4425 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4426 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4427 } else {
4428 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4429 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4430 }
4431 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4432 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4433 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4434 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4435 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4436 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4437 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4438 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4439
4440 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4441 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4442
4443 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4444 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4445 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4446 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4447 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
4448 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4449 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
4450 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4451 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
4452
4453 if (core == 0) {
4454 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4455 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4456 } else {
4457 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4458 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4459 }
4460
4461 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4462 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4463 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4464
4465 if (core == 0) {
4466 rxval = 1;
4467 txval = 8;
4468 } else {
4469 rxval = 4;
4470 txval = 2;
4471 }
4472 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4473 core + 1);
4474 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4475 2 - core);
4476 }
4477 #endif
4478
4479
4480 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
4481 {
4482 int i;
4483 s32 iq;
4484 u32 ii;
4485 u32 qq;
4486 int iq_nbits, qq_nbits;
4487 int arsh, brsh;
4488 u16 tmp, a, b;
4489
4490 struct nphy_iq_est est;
4491 struct b43_phy_n_iq_comp old;
4492 struct b43_phy_n_iq_comp new = { };
4493 bool error = false;
4494
4495 if (mask == 0)
4496 return;
4497
4498 b43_nphy_rx_iq_coeffs(dev, false, &old);
4499 b43_nphy_rx_iq_coeffs(dev, true, &new);
4500 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
4501 new = old;
4502
4503 for (i = 0; i < 2; i++) {
4504 if (i == 0 && (mask & 1)) {
4505 iq = est.iq0_prod;
4506 ii = est.i0_pwr;
4507 qq = est.q0_pwr;
4508 } else if (i == 1 && (mask & 2)) {
4509 iq = est.iq1_prod;
4510 ii = est.i1_pwr;
4511 qq = est.q1_pwr;
4512 } else {
4513 continue;
4514 }
4515
4516 if (ii + qq < 2) {
4517 error = true;
4518 break;
4519 }
4520
4521 iq_nbits = fls(abs(iq));
4522 qq_nbits = fls(qq);
4523
4524 arsh = iq_nbits - 20;
4525 if (arsh >= 0) {
4526 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
4527 tmp = ii >> arsh;
4528 } else {
4529 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
4530 tmp = ii << -arsh;
4531 }
4532 if (tmp == 0) {
4533 error = true;
4534 break;
4535 }
4536 a /= tmp;
4537
4538 brsh = qq_nbits - 11;
4539 if (brsh >= 0) {
4540 b = (qq << (31 - qq_nbits));
4541 tmp = ii >> brsh;
4542 } else {
4543 b = (qq << (31 - qq_nbits));
4544 tmp = ii << -brsh;
4545 }
4546 if (tmp == 0) {
4547 error = true;
4548 break;
4549 }
4550 b = int_sqrt(b / tmp - a * a) - (1 << 10);
4551
4552 if (i == 0 && (mask & 0x1)) {
4553 if (dev->phy.rev >= 3) {
4554 new.a0 = a & 0x3FF;
4555 new.b0 = b & 0x3FF;
4556 } else {
4557 new.a0 = b & 0x3FF;
4558 new.b0 = a & 0x3FF;
4559 }
4560 } else if (i == 1 && (mask & 0x2)) {
4561 if (dev->phy.rev >= 3) {
4562 new.a1 = a & 0x3FF;
4563 new.b1 = b & 0x3FF;
4564 } else {
4565 new.a1 = b & 0x3FF;
4566 new.b1 = a & 0x3FF;
4567 }
4568 }
4569 }
4570
4571 if (error)
4572 new = old;
4573
4574 b43_nphy_rx_iq_coeffs(dev, true, &new);
4575 }
4576
4577
4578 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
4579 {
4580 u16 array[4];
4581 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
4582
4583 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
4584 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
4585 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
4586 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
4587 }
4588
4589
4590 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
4591 {
4592 struct b43_phy_n *nphy = dev->phy.n;
4593
4594 u8 channel = dev->phy.channel;
4595 int tone[2] = { 57, 58 };
4596 u32 noise[2] = { 0x3FF, 0x3FF };
4597
4598 B43_WARN_ON(dev->phy.rev < 3);
4599
4600 if (nphy->hang_avoid)
4601 b43_nphy_stay_in_carrier_search(dev, 1);
4602
4603 if (nphy->gband_spurwar_en) {
4604
4605 if (channel == 11 && b43_is_40mhz(dev))
4606 ;
4607 else
4608 ;
4609
4610 }
4611
4612 if (nphy->aband_spurwar_en) {
4613 if (channel == 54) {
4614 tone[0] = 0x20;
4615 noise[0] = 0x25F;
4616 } else if (channel == 38 || channel == 102 || channel == 118) {
4617 if (0 ) {
4618 tone[0] = 0x20;
4619 noise[0] = 0x21F;
4620 } else {
4621 tone[0] = 0;
4622 noise[0] = 0;
4623 }
4624 } else if (channel == 134) {
4625 tone[0] = 0x20;
4626 noise[0] = 0x21F;
4627 } else if (channel == 151) {
4628 tone[0] = 0x10;
4629 noise[0] = 0x23F;
4630 } else if (channel == 153 || channel == 161) {
4631 tone[0] = 0x30;
4632 noise[0] = 0x23F;
4633 } else {
4634 tone[0] = 0;
4635 noise[0] = 0;
4636 }
4637
4638 if (!tone[0] && !noise[0])
4639 ;
4640 else
4641 ;
4642 }
4643
4644 if (nphy->hang_avoid)
4645 b43_nphy_stay_in_carrier_search(dev, 0);
4646 }
4647
4648
4649 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4650 {
4651 struct b43_phy_n *nphy = dev->phy.n;
4652 int i, j;
4653 u32 tmp;
4654 u32 cur_real, cur_imag, real_part, imag_part;
4655
4656 u16 buffer[7];
4657
4658 if (nphy->hang_avoid)
4659 b43_nphy_stay_in_carrier_search(dev, true);
4660
4661 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4662
4663 for (i = 0; i < 2; i++) {
4664 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4665 (buffer[i * 2 + 1] & 0x3FF);
4666 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4667 (((i + 26) << 10) | 320));
4668 for (j = 0; j < 128; j++) {
4669 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4670 ((tmp >> 16) & 0xFFFF));
4671 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4672 (tmp & 0xFFFF));
4673 }
4674 }
4675
4676 for (i = 0; i < 2; i++) {
4677 tmp = buffer[5 + i];
4678 real_part = (tmp >> 8) & 0xFF;
4679 imag_part = (tmp & 0xFF);
4680 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4681 (((i + 26) << 10) | 448));
4682
4683 if (dev->phy.rev >= 3) {
4684 cur_real = real_part;
4685 cur_imag = imag_part;
4686 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4687 }
4688
4689 for (j = 0; j < 128; j++) {
4690 if (dev->phy.rev < 3) {
4691 cur_real = (real_part * loscale[j] + 128) >> 8;
4692 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4693 tmp = ((cur_real & 0xFF) << 8) |
4694 (cur_imag & 0xFF);
4695 }
4696 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4697 ((tmp >> 16) & 0xFFFF));
4698 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4699 (tmp & 0xFFFF));
4700 }
4701 }
4702
4703 if (dev->phy.rev >= 3) {
4704 b43_shm_write16(dev, B43_SHM_SHARED,
4705 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4706 b43_shm_write16(dev, B43_SHM_SHARED,
4707 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4708 }
4709
4710 if (nphy->hang_avoid)
4711 b43_nphy_stay_in_carrier_search(dev, false);
4712 }
4713
4714
4715
4716
4717
4718 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4719 {
4720 struct b43_phy_n *nphy = dev->phy.n;
4721
4722 u16 *rssical_radio_regs = NULL;
4723 u16 *rssical_phy_regs = NULL;
4724
4725 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
4726 if (!nphy->rssical_chanspec_2G.center_freq)
4727 return;
4728 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4729 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4730 } else {
4731 if (!nphy->rssical_chanspec_5G.center_freq)
4732 return;
4733 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4734 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4735 }
4736
4737 if (dev->phy.rev >= 19) {
4738
4739 } else if (dev->phy.rev >= 7) {
4740 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK,
4741 rssical_radio_regs[0]);
4742 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK,
4743 rssical_radio_regs[1]);
4744 } else {
4745 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4746 rssical_radio_regs[0]);
4747 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4748 rssical_radio_regs[1]);
4749 }
4750
4751 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4752 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4753 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4754 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4755
4756 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4757 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4758 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4759 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4760
4761 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4762 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4763 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4764 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4765 }
4766
4767 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev)
4768 {
4769
4770 }
4771
4772 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev)
4773 {
4774 struct b43_phy *phy = &dev->phy;
4775 struct b43_phy_n *nphy = dev->phy.n;
4776 u16 *save = nphy->tx_rx_cal_radio_saveregs;
4777 int core, off;
4778 u16 r, tmp;
4779
4780 for (core = 0; core < 2; core++) {
4781 r = core ? 0x20 : 0;
4782 off = core * 11;
4783
4784 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER);
4785 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG);
4786 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC);
4787 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM);
4788 save[off + 4] = 0;
4789 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX);
4790 if (phy->radio_rev != 5)
4791 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA);
4792 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG);
4793 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1);
4794
4795 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
4796 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA);
4797 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4798 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
4799 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
4800 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0);
4801 if (nphy->use_int_tx_iq_lo_cal) {
4802 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4);
4803 tmp = true ? 0x31 : 0x21;
4804 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp);
4805 }
4806 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00);
4807 } else {
4808 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6);
4809 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4810 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55);
4811 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0);
4812
4813 if (phy->radio_rev != 5)
4814 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0);
4815 if (nphy->use_int_tx_iq_lo_cal) {
4816 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6);
4817 tmp = true ? 0x31 : 0x21;
4818 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp);
4819 }
4820 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0);
4821 }
4822 }
4823 }
4824
4825
4826 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4827 {
4828 struct b43_phy *phy = &dev->phy;
4829 struct b43_phy_n *nphy = dev->phy.n;
4830 u16 *save = nphy->tx_rx_cal_radio_saveregs;
4831 u16 tmp;
4832 u8 offset, i;
4833
4834 if (phy->rev >= 19) {
4835 b43_nphy_tx_cal_radio_setup_rev19(dev);
4836 } else if (phy->rev >= 7) {
4837 b43_nphy_tx_cal_radio_setup_rev7(dev);
4838 } else if (phy->rev >= 3) {
4839 for (i = 0; i < 2; i++) {
4840 tmp = (i == 0) ? 0x2000 : 0x3000;
4841 offset = i * 11;
4842
4843 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4844 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4845 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4846 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4847 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4848 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4849 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4850 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4851 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4852 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4853 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
4854
4855 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
4856 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4857 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4858 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4859 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4860 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4861 if (nphy->ipa5g_on) {
4862 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4863 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
4864 } else {
4865 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4866 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
4867 }
4868 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4869 } else {
4870 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4871 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4872 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4873 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4874 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4875 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
4876 if (nphy->ipa2g_on) {
4877 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4878 b43_radio_write(dev, tmp | B2055_XOCTL2,
4879 (dev->phy.rev < 5) ? 0x11 : 0x01);
4880 } else {
4881 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4882 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4883 }
4884 }
4885 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4886 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4887 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
4888 }
4889 } else {
4890 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4891 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
4892
4893 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4894 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
4895
4896 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4897 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
4898
4899 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4900 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4901
4902 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4903 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4904
4905 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4906 B43_NPHY_BANDCTL_5GHZ)) {
4907 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4908 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4909 } else {
4910 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4911 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4912 }
4913
4914 if (dev->phy.rev < 2) {
4915 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4916 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4917 } else {
4918 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4919 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4920 }
4921 }
4922 }
4923
4924
4925 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4926 {
4927 struct b43_phy_n *nphy = dev->phy.n;
4928 int i;
4929 u16 scale, entry;
4930
4931 u16 tmp = nphy->txcal_bbmult;
4932 if (core == 0)
4933 tmp >>= 8;
4934 tmp &= 0xff;
4935
4936 for (i = 0; i < 18; i++) {
4937 scale = (ladder_lo[i].percent * tmp) / 100;
4938 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4939 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4940
4941 scale = (ladder_iq[i].percent * tmp) / 100;
4942 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4943 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4944 }
4945 }
4946
4947 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset,
4948 const s16 *filter)
4949 {
4950 int i;
4951
4952 offset = B43_PHY_N(offset);
4953
4954 for (i = 0; i < 15; i++, offset++)
4955 b43_phy_write(dev, offset, filter[i]);
4956 }
4957
4958
4959 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4960 {
4961 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5,
4962 tbl_tx_filter_coef_rev4[2]);
4963 }
4964
4965
4966 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4967 {
4968
4969 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4970 static const s16 dig_filter_phy_rev16[] = {
4971 -375, 136, -407, 208, -1527,
4972 956, 93, 186, 93, 230,
4973 -44, 230, 201, -191, 201,
4974 };
4975 int i;
4976
4977 for (i = 0; i < 3; i++)
4978 b43_nphy_pa_set_tx_dig_filter(dev, offset[i],
4979 tbl_tx_filter_coef_rev4[i]);
4980
4981
4982 if (dev->phy.rev == 16)
4983 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
4984
4985
4986 if (dev->phy.rev == 17) {
4987 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
4988 b43_nphy_pa_set_tx_dig_filter(dev, 0x195,
4989 tbl_tx_filter_coef_rev4[1]);
4990 }
4991
4992 if (b43_is_40mhz(dev)) {
4993 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4994 tbl_tx_filter_coef_rev4[3]);
4995 } else {
4996 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
4997 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4998 tbl_tx_filter_coef_rev4[5]);
4999 if (dev->phy.channel == 14)
5000 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
5001 tbl_tx_filter_coef_rev4[6]);
5002 }
5003 }
5004
5005
5006 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
5007 {
5008 struct b43_phy_n *nphy = dev->phy.n;
5009
5010 u16 curr_gain[2];
5011 struct nphy_txgains target;
5012 const u32 *table = NULL;
5013
5014 if (!nphy->txpwrctrl) {
5015 int i;
5016
5017 if (nphy->hang_avoid)
5018 b43_nphy_stay_in_carrier_search(dev, true);
5019 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
5020 if (nphy->hang_avoid)
5021 b43_nphy_stay_in_carrier_search(dev, false);
5022
5023 for (i = 0; i < 2; ++i) {
5024 if (dev->phy.rev >= 7) {
5025 target.ipa[i] = curr_gain[i] & 0x0007;
5026 target.pad[i] = (curr_gain[i] & 0x00F8) >> 3;
5027 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
5028 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
5029 target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15;
5030 } else if (dev->phy.rev >= 3) {
5031 target.ipa[i] = curr_gain[i] & 0x000F;
5032 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
5033 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
5034 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
5035 } else {
5036 target.ipa[i] = curr_gain[i] & 0x0003;
5037 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
5038 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
5039 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
5040 }
5041 }
5042 } else {
5043 int i;
5044 u16 index[2];
5045 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
5046 B43_NPHY_TXPCTL_STAT_BIDX) >>
5047 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
5048 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
5049 B43_NPHY_TXPCTL_STAT_BIDX) >>
5050 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
5051
5052 for (i = 0; i < 2; ++i) {
5053 table = b43_nphy_get_tx_gain_table(dev);
5054 if (!table)
5055 break;
5056
5057 if (dev->phy.rev >= 7) {
5058 target.ipa[i] = (table[index[i]] >> 16) & 0x7;
5059 target.pad[i] = (table[index[i]] >> 19) & 0x1F;
5060 target.pga[i] = (table[index[i]] >> 24) & 0xF;
5061 target.txgm[i] = (table[index[i]] >> 28) & 0x7;
5062 target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1;
5063 } else if (dev->phy.rev >= 3) {
5064 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
5065 target.pad[i] = (table[index[i]] >> 20) & 0xF;
5066 target.pga[i] = (table[index[i]] >> 24) & 0xF;
5067 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
5068 } else {
5069 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
5070 target.pad[i] = (table[index[i]] >> 18) & 0x3;
5071 target.pga[i] = (table[index[i]] >> 20) & 0x7;
5072 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
5073 }
5074 }
5075 }
5076
5077 return target;
5078 }
5079
5080
5081 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
5082 {
5083 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
5084
5085 if (dev->phy.rev >= 3) {
5086 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
5087 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
5088 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
5089 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
5090 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
5091 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
5092 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
5093 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
5094 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
5095 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
5096 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
5097 b43_nphy_reset_cca(dev);
5098 } else {
5099 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
5100 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
5101 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
5102 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
5103 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
5104 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
5105 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
5106 }
5107 }
5108
5109
5110 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
5111 {
5112 struct b43_phy *phy = &dev->phy;
5113 struct b43_phy_n *nphy = dev->phy.n;
5114 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
5115 u16 tmp;
5116
5117 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
5118 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
5119 if (dev->phy.rev >= 3) {
5120 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
5121 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
5122
5123 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
5124 regs[2] = tmp;
5125 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
5126
5127 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5128 regs[3] = tmp;
5129 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
5130
5131 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
5132 b43_phy_mask(dev, B43_NPHY_BBCFG,
5133 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5134
5135 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
5136 regs[5] = tmp;
5137 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
5138
5139 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
5140 regs[6] = tmp;
5141 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
5142 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
5143 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
5144
5145 if (!nphy->use_int_tx_iq_lo_cal)
5146 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
5147 1, 3);
5148 else
5149 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA,
5150 0, 3);
5151 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
5152 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
5153
5154 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
5155 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
5156 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
5157 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
5158
5159 tmp = b43_nphy_read_lpf_ctl(dev, 0);
5160 if (phy->rev >= 19)
5161 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false,
5162 1);
5163 else if (phy->rev >= 7)
5164 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false,
5165 1);
5166
5167 if (nphy->use_int_tx_iq_lo_cal && true ) {
5168 if (phy->rev >= 19) {
5169 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3,
5170 false, 0);
5171 } else if (phy->rev >= 8) {
5172 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3,
5173 false, 0);
5174 } else if (phy->rev == 7) {
5175 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4);
5176 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
5177 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0);
5178 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0);
5179 } else {
5180 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0);
5181 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0);
5182 }
5183 }
5184 }
5185 } else {
5186 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
5187 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
5188 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5189 regs[2] = tmp;
5190 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
5191 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
5192 regs[3] = tmp;
5193 tmp |= 0x2000;
5194 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
5195 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
5196 regs[4] = tmp;
5197 tmp |= 0x2000;
5198 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
5199 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
5200 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
5201 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
5202 tmp = 0x0180;
5203 else
5204 tmp = 0x0120;
5205 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
5206 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
5207 }
5208 }
5209
5210
5211 static void b43_nphy_save_cal(struct b43_wldev *dev)
5212 {
5213 struct b43_phy *phy = &dev->phy;
5214 struct b43_phy_n *nphy = dev->phy.n;
5215
5216 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
5217 u16 *txcal_radio_regs = NULL;
5218 struct b43_chanspec *iqcal_chanspec;
5219 u16 *table = NULL;
5220
5221 if (nphy->hang_avoid)
5222 b43_nphy_stay_in_carrier_search(dev, 1);
5223
5224 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
5225 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
5226 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
5227 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
5228 table = nphy->cal_cache.txcal_coeffs_2G;
5229 } else {
5230 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
5231 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
5232 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
5233 table = nphy->cal_cache.txcal_coeffs_5G;
5234 }
5235
5236 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
5237
5238 if (phy->rev >= 19) {
5239
5240 } else if (phy->rev >= 7) {
5241 txcal_radio_regs[0] = b43_radio_read(dev,
5242 R2057_TX0_LOFT_FINE_I);
5243 txcal_radio_regs[1] = b43_radio_read(dev,
5244 R2057_TX0_LOFT_FINE_Q);
5245 txcal_radio_regs[4] = b43_radio_read(dev,
5246 R2057_TX0_LOFT_COARSE_I);
5247 txcal_radio_regs[5] = b43_radio_read(dev,
5248 R2057_TX0_LOFT_COARSE_Q);
5249 txcal_radio_regs[2] = b43_radio_read(dev,
5250 R2057_TX1_LOFT_FINE_I);
5251 txcal_radio_regs[3] = b43_radio_read(dev,
5252 R2057_TX1_LOFT_FINE_Q);
5253 txcal_radio_regs[6] = b43_radio_read(dev,
5254 R2057_TX1_LOFT_COARSE_I);
5255 txcal_radio_regs[7] = b43_radio_read(dev,
5256 R2057_TX1_LOFT_COARSE_Q);
5257 } else if (phy->rev >= 3) {
5258 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
5259 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
5260 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
5261 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
5262 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
5263 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
5264 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
5265 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
5266 } else {
5267 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
5268 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
5269 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
5270 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
5271 }
5272 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
5273 iqcal_chanspec->channel_type =
5274 cfg80211_get_chandef_type(dev->phy.chandef);
5275 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
5276
5277 if (nphy->hang_avoid)
5278 b43_nphy_stay_in_carrier_search(dev, 0);
5279 }
5280
5281
5282 static void b43_nphy_restore_cal(struct b43_wldev *dev)
5283 {
5284 struct b43_phy *phy = &dev->phy;
5285 struct b43_phy_n *nphy = dev->phy.n;
5286
5287 u16 coef[4];
5288 u16 *loft = NULL;
5289 u16 *table = NULL;
5290
5291 int i;
5292 u16 *txcal_radio_regs = NULL;
5293 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
5294
5295 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
5296 if (!nphy->iqcal_chanspec_2G.center_freq)
5297 return;
5298 table = nphy->cal_cache.txcal_coeffs_2G;
5299 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
5300 } else {
5301 if (!nphy->iqcal_chanspec_5G.center_freq)
5302 return;
5303 table = nphy->cal_cache.txcal_coeffs_5G;
5304 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
5305 }
5306
5307 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
5308
5309 for (i = 0; i < 4; i++) {
5310 if (dev->phy.rev >= 3)
5311 table[i] = coef[i];
5312 else
5313 coef[i] = 0;
5314 }
5315
5316 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
5317 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
5318 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
5319
5320 if (dev->phy.rev < 2)
5321 b43_nphy_tx_iq_workaround(dev);
5322
5323 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
5324 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
5325 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
5326 } else {
5327 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
5328 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
5329 }
5330
5331
5332 if (phy->rev >= 19) {
5333
5334 } else if (phy->rev >= 7) {
5335 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I,
5336 txcal_radio_regs[0]);
5337 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q,
5338 txcal_radio_regs[1]);
5339 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I,
5340 txcal_radio_regs[4]);
5341 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q,
5342 txcal_radio_regs[5]);
5343 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I,
5344 txcal_radio_regs[2]);
5345 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q,
5346 txcal_radio_regs[3]);
5347 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I,
5348 txcal_radio_regs[6]);
5349 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q,
5350 txcal_radio_regs[7]);
5351 } else if (phy->rev >= 3) {
5352 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
5353 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
5354 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
5355 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
5356 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
5357 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
5358 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
5359 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
5360 } else {
5361 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
5362 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
5363 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
5364 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
5365 }
5366 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
5367 }
5368
5369
5370 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
5371 struct nphy_txgains target,
5372 bool full, bool mphase)
5373 {
5374 struct b43_phy *phy = &dev->phy;
5375 struct b43_phy_n *nphy = dev->phy.n;
5376 int i;
5377 int error = 0;
5378 int freq;
5379 bool avoid = false;
5380 u8 length;
5381 u16 tmp, core, type, count, max, numb, last = 0, cmd;
5382 const u16 *table;
5383 bool phy6or5x;
5384
5385 u16 buffer[11];
5386 u16 diq_start = 0;
5387 u16 save[2];
5388 u16 gain[2];
5389 struct nphy_iqcal_params params[2];
5390 bool updated[2] = { };
5391
5392 b43_nphy_stay_in_carrier_search(dev, true);
5393
5394 if (dev->phy.rev >= 4) {
5395 avoid = nphy->hang_avoid;
5396 nphy->hang_avoid = false;
5397 }
5398
5399 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
5400
5401 for (i = 0; i < 2; i++) {
5402 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
5403 gain[i] = params[i].cal_gain;
5404 }
5405
5406 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
5407
5408 b43_nphy_tx_cal_radio_setup(dev);
5409 b43_nphy_tx_cal_phy_setup(dev);
5410
5411 phy6or5x = dev->phy.rev >= 6 ||
5412 (dev->phy.rev == 5 && nphy->ipa2g_on &&
5413 b43_current_band(dev->wl) == NL80211_BAND_2GHZ);
5414 if (phy6or5x) {
5415 if (b43_is_40mhz(dev)) {
5416 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
5417 tbl_tx_iqlo_cal_loft_ladder_40);
5418 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
5419 tbl_tx_iqlo_cal_iqimb_ladder_40);
5420 } else {
5421 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
5422 tbl_tx_iqlo_cal_loft_ladder_20);
5423 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
5424 tbl_tx_iqlo_cal_iqimb_ladder_20);
5425 }
5426 }
5427
5428 if (phy->rev >= 19) {
5429
5430 } else if (phy->rev >= 7) {
5431 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9);
5432 } else {
5433 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
5434 }
5435
5436 if (!b43_is_40mhz(dev))
5437 freq = 2500;
5438 else
5439 freq = 5000;
5440
5441 if (nphy->mphase_cal_phase_id > 2)
5442 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
5443 0xFFFF, 0, true, false, false);
5444 else
5445 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
5446
5447 if (error == 0) {
5448 if (nphy->mphase_cal_phase_id > 2) {
5449 table = nphy->mphase_txcal_bestcoeffs;
5450 length = 11;
5451 if (dev->phy.rev < 3)
5452 length -= 2;
5453 } else {
5454 if (!full && nphy->txiqlocal_coeffsvalid) {
5455 table = nphy->txiqlocal_bestc;
5456 length = 11;
5457 if (dev->phy.rev < 3)
5458 length -= 2;
5459 } else {
5460 full = true;
5461 if (dev->phy.rev >= 3) {
5462 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
5463 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
5464 } else {
5465 table = tbl_tx_iqlo_cal_startcoefs;
5466 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
5467 }
5468 }
5469 }
5470
5471 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
5472
5473 if (full) {
5474 if (dev->phy.rev >= 3)
5475 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
5476 else
5477 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
5478 } else {
5479 if (dev->phy.rev >= 3)
5480 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
5481 else
5482 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
5483 }
5484
5485 if (mphase) {
5486 count = nphy->mphase_txcal_cmdidx;
5487 numb = min(max,
5488 (u16)(count + nphy->mphase_txcal_numcmds));
5489 } else {
5490 count = 0;
5491 numb = max;
5492 }
5493
5494 for (; count < numb; count++) {
5495 if (full) {
5496 if (dev->phy.rev >= 3)
5497 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
5498 else
5499 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
5500 } else {
5501 if (dev->phy.rev >= 3)
5502 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
5503 else
5504 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
5505 }
5506
5507 core = (cmd & 0x3000) >> 12;
5508 type = (cmd & 0x0F00) >> 8;
5509
5510 if (phy6or5x && updated[core] == 0) {
5511 b43_nphy_update_tx_cal_ladder(dev, core);
5512 updated[core] = true;
5513 }
5514
5515 tmp = (params[core].ncorr[type] << 8) | 0x66;
5516 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
5517
5518 if (type == 1 || type == 3 || type == 4) {
5519 buffer[0] = b43_ntab_read(dev,
5520 B43_NTAB16(15, 69 + core));
5521 diq_start = buffer[0];
5522 buffer[0] = 0;
5523 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
5524 0);
5525 }
5526
5527 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
5528 for (i = 0; i < 2000; i++) {
5529 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
5530 if (tmp & 0xC000)
5531 break;
5532 udelay(10);
5533 }
5534
5535 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5536 buffer);
5537 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
5538 buffer);
5539
5540 if (type == 1 || type == 3 || type == 4)
5541 buffer[0] = diq_start;
5542 }
5543
5544 if (mphase)
5545 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
5546
5547 last = (dev->phy.rev < 3) ? 6 : 7;
5548
5549 if (!mphase || nphy->mphase_cal_phase_id == last) {
5550 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
5551 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
5552 if (dev->phy.rev < 3) {
5553 buffer[0] = 0;
5554 buffer[1] = 0;
5555 buffer[2] = 0;
5556 buffer[3] = 0;
5557 }
5558 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5559 buffer);
5560 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
5561 buffer);
5562 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5563 buffer);
5564 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5565 buffer);
5566 length = 11;
5567 if (dev->phy.rev < 3)
5568 length -= 2;
5569 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5570 nphy->txiqlocal_bestc);
5571 nphy->txiqlocal_coeffsvalid = true;
5572 nphy->txiqlocal_chanspec.center_freq =
5573 phy->chandef->chan->center_freq;
5574 nphy->txiqlocal_chanspec.channel_type =
5575 cfg80211_get_chandef_type(phy->chandef);
5576 } else {
5577 length = 11;
5578 if (dev->phy.rev < 3)
5579 length -= 2;
5580 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5581 nphy->mphase_txcal_bestcoeffs);
5582 }
5583
5584 b43_nphy_stop_playback(dev);
5585 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
5586 }
5587
5588 b43_nphy_tx_cal_phy_cleanup(dev);
5589 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
5590
5591 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
5592 b43_nphy_tx_iq_workaround(dev);
5593
5594 if (dev->phy.rev >= 4)
5595 nphy->hang_avoid = avoid;
5596
5597 b43_nphy_stay_in_carrier_search(dev, false);
5598
5599 return error;
5600 }
5601
5602
5603 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
5604 {
5605 struct b43_phy_n *nphy = dev->phy.n;
5606 u8 i;
5607 u16 buffer[7];
5608 bool equal = true;
5609
5610 if (!nphy->txiqlocal_coeffsvalid ||
5611 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
5612 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
5613 return;
5614
5615 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
5616 for (i = 0; i < 4; i++) {
5617 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
5618 equal = false;
5619 break;
5620 }
5621 }
5622
5623 if (!equal) {
5624 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
5625 nphy->txiqlocal_bestc);
5626 for (i = 0; i < 4; i++)
5627 buffer[i] = 0;
5628 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5629 buffer);
5630 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5631 &nphy->txiqlocal_bestc[5]);
5632 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5633 &nphy->txiqlocal_bestc[5]);
5634 }
5635 }
5636
5637
5638 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
5639 struct nphy_txgains target, u8 type, bool debug)
5640 {
5641 struct b43_phy_n *nphy = dev->phy.n;
5642 int i, j, index;
5643 u8 rfctl[2];
5644 u8 afectl_core;
5645 u16 tmp[6];
5646 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
5647 u32 real, imag;
5648 enum nl80211_band band;
5649
5650 u8 use;
5651 u16 cur_hpf;
5652 u16 lna[3] = { 3, 3, 1 };
5653 u16 hpf1[3] = { 7, 2, 0 };
5654 u16 hpf2[3] = { 2, 0, 0 };
5655 u32 power[3] = { };
5656 u16 gain_save[2];
5657 u16 cal_gain[2];
5658 struct nphy_iqcal_params cal_params[2];
5659 struct nphy_iq_est est;
5660 int ret = 0;
5661 bool playtone = true;
5662 int desired = 13;
5663
5664 b43_nphy_stay_in_carrier_search(dev, 1);
5665
5666 if (dev->phy.rev < 2)
5667 b43_nphy_reapply_tx_cal_coeffs(dev);
5668 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5669 for (i = 0; i < 2; i++) {
5670 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
5671 cal_gain[i] = cal_params[i].cal_gain;
5672 }
5673 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
5674
5675 for (i = 0; i < 2; i++) {
5676 if (i == 0) {
5677 rfctl[0] = B43_NPHY_RFCTL_INTC1;
5678 rfctl[1] = B43_NPHY_RFCTL_INTC2;
5679 afectl_core = B43_NPHY_AFECTL_C1;
5680 } else {
5681 rfctl[0] = B43_NPHY_RFCTL_INTC2;
5682 rfctl[1] = B43_NPHY_RFCTL_INTC1;
5683 afectl_core = B43_NPHY_AFECTL_C2;
5684 }
5685
5686 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
5687 tmp[2] = b43_phy_read(dev, afectl_core);
5688 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5689 tmp[4] = b43_phy_read(dev, rfctl[0]);
5690 tmp[5] = b43_phy_read(dev, rfctl[1]);
5691
5692 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
5693 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
5694 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
5695 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
5696 (1 - i));
5697 b43_phy_set(dev, afectl_core, 0x0006);
5698 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
5699
5700 band = b43_current_band(dev->wl);
5701
5702 if (nphy->rxcalparams & 0xFF000000) {
5703 if (band == NL80211_BAND_5GHZ)
5704 b43_phy_write(dev, rfctl[0], 0x140);
5705 else
5706 b43_phy_write(dev, rfctl[0], 0x110);
5707 } else {
5708 if (band == NL80211_BAND_5GHZ)
5709 b43_phy_write(dev, rfctl[0], 0x180);
5710 else
5711 b43_phy_write(dev, rfctl[0], 0x120);
5712 }
5713
5714 if (band == NL80211_BAND_5GHZ)
5715 b43_phy_write(dev, rfctl[1], 0x148);
5716 else
5717 b43_phy_write(dev, rfctl[1], 0x114);
5718
5719 if (nphy->rxcalparams & 0x10000) {
5720 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
5721 (i + 1));
5722 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
5723 (2 - i));
5724 }
5725
5726 for (j = 0; j < 4; j++) {
5727 if (j < 3) {
5728 cur_lna = lna[j];
5729 cur_hpf1 = hpf1[j];
5730 cur_hpf2 = hpf2[j];
5731 } else {
5732 if (power[1] > 10000) {
5733 use = 1;
5734 cur_hpf = cur_hpf1;
5735 index = 2;
5736 } else {
5737 if (power[0] > 10000) {
5738 use = 1;
5739 cur_hpf = cur_hpf1;
5740 index = 1;
5741 } else {
5742 index = 0;
5743 use = 2;
5744 cur_hpf = cur_hpf2;
5745 }
5746 }
5747 cur_lna = lna[index];
5748 cur_hpf1 = hpf1[index];
5749 cur_hpf2 = hpf2[index];
5750 cur_hpf += desired - hweight32(power[index]);
5751 cur_hpf = clamp_val(cur_hpf, 0, 10);
5752 if (use == 1)
5753 cur_hpf1 = cur_hpf;
5754 else
5755 cur_hpf2 = cur_hpf;
5756 }
5757
5758 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
5759 (cur_lna << 2));
5760 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
5761 false);
5762 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5763 b43_nphy_stop_playback(dev);
5764
5765 if (playtone) {
5766 ret = b43_nphy_tx_tone(dev, 4000,
5767 (nphy->rxcalparams & 0xFFFF),
5768 false, false, true);
5769 playtone = false;
5770 } else {
5771 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
5772 false, true);
5773 }
5774
5775 if (ret == 0) {
5776 if (j < 3) {
5777 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
5778 false);
5779 if (i == 0) {
5780 real = est.i0_pwr;
5781 imag = est.q0_pwr;
5782 } else {
5783 real = est.i1_pwr;
5784 imag = est.q1_pwr;
5785 }
5786 power[i] = ((real + imag) / 1024) + 1;
5787 } else {
5788 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
5789 }
5790 b43_nphy_stop_playback(dev);
5791 }
5792
5793 if (ret != 0)
5794 break;
5795 }
5796
5797 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5798 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5799 b43_phy_write(dev, rfctl[1], tmp[5]);
5800 b43_phy_write(dev, rfctl[0], tmp[4]);
5801 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5802 b43_phy_write(dev, afectl_core, tmp[2]);
5803 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5804
5805 if (ret != 0)
5806 break;
5807 }
5808
5809 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
5810 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5811 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5812
5813 b43_nphy_stay_in_carrier_search(dev, 0);
5814
5815 return ret;
5816 }
5817
5818 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5819 struct nphy_txgains target, u8 type, bool debug)
5820 {
5821 return -1;
5822 }
5823
5824
5825 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5826 struct nphy_txgains target, u8 type, bool debug)
5827 {
5828 if (dev->phy.rev >= 7)
5829 type = 0;
5830
5831 if (dev->phy.rev >= 3)
5832 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5833 else
5834 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5835 }
5836
5837
5838 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5839 {
5840 struct b43_phy *phy = &dev->phy;
5841 struct b43_phy_n *nphy = phy->n;
5842
5843
5844 nphy->phyrxchain = mask;
5845
5846 if (0 )
5847 return;
5848
5849 b43_mac_suspend(dev);
5850
5851 if (nphy->hang_avoid)
5852 b43_nphy_stay_in_carrier_search(dev, true);
5853
5854 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5855 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5856
5857 if ((mask & 0x3) != 0x3) {
5858 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5859 if (dev->phy.rev >= 3) {
5860
5861 }
5862 } else {
5863 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5864 if (dev->phy.rev >= 3) {
5865
5866 }
5867 }
5868
5869 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5870
5871 if (nphy->hang_avoid)
5872 b43_nphy_stay_in_carrier_search(dev, false);
5873
5874 b43_mac_enable(dev);
5875 }
5876
5877 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
5878 bool ignore_tssi)
5879 {
5880 struct b43_phy *phy = &dev->phy;
5881 struct b43_phy_n *nphy = dev->phy.n;
5882 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5883 struct b43_ppr *ppr = &nphy->tx_pwr_max_ppr;
5884 u8 max;
5885
5886 if (nphy->tx_pwr_last_recalc_freq == channel->center_freq &&
5887 nphy->tx_pwr_last_recalc_limit == phy->desired_txpower)
5888 return B43_TXPWR_RES_DONE;
5889
5890
5891 b43_ppr_clear(dev, ppr);
5892
5893
5894 b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G);
5895
5896
5897 max = INT_TO_Q52(phy->chandef->chan->max_power);
5898 if (phy->desired_txpower)
5899 max = min_t(u8, max, INT_TO_Q52(phy->desired_txpower));
5900 b43_ppr_apply_max(dev, ppr, max);
5901 if (b43_debug(dev, B43_DBG_XMITPOWER))
5902 b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n",
5903 Q52_ARG(b43_ppr_get_max(dev, ppr)));
5904
5905
5906 #if 0
5907
5908 hw_gain = 6;
5909 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
5910 hw_gain += sprom->antenna_gain.a0;
5911 else
5912 hw_gain += sprom->antenna_gain.a1;
5913 b43_ppr_add(dev, ppr, -hw_gain);
5914 #endif
5915
5916
5917 b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8));
5918
5919
5920 b43_mac_suspend(dev);
5921 b43_nphy_tx_power_ctl_setup(dev);
5922 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
5923 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK);
5924 b43_read32(dev, B43_MMIO_MACCTL);
5925 udelay(1);
5926 }
5927 b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl);
5928 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
5929 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0);
5930 b43_mac_enable(dev);
5931
5932 nphy->tx_pwr_last_recalc_freq = channel->center_freq;
5933 nphy->tx_pwr_last_recalc_limit = phy->desired_txpower;
5934
5935 return B43_TXPWR_RES_DONE;
5936 }
5937
5938
5939
5940
5941
5942
5943 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5944 {
5945 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5946
5947 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5948 if (preamble == 1)
5949 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5950 else
5951 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5952
5953 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5954 }
5955
5956
5957 static void b43_nphy_bphy_init(struct b43_wldev *dev)
5958 {
5959 unsigned int i;
5960 u16 val;
5961
5962 val = 0x1E1F;
5963 for (i = 0; i < 16; i++) {
5964 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5965 val -= 0x202;
5966 }
5967 val = 0x3E3F;
5968 for (i = 0; i < 16; i++) {
5969 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5970 val -= 0x202;
5971 }
5972 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5973 }
5974
5975
5976 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5977 {
5978 if (dev->phy.rev >= 7)
5979 return;
5980
5981 if (dev->phy.rev >= 3) {
5982 if (!init)
5983 return;
5984 if (0 ) {
5985 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5986 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5987 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5988 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5989 }
5990 } else {
5991 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5992 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5993
5994 switch (dev->dev->bus_type) {
5995 #ifdef CONFIG_B43_BCMA
5996 case B43_BUS_BCMA:
5997 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5998 0xFC00, 0xFC00);
5999 break;
6000 #endif
6001 #ifdef CONFIG_B43_SSB
6002 case B43_BUS_SSB:
6003 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
6004 0xFC00, 0xFC00);
6005 break;
6006 #endif
6007 }
6008
6009 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
6010 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
6011 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
6012 0);
6013
6014 if (init) {
6015 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
6016 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
6017 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
6018 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
6019 }
6020 }
6021 }
6022
6023
6024 static int b43_phy_initn(struct b43_wldev *dev)
6025 {
6026 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6027 struct b43_phy *phy = &dev->phy;
6028 struct b43_phy_n *nphy = phy->n;
6029 u8 tx_pwr_state;
6030 struct nphy_txgains target;
6031 u16 tmp;
6032 bool do_rssi_cal;
6033
6034 u16 clip[2];
6035 bool do_cal = false;
6036
6037 if ((dev->phy.rev >= 3) &&
6038 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
6039 (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) {
6040 switch (dev->dev->bus_type) {
6041 #ifdef CONFIG_B43_BCMA
6042 case B43_BUS_BCMA:
6043 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
6044 BCMA_CC_CHIPCTL, 0x40);
6045 break;
6046 #endif
6047 #ifdef CONFIG_B43_SSB
6048 case B43_BUS_SSB:
6049 chipco_set32(&dev->dev->sdev->bus->chipco,
6050 SSB_CHIPCO_CHIPCTL, 0x40);
6051 break;
6052 #endif
6053 }
6054 }
6055 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) ||
6056 phy->rev >= 7 ||
6057 (phy->rev >= 5 &&
6058 sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL);
6059 nphy->deaf_count = 0;
6060 b43_nphy_tables_init(dev);
6061 nphy->crsminpwr_adjusted = false;
6062 nphy->noisevars_adjusted = false;
6063
6064
6065 if (dev->phy.rev >= 3) {
6066 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
6067 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
6068 if (phy->rev >= 7) {
6069 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0);
6070 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0);
6071 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0);
6072 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0);
6073 }
6074 if (phy->rev >= 19) {
6075
6076 }
6077
6078 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
6079 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
6080 } else {
6081 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
6082 }
6083 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
6084 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
6085 if (dev->phy.rev < 6) {
6086 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
6087 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
6088 }
6089 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
6090 ~(B43_NPHY_RFSEQMODE_CAOVER |
6091 B43_NPHY_RFSEQMODE_TROVER));
6092 if (dev->phy.rev >= 3)
6093 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
6094 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
6095
6096 if (dev->phy.rev <= 2) {
6097 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
6098 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
6099 ~B43_NPHY_BPHY_CTL3_SCALE,
6100 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
6101 }
6102 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
6103 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
6104
6105 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
6106 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
6107 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
6108 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
6109 else
6110 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
6111 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
6112 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
6113 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
6114
6115 if (phy->rev < 8)
6116 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
6117
6118 b43_nphy_update_txrx_chain(dev);
6119
6120 if (phy->rev < 2) {
6121 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
6122 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
6123 }
6124
6125 if (b43_nphy_ipa(dev)) {
6126 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
6127 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
6128 nphy->papd_epsilon_offset[0] << 7);
6129 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
6130 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
6131 nphy->papd_epsilon_offset[1] << 7);
6132 b43_nphy_int_pa_set_tx_dig_filters(dev);
6133 } else if (phy->rev >= 5) {
6134 b43_nphy_ext_pa_set_tx_dig_filters(dev);
6135 }
6136
6137 b43_nphy_workarounds(dev);
6138
6139
6140 b43_phy_force_clock(dev, 1);
6141 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
6142 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
6143 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
6144 b43_phy_force_clock(dev, 0);
6145
6146 b43_mac_phy_clock_set(dev, true);
6147
6148 if (phy->rev < 7) {
6149 b43_nphy_pa_override(dev, false);
6150 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6151 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
6152 b43_nphy_pa_override(dev, true);
6153 }
6154
6155 b43_nphy_classifier(dev, 0, 0);
6156 b43_nphy_read_clip_detection(dev, clip);
6157 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
6158 b43_nphy_bphy_init(dev);
6159
6160 tx_pwr_state = nphy->txpwrctrl;
6161 b43_nphy_tx_power_ctrl(dev, false);
6162 b43_nphy_tx_power_fix(dev);
6163 b43_nphy_tx_power_ctl_idle_tssi(dev);
6164 b43_nphy_tx_power_ctl_setup(dev);
6165 b43_nphy_tx_gain_table_upload(dev);
6166
6167 if (nphy->phyrxchain != 3)
6168 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
6169 if (nphy->mphase_cal_phase_id > 0)
6170 ;
6171
6172 do_rssi_cal = false;
6173 if (phy->rev >= 3) {
6174 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
6175 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
6176 else
6177 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
6178
6179 if (do_rssi_cal)
6180 b43_nphy_rssi_cal(dev);
6181 else
6182 b43_nphy_restore_rssi_cal(dev);
6183 } else {
6184 b43_nphy_rssi_cal(dev);
6185 }
6186
6187 if (!((nphy->measure_hold & 0x6) != 0)) {
6188 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
6189 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
6190 else
6191 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
6192
6193 if (nphy->mute)
6194 do_cal = false;
6195
6196 if (do_cal) {
6197 target = b43_nphy_get_tx_gains(dev);
6198
6199 if (nphy->antsel_type == 2)
6200 b43_nphy_superswitch_init(dev, true);
6201 if (nphy->perical != 2) {
6202 b43_nphy_rssi_cal(dev);
6203 if (phy->rev >= 3) {
6204 nphy->cal_orig_pwr_idx[0] =
6205 nphy->txpwrindex[0].index_internal;
6206 nphy->cal_orig_pwr_idx[1] =
6207 nphy->txpwrindex[1].index_internal;
6208
6209 target = b43_nphy_get_tx_gains(dev);
6210 }
6211 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
6212 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
6213 b43_nphy_save_cal(dev);
6214 } else if (nphy->mphase_cal_phase_id == 0)
6215 ;
6216 } else {
6217 b43_nphy_restore_cal(dev);
6218 }
6219 }
6220
6221 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
6222 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
6223 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
6224 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
6225 if (phy->rev >= 3 && phy->rev <= 6)
6226 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
6227 b43_nphy_tx_lpf_bw(dev);
6228 if (phy->rev >= 3)
6229 b43_nphy_spur_workaround(dev);
6230
6231 return 0;
6232 }
6233
6234
6235
6236
6237
6238 static void b43_chantab_phy_upload(struct b43_wldev *dev,
6239 const struct b43_phy_n_sfo_cfg *e)
6240 {
6241 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
6242 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
6243 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
6244 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
6245 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
6246 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
6247 }
6248
6249
6250 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
6251 {
6252 switch (dev->dev->bus_type) {
6253 #ifdef CONFIG_B43_BCMA
6254 case B43_BUS_BCMA:
6255 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
6256 avoid);
6257 break;
6258 #endif
6259 #ifdef CONFIG_B43_SSB
6260 case B43_BUS_SSB:
6261 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
6262 avoid);
6263 break;
6264 #endif
6265 }
6266 }
6267
6268
6269 static void b43_nphy_channel_setup(struct b43_wldev *dev,
6270 const struct b43_phy_n_sfo_cfg *e,
6271 struct ieee80211_channel *new_channel)
6272 {
6273 struct b43_phy *phy = &dev->phy;
6274 struct b43_phy_n *nphy = dev->phy.n;
6275 int ch = new_channel->hw_value;
6276 u16 tmp16;
6277
6278 if (new_channel->band == NL80211_BAND_5GHZ) {
6279
6280 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
6281
6282 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
6283 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
6284
6285 b43_phy_set(dev, B43_PHY_B_BBCFG,
6286 B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX);
6287 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
6288 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
6289 } else if (new_channel->band == NL80211_BAND_2GHZ) {
6290 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
6291 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
6292 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
6293
6294 b43_phy_mask(dev, B43_PHY_B_BBCFG,
6295 (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX));
6296 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
6297 }
6298
6299 b43_chantab_phy_upload(dev, e);
6300
6301 if (new_channel->hw_value == 14) {
6302 b43_nphy_classifier(dev, 2, 0);
6303 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
6304 } else {
6305 b43_nphy_classifier(dev, 2, 2);
6306 if (new_channel->band == NL80211_BAND_2GHZ)
6307 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
6308 }
6309
6310 if (!nphy->txpwrctrl)
6311 b43_nphy_tx_power_fix(dev);
6312
6313 if (dev->phy.rev < 3)
6314 b43_nphy_adjust_lna_gain_table(dev);
6315
6316 b43_nphy_tx_lpf_bw(dev);
6317
6318 if (dev->phy.rev >= 3 &&
6319 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
6320 u8 spuravoid = 0;
6321
6322 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
6323 spuravoid = 1;
6324 } else if (phy->rev >= 19) {
6325
6326 } else if (phy->rev >= 18) {
6327
6328 } else if (phy->rev >= 17) {
6329
6330 } else if (phy->rev >= 16) {
6331
6332 } else if (phy->rev >= 7) {
6333 if (!b43_is_40mhz(dev)) {
6334 if (ch == 13 || ch == 14 || ch == 153)
6335 spuravoid = 1;
6336 } else {
6337 if (ch == 54)
6338 spuravoid = 1;
6339 }
6340 } else {
6341 if (!b43_is_40mhz(dev)) {
6342 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
6343 spuravoid = 1;
6344 } else {
6345 if (nphy->aband_spurwar_en &&
6346 (ch == 38 || ch == 102 || ch == 118))
6347 spuravoid = dev->dev->chip_id == 0x4716;
6348 }
6349 }
6350
6351 b43_nphy_pmu_spur_avoid(dev, spuravoid);
6352
6353 b43_mac_switch_freq(dev, spuravoid);
6354
6355 if (dev->phy.rev == 3 || dev->phy.rev == 4)
6356 b43_wireless_core_phy_pll_reset(dev);
6357
6358 if (spuravoid)
6359 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
6360 else
6361 b43_phy_mask(dev, B43_NPHY_BBCFG,
6362 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
6363
6364 b43_nphy_reset_cca(dev);
6365
6366
6367 }
6368
6369 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
6370
6371 if (phy->rev >= 3)
6372 b43_nphy_spur_workaround(dev);
6373 }
6374
6375
6376 static int b43_nphy_set_channel(struct b43_wldev *dev,
6377 struct ieee80211_channel *channel,
6378 enum nl80211_channel_type channel_type)
6379 {
6380 struct b43_phy *phy = &dev->phy;
6381
6382 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
6383 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
6384 const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL;
6385 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
6386
6387 u8 tmp;
6388
6389 if (phy->rev >= 19) {
6390 return -ESRCH;
6391
6392 } else if (phy->rev >= 7) {
6393 r2057_get_chantabent_rev7(dev, channel->center_freq,
6394 &tabent_r7, &tabent_r7_2g);
6395 if (!tabent_r7 && !tabent_r7_2g)
6396 return -ESRCH;
6397 } else if (phy->rev >= 3) {
6398 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
6399 channel->center_freq);
6400 if (!tabent_r3)
6401 return -ESRCH;
6402 } else {
6403 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
6404 channel->hw_value);
6405 if (!tabent_r2)
6406 return -ESRCH;
6407 }
6408
6409
6410
6411 phy->channel = channel->hw_value;
6412
6413 #if 0
6414 if (b43_channel_type_is_40mhz(phy->channel_type) !=
6415 b43_channel_type_is_40mhz(channel_type))
6416 ;
6417 #endif
6418
6419 if (channel_type == NL80211_CHAN_HT40PLUS) {
6420 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20);
6421 if (phy->rev >= 7)
6422 b43_phy_set(dev, 0x310, 0x8000);
6423 } else if (channel_type == NL80211_CHAN_HT40MINUS) {
6424 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20);
6425 if (phy->rev >= 7)
6426 b43_phy_mask(dev, 0x310, (u16)~0x8000);
6427 }
6428
6429 if (phy->rev >= 19) {
6430
6431 } else if (phy->rev >= 7) {
6432 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
6433 &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);
6434
6435 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
6436 tmp = (channel->band == NL80211_BAND_5GHZ) ? 2 : 0;
6437 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp);
6438 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp);
6439 }
6440
6441 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g);
6442 b43_nphy_channel_setup(dev, phy_regs, channel);
6443 } else if (phy->rev >= 3) {
6444 tmp = (channel->band == NL80211_BAND_5GHZ) ? 4 : 0;
6445 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
6446 b43_radio_2056_setup(dev, tabent_r3);
6447 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
6448 } else {
6449 tmp = (channel->band == NL80211_BAND_5GHZ) ? 0x0020 : 0x0050;
6450 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
6451 b43_radio_2055_setup(dev, tabent_r2);
6452 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
6453 }
6454
6455 return 0;
6456 }
6457
6458
6459
6460
6461
6462 static int b43_nphy_op_allocate(struct b43_wldev *dev)
6463 {
6464 struct b43_phy_n *nphy;
6465
6466 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
6467 if (!nphy)
6468 return -ENOMEM;
6469
6470 dev->phy.n = nphy;
6471
6472 return 0;
6473 }
6474
6475 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
6476 {
6477 struct b43_phy *phy = &dev->phy;
6478 struct b43_phy_n *nphy = phy->n;
6479 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6480
6481 memset(nphy, 0, sizeof(*nphy));
6482
6483 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
6484 nphy->spur_avoid = (phy->rev >= 3) ?
6485 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
6486 nphy->gain_boost = true;
6487 nphy->txrx_chain = 2;
6488 nphy->phyrxchain = 3;
6489 nphy->perical = 2;
6490
6491
6492 nphy->tx_pwr_idx[0] = 128;
6493 nphy->tx_pwr_idx[1] = 128;
6494
6495
6496 nphy->txpwrctrl = false;
6497 nphy->pwg_gain_5ghz = false;
6498 if (dev->phy.rev >= 3 ||
6499 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
6500 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
6501 nphy->txpwrctrl = true;
6502 nphy->pwg_gain_5ghz = true;
6503 } else if (sprom->revision >= 4) {
6504 if (dev->phy.rev >= 2 &&
6505 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
6506 nphy->txpwrctrl = true;
6507 #ifdef CONFIG_B43_SSB
6508 if (dev->dev->bus_type == B43_BUS_SSB &&
6509 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
6510 struct pci_dev *pdev =
6511 dev->dev->sdev->bus->host_pci;
6512 if (pdev->device == 0x4328 ||
6513 pdev->device == 0x432a)
6514 nphy->pwg_gain_5ghz = true;
6515 }
6516 #endif
6517 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
6518 nphy->pwg_gain_5ghz = true;
6519 }
6520 }
6521
6522 if (dev->phy.rev >= 3) {
6523 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
6524 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
6525 }
6526 }
6527
6528 static void b43_nphy_op_free(struct b43_wldev *dev)
6529 {
6530 struct b43_phy *phy = &dev->phy;
6531 struct b43_phy_n *nphy = phy->n;
6532
6533 kfree(nphy);
6534 phy->n = NULL;
6535 }
6536
6537 static int b43_nphy_op_init(struct b43_wldev *dev)
6538 {
6539 return b43_phy_initn(dev);
6540 }
6541
6542 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
6543 {
6544 #if B43_DEBUG
6545 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
6546
6547 b43err(dev->wl, "Invalid OFDM PHY access at "
6548 "0x%04X on N-PHY\n", offset);
6549 dump_stack();
6550 }
6551 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
6552
6553 b43err(dev->wl, "Invalid EXT-G PHY access at "
6554 "0x%04X on N-PHY\n", offset);
6555 dump_stack();
6556 }
6557 #endif
6558 }
6559
6560 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
6561 u16 set)
6562 {
6563 check_phyreg(dev, reg);
6564 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
6565 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
6566 dev->phy.writes_counter = 1;
6567 }
6568
6569 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
6570 {
6571
6572 B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
6573
6574 if (dev->phy.rev >= 7)
6575 reg |= 0x200;
6576 else
6577 reg |= 0x100;
6578
6579 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
6580 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
6581 }
6582
6583 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
6584 {
6585
6586 B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
6587
6588 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
6589 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
6590 }
6591
6592
6593 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
6594 bool blocked)
6595 {
6596 struct b43_phy *phy = &dev->phy;
6597
6598 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
6599 b43err(dev->wl, "MAC not suspended\n");
6600
6601 if (blocked) {
6602 if (phy->rev >= 19) {
6603
6604 } else if (phy->rev >= 8) {
6605 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6606 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
6607 } else if (phy->rev >= 7) {
6608
6609 } else if (phy->rev >= 3) {
6610 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6611 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
6612
6613 b43_radio_mask(dev, 0x09, ~0x2);
6614
6615 b43_radio_write(dev, 0x204D, 0);
6616 b43_radio_write(dev, 0x2053, 0);
6617 b43_radio_write(dev, 0x2058, 0);
6618 b43_radio_write(dev, 0x205E, 0);
6619 b43_radio_mask(dev, 0x2062, ~0xF0);
6620 b43_radio_write(dev, 0x2064, 0);
6621
6622 b43_radio_write(dev, 0x304D, 0);
6623 b43_radio_write(dev, 0x3053, 0);
6624 b43_radio_write(dev, 0x3058, 0);
6625 b43_radio_write(dev, 0x305E, 0);
6626 b43_radio_mask(dev, 0x3062, ~0xF0);
6627 b43_radio_write(dev, 0x3064, 0);
6628 }
6629 } else {
6630 if (phy->rev >= 19) {
6631
6632 } else if (phy->rev >= 7) {
6633 if (!dev->phy.radio_on)
6634 b43_radio_2057_init(dev);
6635 b43_switch_channel(dev, dev->phy.channel);
6636 } else if (phy->rev >= 3) {
6637 if (!dev->phy.radio_on)
6638 b43_radio_init2056(dev);
6639 b43_switch_channel(dev, dev->phy.channel);
6640 } else {
6641 b43_radio_init2055(dev);
6642 }
6643 }
6644 }
6645
6646
6647 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
6648 {
6649 struct b43_phy *phy = &dev->phy;
6650 u16 override = on ? 0x0 : 0x7FFF;
6651 u16 core = on ? 0xD : 0x00FD;
6652
6653 if (phy->rev >= 19) {
6654
6655 } else if (phy->rev >= 3) {
6656 if (on) {
6657 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6658 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6659 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6660 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6661 } else {
6662 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6663 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6664 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6665 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6666 }
6667 } else {
6668 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6669 }
6670 }
6671
6672 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
6673 unsigned int new_channel)
6674 {
6675 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
6676 enum nl80211_channel_type channel_type =
6677 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
6678
6679 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
6680 if ((new_channel < 1) || (new_channel > 14))
6681 return -EINVAL;
6682 } else {
6683 if (new_channel > 200)
6684 return -EINVAL;
6685 }
6686
6687 return b43_nphy_set_channel(dev, channel, channel_type);
6688 }
6689
6690 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
6691 {
6692 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
6693 return 1;
6694 return 36;
6695 }
6696
6697 const struct b43_phy_operations b43_phyops_n = {
6698 .allocate = b43_nphy_op_allocate,
6699 .free = b43_nphy_op_free,
6700 .prepare_structs = b43_nphy_op_prepare_structs,
6701 .init = b43_nphy_op_init,
6702 .phy_maskset = b43_nphy_op_maskset,
6703 .radio_read = b43_nphy_op_radio_read,
6704 .radio_write = b43_nphy_op_radio_write,
6705 .software_rfkill = b43_nphy_op_software_rfkill,
6706 .switch_analog = b43_nphy_op_switch_analog,
6707 .switch_channel = b43_nphy_op_switch_channel,
6708 .get_default_chan = b43_nphy_op_get_default_chan,
6709 .recalc_txpower = b43_nphy_op_recalc_txpower,
6710 };