root/drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_ipc.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (c) 2018 Quantenna Communications */
   3 
   4 #ifndef _QTN_FMAC_PCIE_IPC_H_
   5 #define _QTN_FMAC_PCIE_IPC_H_
   6 
   7 #include <linux/types.h>
   8 
   9 #include "shm_ipc_defs.h"
  10 
  11 /* EP/RC status and flags */
  12 #define QTN_BDA_PCIE_INIT               0x01
  13 #define QTN_BDA_PCIE_RDY                0x02
  14 #define QTN_BDA_FW_LOAD_RDY             0x03
  15 #define QTN_BDA_FW_LOAD_DONE            0x04
  16 #define QTN_BDA_FW_START                0x05
  17 #define QTN_BDA_FW_RUN                  0x06
  18 #define QTN_BDA_FW_HOST_RDY             0x07
  19 #define QTN_BDA_FW_TARGET_RDY           0x11
  20 #define QTN_BDA_FW_TARGET_BOOT          0x12
  21 #define QTN_BDA_FW_FLASH_BOOT           0x13
  22 #define QTN_BDA_FW_QLINK_DONE           0x14
  23 #define QTN_BDA_FW_HOST_LOAD            0x08
  24 #define QTN_BDA_FW_BLOCK_DONE           0x09
  25 #define QTN_BDA_FW_BLOCK_RDY            0x0A
  26 #define QTN_BDA_FW_EP_RDY               0x0B
  27 #define QTN_BDA_FW_BLOCK_END            0x0C
  28 #define QTN_BDA_FW_CONFIG               0x0D
  29 #define QTN_BDA_FW_RUNNING              0x0E
  30 #define QTN_BDA_PCIE_FAIL               0x82
  31 #define QTN_BDA_FW_LOAD_FAIL            0x85
  32 
  33 #define QTN_BDA_RCMODE                  BIT(1)
  34 #define QTN_BDA_MSI                     BIT(2)
  35 #define QTN_BDA_HOST_CALCMD             BIT(3)
  36 #define QTN_BDA_FLASH_PRESENT           BIT(4)
  37 #define QTN_BDA_FLASH_BOOT              BIT(5)
  38 #define QTN_BDA_XMIT_UBOOT              BIT(6)
  39 #define QTN_BDA_HOST_QLINK_DRV          BIT(7)
  40 #define QTN_BDA_TARGET_FBOOT_ERR        BIT(8)
  41 #define QTN_BDA_TARGET_FWLOAD_ERR       BIT(9)
  42 #define QTN_BDA_HOST_NOFW_ERR           BIT(12)
  43 #define QTN_BDA_HOST_MEMALLOC_ERR       BIT(13)
  44 #define QTN_BDA_HOST_MEMMAP_ERR         BIT(14)
  45 #define QTN_BDA_VER(x)                  (((x) >> 4) & 0xFF)
  46 #define QTN_BDA_ERROR_MASK              0xFF00
  47 
  48 /* registers and shmem address macros */
  49 #if BITS_PER_LONG == 64
  50 #define QTN_HOST_HI32(a)        ((u32)(((u64)a) >> 32))
  51 #define QTN_HOST_LO32(a)        ((u32)(((u64)a) & 0xffffffffUL))
  52 #define QTN_HOST_ADDR(h, l)     ((((u64)h) << 32) | ((u64)l))
  53 #elif BITS_PER_LONG == 32
  54 #define QTN_HOST_HI32(a)        0
  55 #define QTN_HOST_LO32(a)        ((u32)(((u32)a) & 0xffffffffUL))
  56 #define QTN_HOST_ADDR(h, l)     ((u32)l)
  57 #else
  58 #error Unexpected BITS_PER_LONG value
  59 #endif
  60 
  61 #define QTN_PCIE_BDA_VERSION            0x1001
  62 
  63 #define PCIE_BDA_NAMELEN                32
  64 
  65 #define QTN_PCIE_RC_TX_QUEUE_LEN        256
  66 #define QTN_PCIE_TX_VALID_PKT           0x80000000
  67 #define QTN_PCIE_PKT_LEN_MASK           0xffff
  68 
  69 #define QTN_BD_EMPTY            ((uint32_t)0x00000001)
  70 #define QTN_BD_WRAP             ((uint32_t)0x00000002)
  71 #define QTN_BD_MASK_LEN         ((uint32_t)0xFFFF0000)
  72 #define QTN_BD_MASK_OFFSET      ((uint32_t)0x0000FF00)
  73 
  74 #define QTN_GET_LEN(x)          (((x) >> 16) & 0xFFFF)
  75 #define QTN_GET_OFFSET(x)       (((x) >> 8) & 0xFF)
  76 #define QTN_SET_LEN(len)        (((len) & 0xFFFF) << 16)
  77 #define QTN_SET_OFFSET(of)      (((of) & 0xFF) << 8)
  78 
  79 #define RX_DONE_INTR_MSK        ((0x1 << 6) - 1)
  80 
  81 #define PCIE_DMA_OFFSET_ERROR           0xFFFF
  82 #define PCIE_DMA_OFFSET_ERROR_MASK      0xFFFF
  83 
  84 #define QTN_PCI_ENDIAN_DETECT_DATA      0x12345678
  85 #define QTN_PCI_ENDIAN_REVERSE_DATA     0x78563412
  86 #define QTN_PCI_ENDIAN_VALID_STATUS     0x3c3c3c3c
  87 #define QTN_PCI_ENDIAN_INVALID_STATUS   0
  88 #define QTN_PCI_LITTLE_ENDIAN           0
  89 #define QTN_PCI_BIG_ENDIAN              0xffffffff
  90 
  91 #define NBLOCKS(size, blksize)          \
  92         ((size) / (blksize) + (((size) % (blksize) > 0) ? 1 : 0))
  93 
  94 #endif /* _QTN_FMAC_PCIE_IPC_H_ */

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